1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include "i915_drv.h"
26 #include "intel_ringbuffer.h"
27 #include "intel_lrc.h"
28
29 static const struct engine_info {
30 const char *name;
31 unsigned exec_id;
32 enum intel_engine_hw_id hw_id;
33 u32 mmio_base;
34 unsigned irq_shift;
35 int (*init_legacy)(struct intel_engine_cs *engine);
36 int (*init_execlists)(struct intel_engine_cs *engine);
37 } intel_engines[] = {
38 [RCS] = {
39 .name = "render ring",
40 .exec_id = I915_EXEC_RENDER,
41 .hw_id = RCS_HW,
42 .mmio_base = RENDER_RING_BASE,
43 .irq_shift = GEN8_RCS_IRQ_SHIFT,
44 .init_execlists = logical_render_ring_init,
45 .init_legacy = intel_init_render_ring_buffer,
46 },
47 [BCS] = {
48 .name = "blitter ring",
49 .exec_id = I915_EXEC_BLT,
50 .hw_id = BCS_HW,
51 .mmio_base = BLT_RING_BASE,
52 .irq_shift = GEN8_BCS_IRQ_SHIFT,
53 .init_execlists = logical_xcs_ring_init,
54 .init_legacy = intel_init_blt_ring_buffer,
55 },
56 [VCS] = {
57 .name = "bsd ring",
58 .exec_id = I915_EXEC_BSD,
59 .hw_id = VCS_HW,
60 .mmio_base = GEN6_BSD_RING_BASE,
61 .irq_shift = GEN8_VCS1_IRQ_SHIFT,
62 .init_execlists = logical_xcs_ring_init,
63 .init_legacy = intel_init_bsd_ring_buffer,
64 },
65 [VCS2] = {
66 .name = "bsd2 ring",
67 .exec_id = I915_EXEC_BSD,
68 .hw_id = VCS2_HW,
69 .mmio_base = GEN8_BSD2_RING_BASE,
70 .irq_shift = GEN8_VCS2_IRQ_SHIFT,
71 .init_execlists = logical_xcs_ring_init,
72 .init_legacy = intel_init_bsd2_ring_buffer,
73 },
74 [VECS] = {
75 .name = "video enhancement ring",
76 .exec_id = I915_EXEC_VEBOX,
77 .hw_id = VECS_HW,
78 .mmio_base = VEBOX_RING_BASE,
79 .irq_shift = GEN8_VECS_IRQ_SHIFT,
80 .init_execlists = logical_xcs_ring_init,
81 .init_legacy = intel_init_vebox_ring_buffer,
82 },
83 };
84
85 static struct intel_engine_cs *
intel_engine_setup(struct drm_i915_private * dev_priv,enum intel_engine_id id)86 intel_engine_setup(struct drm_i915_private *dev_priv,
87 enum intel_engine_id id)
88 {
89 const struct engine_info *info = &intel_engines[id];
90 struct intel_engine_cs *engine = &dev_priv->engine[id];
91
92 engine->id = id;
93 engine->i915 = dev_priv;
94 engine->name = info->name;
95 engine->exec_id = info->exec_id;
96 engine->hw_id = engine->guc_id = info->hw_id;
97 engine->mmio_base = info->mmio_base;
98 engine->irq_shift = info->irq_shift;
99
100 return engine;
101 }
102
103 /**
104 * intel_engines_init() - allocate, populate and init the Engine Command Streamers
105 * @dev: DRM device.
106 *
107 * Return: non-zero if the initialization failed.
108 */
intel_engines_init(struct drm_device * dev)109 int intel_engines_init(struct drm_device *dev)
110 {
111 struct drm_i915_private *dev_priv = to_i915(dev);
112 struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
113 unsigned int mask = 0;
114 int (*init)(struct intel_engine_cs *engine);
115 unsigned int i;
116 int ret;
117
118 WARN_ON(INTEL_INFO(dev_priv)->ring_mask == 0);
119 WARN_ON(INTEL_INFO(dev_priv)->ring_mask &
120 GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
121
122 for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
123 if (!HAS_ENGINE(dev_priv, i))
124 continue;
125
126 if (i915.enable_execlists)
127 init = intel_engines[i].init_execlists;
128 else
129 init = intel_engines[i].init_legacy;
130
131 if (!init)
132 continue;
133
134 ret = init(intel_engine_setup(dev_priv, i));
135 if (ret)
136 goto cleanup;
137
138 mask |= ENGINE_MASK(i);
139 }
140
141 /*
142 * Catch failures to update intel_engines table when the new engines
143 * are added to the driver by a warning and disabling the forgotten
144 * engines.
145 */
146 if (WARN_ON(mask != INTEL_INFO(dev_priv)->ring_mask))
147 device_info->ring_mask = mask;
148
149 device_info->num_rings = hweight32(mask);
150
151 return 0;
152
153 cleanup:
154 for (i = 0; i < I915_NUM_ENGINES; i++) {
155 if (i915.enable_execlists)
156 intel_logical_ring_cleanup(&dev_priv->engine[i]);
157 else
158 intel_engine_cleanup(&dev_priv->engine[i]);
159 }
160
161 return ret;
162 }
163
intel_engine_init_seqno(struct intel_engine_cs * engine,u32 seqno)164 void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno)
165 {
166 struct drm_i915_private *dev_priv = engine->i915;
167
168 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
169 * so long as the semaphore value in the register/page is greater
170 * than the sync value), so whenever we reset the seqno,
171 * so long as we reset the tracking semaphore value to 0, it will
172 * always be before the next request's seqno. If we don't reset
173 * the semaphore value, then when the seqno moves backwards all
174 * future waits will complete instantly (causing rendering corruption).
175 */
176 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
177 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
178 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
179 if (HAS_VEBOX(dev_priv))
180 I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
181 }
182 if (dev_priv->semaphore) {
183 struct page *page = i915_vma_first_page(dev_priv->semaphore);
184 void *semaphores;
185
186 /* Semaphores are in noncoherent memory, flush to be safe */
187 semaphores = kmap(page);
188 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
189 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
190 drm_clflush_virt_range(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
191 I915_NUM_ENGINES * gen8_semaphore_seqno_size);
192 kunmap(page);
193 }
194 memset(engine->semaphore.sync_seqno, 0,
195 sizeof(engine->semaphore.sync_seqno));
196
197 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
198 if (engine->irq_seqno_barrier)
199 engine->irq_seqno_barrier(engine);
200 engine->last_submitted_seqno = seqno;
201
202 engine->hangcheck.seqno = seqno;
203
204 /* After manually advancing the seqno, fake the interrupt in case
205 * there are any waiters for that seqno.
206 */
207 intel_engine_wakeup(engine);
208 }
209
intel_engine_init_hangcheck(struct intel_engine_cs * engine)210 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
211 {
212 memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
213 }
214
intel_engine_init_requests(struct intel_engine_cs * engine)215 static void intel_engine_init_requests(struct intel_engine_cs *engine)
216 {
217 init_request_active(&engine->last_request, NULL);
218 INIT_LIST_HEAD(&engine->request_list);
219 }
220
221 /**
222 * intel_engines_setup_common - setup engine state not requiring hw access
223 * @engine: Engine to setup.
224 *
225 * Initializes @engine@ structure members shared between legacy and execlists
226 * submission modes which do not require hardware access.
227 *
228 * Typically done early in the submission mode specific engine setup stage.
229 */
intel_engine_setup_common(struct intel_engine_cs * engine)230 void intel_engine_setup_common(struct intel_engine_cs *engine)
231 {
232 INIT_LIST_HEAD(&engine->execlist_queue);
233 spin_lock_init(&engine->execlist_lock);
234
235 engine->fence_context = fence_context_alloc(1);
236
237 intel_engine_init_requests(engine);
238 intel_engine_init_hangcheck(engine);
239 i915_gem_batch_pool_init(engine, &engine->batch_pool);
240
241 intel_engine_init_cmd_parser(engine);
242 }
243
intel_engine_create_scratch(struct intel_engine_cs * engine,int size)244 int intel_engine_create_scratch(struct intel_engine_cs *engine, int size)
245 {
246 struct drm_i915_gem_object *obj;
247 struct i915_vma *vma;
248 int ret;
249
250 WARN_ON(engine->scratch);
251
252 obj = i915_gem_object_create_stolen(&engine->i915->drm, size);
253 if (!obj)
254 obj = i915_gem_object_create(&engine->i915->drm, size);
255 if (IS_ERR(obj)) {
256 DRM_ERROR("Failed to allocate scratch page\n");
257 return PTR_ERR(obj);
258 }
259
260 vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL);
261 if (IS_ERR(vma)) {
262 ret = PTR_ERR(vma);
263 goto err_unref;
264 }
265
266 ret = i915_vma_pin(vma, 0, 4096, PIN_GLOBAL | PIN_HIGH);
267 if (ret)
268 goto err_unref;
269
270 engine->scratch = vma;
271 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
272 engine->name, i915_ggtt_offset(vma));
273 return 0;
274
275 err_unref:
276 i915_gem_object_put(obj);
277 return ret;
278 }
279
intel_engine_cleanup_scratch(struct intel_engine_cs * engine)280 static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
281 {
282 i915_vma_unpin_and_release(&engine->scratch);
283 }
284
285 /**
286 * intel_engines_init_common - initialize cengine state which might require hw access
287 * @engine: Engine to initialize.
288 *
289 * Initializes @engine@ structure members shared between legacy and execlists
290 * submission modes which do require hardware access.
291 *
292 * Typcally done at later stages of submission mode specific engine setup.
293 *
294 * Returns zero on success or an error code on failure.
295 */
intel_engine_init_common(struct intel_engine_cs * engine)296 int intel_engine_init_common(struct intel_engine_cs *engine)
297 {
298 int ret;
299
300 ret = intel_engine_init_breadcrumbs(engine);
301 if (ret)
302 return ret;
303
304 return 0;
305 }
306
307 /**
308 * intel_engines_cleanup_common - cleans up the engine state created by
309 * the common initiailizers.
310 * @engine: Engine to cleanup.
311 *
312 * This cleans up everything created by the common helpers.
313 */
intel_engine_cleanup_common(struct intel_engine_cs * engine)314 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
315 {
316 intel_engine_cleanup_scratch(engine);
317
318 intel_engine_fini_breadcrumbs(engine);
319 intel_engine_cleanup_cmd_parser(engine);
320 i915_gem_batch_pool_fini(&engine->batch_pool);
321 }
322