1 /*
2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
4 *
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
6 *
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 * Module name: htab.c
11 *
12 * Description:
13 * PowerPC Hashed Page Table functions
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21 #undef DEBUG
22 #undef DEBUG_LOW
23
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
36 #include <linux/context_tracking.h>
37 #include <linux/libfdt.h>
38
39 #include <asm/processor.h>
40 #include <asm/pgtable.h>
41 #include <asm/mmu.h>
42 #include <asm/mmu_context.h>
43 #include <asm/page.h>
44 #include <asm/types.h>
45 #include <asm/uaccess.h>
46 #include <asm/machdep.h>
47 #include <asm/prom.h>
48 #include <asm/tlbflush.h>
49 #include <asm/io.h>
50 #include <asm/eeh.h>
51 #include <asm/tlb.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/sections.h>
55 #include <asm/copro.h>
56 #include <asm/udbg.h>
57 #include <asm/code-patching.h>
58 #include <asm/fadump.h>
59 #include <asm/firmware.h>
60 #include <asm/tm.h>
61 #include <asm/trace.h>
62 #include <asm/ps3.h>
63
64 #ifdef DEBUG
65 #define DBG(fmt...) udbg_printf(fmt)
66 #else
67 #define DBG(fmt...)
68 #endif
69
70 #ifdef DEBUG_LOW
71 #define DBG_LOW(fmt...) udbg_printf(fmt)
72 #else
73 #define DBG_LOW(fmt...)
74 #endif
75
76 #define KB (1024)
77 #define MB (1024*KB)
78 #define GB (1024L*MB)
79
80 /*
81 * Note: pte --> Linux PTE
82 * HPTE --> PowerPC Hashed Page Table Entry
83 *
84 * Execution context:
85 * htab_initialize is called with the MMU off (of course), but
86 * the kernel has been copied down to zero so it can directly
87 * reference global data. At this point it is very difficult
88 * to print debug info.
89 *
90 */
91
92 static unsigned long _SDR1;
93 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
94 EXPORT_SYMBOL_GPL(mmu_psize_defs);
95
96 u8 hpte_page_sizes[1 << LP_BITS];
97 EXPORT_SYMBOL_GPL(hpte_page_sizes);
98
99 struct hash_pte *htab_address;
100 unsigned long htab_size_bytes;
101 unsigned long htab_hash_mask;
102 EXPORT_SYMBOL_GPL(htab_hash_mask);
103 int mmu_linear_psize = MMU_PAGE_4K;
104 EXPORT_SYMBOL_GPL(mmu_linear_psize);
105 int mmu_virtual_psize = MMU_PAGE_4K;
106 int mmu_vmalloc_psize = MMU_PAGE_4K;
107 #ifdef CONFIG_SPARSEMEM_VMEMMAP
108 int mmu_vmemmap_psize = MMU_PAGE_4K;
109 #endif
110 int mmu_io_psize = MMU_PAGE_4K;
111 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
112 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
113 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
114 u16 mmu_slb_size = 64;
115 EXPORT_SYMBOL_GPL(mmu_slb_size);
116 #ifdef CONFIG_PPC_64K_PAGES
117 int mmu_ci_restrictions;
118 #endif
119 #ifdef CONFIG_DEBUG_PAGEALLOC
120 static u8 *linear_map_hash_slots;
121 static unsigned long linear_map_hash_count;
122 static DEFINE_SPINLOCK(linear_map_hash_lock);
123 #endif /* CONFIG_DEBUG_PAGEALLOC */
124 struct mmu_hash_ops mmu_hash_ops;
125 EXPORT_SYMBOL(mmu_hash_ops);
126
127 /* There are definitions of page sizes arrays to be used when none
128 * is provided by the firmware.
129 */
130
131 /* Pre-POWER4 CPUs (4k pages only)
132 */
133 static struct mmu_psize_def mmu_psize_defaults_old[] = {
134 [MMU_PAGE_4K] = {
135 .shift = 12,
136 .sllp = 0,
137 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
138 .avpnm = 0,
139 .tlbiel = 0,
140 },
141 };
142
143 /* POWER4, GPUL, POWER5
144 *
145 * Support for 16Mb large pages
146 */
147 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
148 [MMU_PAGE_4K] = {
149 .shift = 12,
150 .sllp = 0,
151 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
152 .avpnm = 0,
153 .tlbiel = 1,
154 },
155 [MMU_PAGE_16M] = {
156 .shift = 24,
157 .sllp = SLB_VSID_L,
158 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
159 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
160 .avpnm = 0x1UL,
161 .tlbiel = 0,
162 },
163 };
164
165 /*
166 * 'R' and 'C' update notes:
167 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
168 * create writeable HPTEs without C set, because the hcall H_PROTECT
169 * that we use in that case will not update C
170 * - The above is however not a problem, because we also don't do that
171 * fancy "no flush" variant of eviction and we use H_REMOVE which will
172 * do the right thing and thus we don't have the race I described earlier
173 *
174 * - Under bare metal, we do have the race, so we need R and C set
175 * - We make sure R is always set and never lost
176 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
177 */
htab_convert_pte_flags(unsigned long pteflags)178 unsigned long htab_convert_pte_flags(unsigned long pteflags)
179 {
180 unsigned long rflags = 0;
181
182 /* _PAGE_EXEC -> NOEXEC */
183 if ((pteflags & _PAGE_EXEC) == 0)
184 rflags |= HPTE_R_N;
185 /*
186 * PPP bits:
187 * Linux uses slb key 0 for kernel and 1 for user.
188 * kernel RW areas are mapped with PPP=0b000
189 * User area is mapped with PPP=0b010 for read/write
190 * or PPP=0b011 for read-only (including writeable but clean pages).
191 */
192 if (pteflags & _PAGE_PRIVILEGED) {
193 /*
194 * Kernel read only mapped with ppp bits 0b110
195 */
196 if (!(pteflags & _PAGE_WRITE)) {
197 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
198 rflags |= (HPTE_R_PP0 | 0x2);
199 else
200 rflags |= 0x3;
201 }
202 } else {
203 if (pteflags & _PAGE_RWX)
204 rflags |= 0x2;
205 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
206 rflags |= 0x1;
207 }
208 /*
209 * We can't allow hardware to update hpte bits. Hence always
210 * set 'R' bit and set 'C' if it is a write fault
211 */
212 rflags |= HPTE_R_R;
213
214 if (pteflags & _PAGE_DIRTY)
215 rflags |= HPTE_R_C;
216 /*
217 * Add in WIG bits
218 */
219
220 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
221 rflags |= HPTE_R_I;
222 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
223 rflags |= (HPTE_R_I | HPTE_R_G);
224 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
225 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
226 else
227 /*
228 * Add memory coherence if cache inhibited is not set
229 */
230 rflags |= HPTE_R_M;
231
232 return rflags;
233 }
234
htab_bolt_mapping(unsigned long vstart,unsigned long vend,unsigned long pstart,unsigned long prot,int psize,int ssize)235 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
236 unsigned long pstart, unsigned long prot,
237 int psize, int ssize)
238 {
239 unsigned long vaddr, paddr;
240 unsigned int step, shift;
241 int ret = 0;
242
243 shift = mmu_psize_defs[psize].shift;
244 step = 1 << shift;
245
246 prot = htab_convert_pte_flags(prot);
247
248 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
249 vstart, vend, pstart, prot, psize, ssize);
250
251 for (vaddr = vstart, paddr = pstart; vaddr < vend;
252 vaddr += step, paddr += step) {
253 unsigned long hash, hpteg;
254 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
255 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
256 unsigned long tprot = prot;
257
258 /*
259 * If we hit a bad address return error.
260 */
261 if (!vsid)
262 return -1;
263 /* Make kernel text executable */
264 if (overlaps_kernel_text(vaddr, vaddr + step))
265 tprot &= ~HPTE_R_N;
266
267 /* Make kvm guest trampolines executable */
268 if (overlaps_kvm_tmp(vaddr, vaddr + step))
269 tprot &= ~HPTE_R_N;
270
271 /*
272 * If relocatable, check if it overlaps interrupt vectors that
273 * are copied down to real 0. For relocatable kernel
274 * (e.g. kdump case) we copy interrupt vectors down to real
275 * address 0. Mark that region as executable. This is
276 * because on p8 system with relocation on exception feature
277 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
278 * in order to execute the interrupt handlers in virtual
279 * mode the vector region need to be marked as executable.
280 */
281 if ((PHYSICAL_START > MEMORY_START) &&
282 overlaps_interrupt_vector_text(vaddr, vaddr + step))
283 tprot &= ~HPTE_R_N;
284
285 hash = hpt_hash(vpn, shift, ssize);
286 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
287
288 BUG_ON(!mmu_hash_ops.hpte_insert);
289 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
290 HPTE_V_BOLTED, psize, psize,
291 ssize);
292
293 if (ret < 0)
294 break;
295
296 #ifdef CONFIG_DEBUG_PAGEALLOC
297 if (debug_pagealloc_enabled() &&
298 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
299 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
300 #endif /* CONFIG_DEBUG_PAGEALLOC */
301 }
302 return ret < 0 ? ret : 0;
303 }
304
htab_remove_mapping(unsigned long vstart,unsigned long vend,int psize,int ssize)305 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
306 int psize, int ssize)
307 {
308 unsigned long vaddr;
309 unsigned int step, shift;
310 int rc;
311 int ret = 0;
312
313 shift = mmu_psize_defs[psize].shift;
314 step = 1 << shift;
315
316 if (!mmu_hash_ops.hpte_removebolted)
317 return -ENODEV;
318
319 for (vaddr = vstart; vaddr < vend; vaddr += step) {
320 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
321 if (rc == -ENOENT) {
322 ret = -ENOENT;
323 continue;
324 }
325 if (rc < 0)
326 return rc;
327 }
328
329 return ret;
330 }
331
332 static bool disable_1tb_segments = false;
333
parse_disable_1tb_segments(char * p)334 static int __init parse_disable_1tb_segments(char *p)
335 {
336 disable_1tb_segments = true;
337 return 0;
338 }
339 early_param("disable_1tb_segments", parse_disable_1tb_segments);
340
htab_dt_scan_seg_sizes(unsigned long node,const char * uname,int depth,void * data)341 static int __init htab_dt_scan_seg_sizes(unsigned long node,
342 const char *uname, int depth,
343 void *data)
344 {
345 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
346 const __be32 *prop;
347 int size = 0;
348
349 /* We are scanning "cpu" nodes only */
350 if (type == NULL || strcmp(type, "cpu") != 0)
351 return 0;
352
353 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
354 if (prop == NULL)
355 return 0;
356 for (; size >= 4; size -= 4, ++prop) {
357 if (be32_to_cpu(prop[0]) == 40) {
358 DBG("1T segment support detected\n");
359
360 if (disable_1tb_segments) {
361 DBG("1T segments disabled by command line\n");
362 break;
363 }
364
365 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
366 return 1;
367 }
368 }
369 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
370 return 0;
371 }
372
get_idx_from_shift(unsigned int shift)373 static int __init get_idx_from_shift(unsigned int shift)
374 {
375 int idx = -1;
376
377 switch (shift) {
378 case 0xc:
379 idx = MMU_PAGE_4K;
380 break;
381 case 0x10:
382 idx = MMU_PAGE_64K;
383 break;
384 case 0x14:
385 idx = MMU_PAGE_1M;
386 break;
387 case 0x18:
388 idx = MMU_PAGE_16M;
389 break;
390 case 0x22:
391 idx = MMU_PAGE_16G;
392 break;
393 }
394 return idx;
395 }
396
htab_dt_scan_page_sizes(unsigned long node,const char * uname,int depth,void * data)397 static int __init htab_dt_scan_page_sizes(unsigned long node,
398 const char *uname, int depth,
399 void *data)
400 {
401 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
402 const __be32 *prop;
403 int size = 0;
404
405 /* We are scanning "cpu" nodes only */
406 if (type == NULL || strcmp(type, "cpu") != 0)
407 return 0;
408
409 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
410 if (!prop)
411 return 0;
412
413 pr_info("Page sizes from device-tree:\n");
414 size /= 4;
415 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
416 while(size > 0) {
417 unsigned int base_shift = be32_to_cpu(prop[0]);
418 unsigned int slbenc = be32_to_cpu(prop[1]);
419 unsigned int lpnum = be32_to_cpu(prop[2]);
420 struct mmu_psize_def *def;
421 int idx, base_idx;
422
423 size -= 3; prop += 3;
424 base_idx = get_idx_from_shift(base_shift);
425 if (base_idx < 0) {
426 /* skip the pte encoding also */
427 prop += lpnum * 2; size -= lpnum * 2;
428 continue;
429 }
430 def = &mmu_psize_defs[base_idx];
431 if (base_idx == MMU_PAGE_16M)
432 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
433
434 def->shift = base_shift;
435 if (base_shift <= 23)
436 def->avpnm = 0;
437 else
438 def->avpnm = (1 << (base_shift - 23)) - 1;
439 def->sllp = slbenc;
440 /*
441 * We don't know for sure what's up with tlbiel, so
442 * for now we only set it for 4K and 64K pages
443 */
444 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
445 def->tlbiel = 1;
446 else
447 def->tlbiel = 0;
448
449 while (size > 0 && lpnum) {
450 unsigned int shift = be32_to_cpu(prop[0]);
451 int penc = be32_to_cpu(prop[1]);
452
453 prop += 2; size -= 2;
454 lpnum--;
455
456 idx = get_idx_from_shift(shift);
457 if (idx < 0)
458 continue;
459
460 if (penc == -1)
461 pr_err("Invalid penc for base_shift=%d "
462 "shift=%d\n", base_shift, shift);
463
464 def->penc[idx] = penc;
465 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
466 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
467 base_shift, shift, def->sllp,
468 def->avpnm, def->tlbiel, def->penc[idx]);
469 }
470 }
471
472 return 1;
473 }
474
475 #ifdef CONFIG_HUGETLB_PAGE
476 /* Scan for 16G memory blocks that have been set aside for huge pages
477 * and reserve those blocks for 16G huge pages.
478 */
htab_dt_scan_hugepage_blocks(unsigned long node,const char * uname,int depth,void * data)479 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
480 const char *uname, int depth,
481 void *data) {
482 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
483 const __be64 *addr_prop;
484 const __be32 *page_count_prop;
485 unsigned int expected_pages;
486 long unsigned int phys_addr;
487 long unsigned int block_size;
488
489 /* We are scanning "memory" nodes only */
490 if (type == NULL || strcmp(type, "memory") != 0)
491 return 0;
492
493 /* This property is the log base 2 of the number of virtual pages that
494 * will represent this memory block. */
495 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
496 if (page_count_prop == NULL)
497 return 0;
498 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
499 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
500 if (addr_prop == NULL)
501 return 0;
502 phys_addr = be64_to_cpu(addr_prop[0]);
503 block_size = be64_to_cpu(addr_prop[1]);
504 if (block_size != (16 * GB))
505 return 0;
506 printk(KERN_INFO "Huge page(16GB) memory: "
507 "addr = 0x%lX size = 0x%lX pages = %d\n",
508 phys_addr, block_size, expected_pages);
509 if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
510 memblock_reserve(phys_addr, block_size * expected_pages);
511 add_gpage(phys_addr, block_size, expected_pages);
512 }
513 return 0;
514 }
515 #endif /* CONFIG_HUGETLB_PAGE */
516
mmu_psize_set_default_penc(void)517 static void mmu_psize_set_default_penc(void)
518 {
519 int bpsize, apsize;
520 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
521 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
522 mmu_psize_defs[bpsize].penc[apsize] = -1;
523 }
524
525 #ifdef CONFIG_PPC_64K_PAGES
526
might_have_hea(void)527 static bool might_have_hea(void)
528 {
529 /*
530 * The HEA ethernet adapter requires awareness of the
531 * GX bus. Without that awareness we can easily assume
532 * we will never see an HEA ethernet device.
533 */
534 #ifdef CONFIG_IBMEBUS
535 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
536 firmware_has_feature(FW_FEATURE_SPLPAR);
537 #else
538 return false;
539 #endif
540 }
541
542 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
543
htab_scan_page_sizes(void)544 static void __init htab_scan_page_sizes(void)
545 {
546 int rc;
547
548 /* se the invalid penc to -1 */
549 mmu_psize_set_default_penc();
550
551 /* Default to 4K pages only */
552 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
553 sizeof(mmu_psize_defaults_old));
554
555 /*
556 * Try to find the available page sizes in the device-tree
557 */
558 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
559 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
560 /*
561 * Nothing in the device-tree, but the CPU supports 16M pages,
562 * so let's fallback on a known size list for 16M capable CPUs.
563 */
564 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
565 sizeof(mmu_psize_defaults_gp));
566 }
567
568 #ifdef CONFIG_HUGETLB_PAGE
569 /* Reserve 16G huge page memory sections for huge pages */
570 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
571 #endif /* CONFIG_HUGETLB_PAGE */
572 }
573
574 /*
575 * Fill in the hpte_page_sizes[] array.
576 * We go through the mmu_psize_defs[] array looking for all the
577 * supported base/actual page size combinations. Each combination
578 * has a unique pagesize encoding (penc) value in the low bits of
579 * the LP field of the HPTE. For actual page sizes less than 1MB,
580 * some of the upper LP bits are used for RPN bits, meaning that
581 * we need to fill in several entries in hpte_page_sizes[].
582 *
583 * In diagrammatic form, with r = RPN bits and z = page size bits:
584 * PTE LP actual page size
585 * rrrr rrrz >=8KB
586 * rrrr rrzz >=16KB
587 * rrrr rzzz >=32KB
588 * rrrr zzzz >=64KB
589 * ...
590 *
591 * The zzzz bits are implementation-specific but are chosen so that
592 * no encoding for a larger page size uses the same value in its
593 * low-order N bits as the encoding for the 2^(12+N) byte page size
594 * (if it exists).
595 */
init_hpte_page_sizes(void)596 static void init_hpte_page_sizes(void)
597 {
598 long int ap, bp;
599 long int shift, penc;
600
601 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
602 if (!mmu_psize_defs[bp].shift)
603 continue; /* not a supported page size */
604 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
605 penc = mmu_psize_defs[bp].penc[ap];
606 if (penc == -1)
607 continue;
608 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
609 if (shift <= 0)
610 continue; /* should never happen */
611 /*
612 * For page sizes less than 1MB, this loop
613 * replicates the entry for all possible values
614 * of the rrrr bits.
615 */
616 while (penc < (1 << LP_BITS)) {
617 hpte_page_sizes[penc] = (ap << 4) | bp;
618 penc += 1 << shift;
619 }
620 }
621 }
622 }
623
htab_init_page_sizes(void)624 static void __init htab_init_page_sizes(void)
625 {
626 init_hpte_page_sizes();
627
628 if (!debug_pagealloc_enabled()) {
629 /*
630 * Pick a size for the linear mapping. Currently, we only
631 * support 16M, 1M and 4K which is the default
632 */
633 if (mmu_psize_defs[MMU_PAGE_16M].shift)
634 mmu_linear_psize = MMU_PAGE_16M;
635 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
636 mmu_linear_psize = MMU_PAGE_1M;
637 }
638
639 #ifdef CONFIG_PPC_64K_PAGES
640 /*
641 * Pick a size for the ordinary pages. Default is 4K, we support
642 * 64K for user mappings and vmalloc if supported by the processor.
643 * We only use 64k for ioremap if the processor
644 * (and firmware) support cache-inhibited large pages.
645 * If not, we use 4k and set mmu_ci_restrictions so that
646 * hash_page knows to switch processes that use cache-inhibited
647 * mappings to 4k pages.
648 */
649 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
650 mmu_virtual_psize = MMU_PAGE_64K;
651 mmu_vmalloc_psize = MMU_PAGE_64K;
652 if (mmu_linear_psize == MMU_PAGE_4K)
653 mmu_linear_psize = MMU_PAGE_64K;
654 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
655 /*
656 * When running on pSeries using 64k pages for ioremap
657 * would stop us accessing the HEA ethernet. So if we
658 * have the chance of ever seeing one, stay at 4k.
659 */
660 if (!might_have_hea())
661 mmu_io_psize = MMU_PAGE_64K;
662 } else
663 mmu_ci_restrictions = 1;
664 }
665 #endif /* CONFIG_PPC_64K_PAGES */
666
667 #ifdef CONFIG_SPARSEMEM_VMEMMAP
668 /* We try to use 16M pages for vmemmap if that is supported
669 * and we have at least 1G of RAM at boot
670 */
671 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
672 memblock_phys_mem_size() >= 0x40000000)
673 mmu_vmemmap_psize = MMU_PAGE_16M;
674 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
675 mmu_vmemmap_psize = MMU_PAGE_64K;
676 else
677 mmu_vmemmap_psize = MMU_PAGE_4K;
678 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
679
680 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
681 "virtual = %d, io = %d"
682 #ifdef CONFIG_SPARSEMEM_VMEMMAP
683 ", vmemmap = %d"
684 #endif
685 "\n",
686 mmu_psize_defs[mmu_linear_psize].shift,
687 mmu_psize_defs[mmu_virtual_psize].shift,
688 mmu_psize_defs[mmu_io_psize].shift
689 #ifdef CONFIG_SPARSEMEM_VMEMMAP
690 ,mmu_psize_defs[mmu_vmemmap_psize].shift
691 #endif
692 );
693 }
694
htab_dt_scan_pftsize(unsigned long node,const char * uname,int depth,void * data)695 static int __init htab_dt_scan_pftsize(unsigned long node,
696 const char *uname, int depth,
697 void *data)
698 {
699 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
700 const __be32 *prop;
701
702 /* We are scanning "cpu" nodes only */
703 if (type == NULL || strcmp(type, "cpu") != 0)
704 return 0;
705
706 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
707 if (prop != NULL) {
708 /* pft_size[0] is the NUMA CEC cookie */
709 ppc64_pft_size = be32_to_cpu(prop[1]);
710 return 1;
711 }
712 return 0;
713 }
714
htab_shift_for_mem_size(unsigned long mem_size)715 unsigned htab_shift_for_mem_size(unsigned long mem_size)
716 {
717 unsigned memshift = __ilog2(mem_size);
718 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
719 unsigned pteg_shift;
720
721 /* round mem_size up to next power of 2 */
722 if ((1UL << memshift) < mem_size)
723 memshift += 1;
724
725 /* aim for 2 pages / pteg */
726 pteg_shift = memshift - (pshift + 1);
727
728 /*
729 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
730 * size permitted by the architecture.
731 */
732 return max(pteg_shift + 7, 18U);
733 }
734
htab_get_table_size(void)735 static unsigned long __init htab_get_table_size(void)
736 {
737 /* If hash size isn't already provided by the platform, we try to
738 * retrieve it from the device-tree. If it's not there neither, we
739 * calculate it now based on the total RAM size
740 */
741 if (ppc64_pft_size == 0)
742 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
743 if (ppc64_pft_size)
744 return 1UL << ppc64_pft_size;
745
746 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
747 }
748
749 #ifdef CONFIG_MEMORY_HOTPLUG
hash__create_section_mapping(unsigned long start,unsigned long end)750 int hash__create_section_mapping(unsigned long start, unsigned long end)
751 {
752 int rc = htab_bolt_mapping(start, end, __pa(start),
753 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
754 mmu_kernel_ssize);
755
756 if (rc < 0) {
757 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
758 mmu_kernel_ssize);
759 BUG_ON(rc2 && (rc2 != -ENOENT));
760 }
761 return rc;
762 }
763
hash__remove_section_mapping(unsigned long start,unsigned long end)764 int hash__remove_section_mapping(unsigned long start, unsigned long end)
765 {
766 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
767 mmu_kernel_ssize);
768 WARN_ON(rc < 0);
769 return rc;
770 }
771 #endif /* CONFIG_MEMORY_HOTPLUG */
772
update_hid_for_hash(void)773 static void update_hid_for_hash(void)
774 {
775 unsigned long hid0;
776 unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
777
778 asm volatile("ptesync": : :"memory");
779 /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
780 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
781 : : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory");
782 asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
783 /*
784 * now switch the HID
785 */
786 hid0 = mfspr(SPRN_HID0);
787 hid0 &= ~HID0_POWER9_RADIX;
788 mtspr(SPRN_HID0, hid0);
789 asm volatile("isync": : :"memory");
790
791 /* Wait for it to happen */
792 while ((mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
793 cpu_relax();
794 }
795
hash_init_partition_table(phys_addr_t hash_table,unsigned long htab_size)796 static void __init hash_init_partition_table(phys_addr_t hash_table,
797 unsigned long htab_size)
798 {
799 unsigned long ps_field;
800 unsigned long patb_size = 1UL << PATB_SIZE_SHIFT;
801
802 /*
803 * slb llp encoding for the page size used in VPM real mode.
804 * We can ignore that for lpid 0
805 */
806 ps_field = 0;
807 htab_size = __ilog2(htab_size) - 18;
808
809 BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 24), "Partition table size too large.");
810 partition_tb = __va(memblock_alloc_base(patb_size, patb_size,
811 MEMBLOCK_ALLOC_ANYWHERE));
812
813 /* Initialize the Partition Table with no entries */
814 memset((void *)partition_tb, 0, patb_size);
815 partition_tb->patb0 = cpu_to_be64(ps_field | hash_table | htab_size);
816 /*
817 * FIXME!! This should be done via update_partition table
818 * For now UPRT is 0 for us.
819 */
820 partition_tb->patb1 = 0;
821 pr_info("Partition table %p\n", partition_tb);
822 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
823 update_hid_for_hash();
824 /*
825 * update partition table control register,
826 * 64 K size.
827 */
828 mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
829
830 }
831
htab_initialize(void)832 static void __init htab_initialize(void)
833 {
834 unsigned long table;
835 unsigned long pteg_count;
836 unsigned long prot;
837 unsigned long base = 0, size = 0;
838 struct memblock_region *reg;
839
840 DBG(" -> htab_initialize()\n");
841
842 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
843 mmu_kernel_ssize = MMU_SEGSIZE_1T;
844 mmu_highuser_ssize = MMU_SEGSIZE_1T;
845 printk(KERN_INFO "Using 1TB segments\n");
846 }
847
848 /*
849 * Calculate the required size of the htab. We want the number of
850 * PTEGs to equal one half the number of real pages.
851 */
852 htab_size_bytes = htab_get_table_size();
853 pteg_count = htab_size_bytes >> 7;
854
855 htab_hash_mask = pteg_count - 1;
856
857 if (firmware_has_feature(FW_FEATURE_LPAR) ||
858 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
859 /* Using a hypervisor which owns the htab */
860 htab_address = NULL;
861 _SDR1 = 0;
862 #ifdef CONFIG_FA_DUMP
863 /*
864 * If firmware assisted dump is active firmware preserves
865 * the contents of htab along with entire partition memory.
866 * Clear the htab if firmware assisted dump is active so
867 * that we dont end up using old mappings.
868 */
869 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
870 mmu_hash_ops.hpte_clear_all();
871 #endif
872 } else {
873 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
874
875 #ifdef CONFIG_PPC_CELL
876 /*
877 * Cell may require the hash table down low when using the
878 * Axon IOMMU in order to fit the dynamic region over it, see
879 * comments in cell/iommu.c
880 */
881 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
882 limit = 0x80000000;
883 pr_info("Hash table forced below 2G for Axon IOMMU\n");
884 }
885 #endif /* CONFIG_PPC_CELL */
886
887 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes,
888 limit);
889
890 DBG("Hash table allocated at %lx, size: %lx\n", table,
891 htab_size_bytes);
892
893 htab_address = __va(table);
894
895 /* htab absolute addr + encoded htabsize */
896 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
897
898 /* Initialize the HPT with no entries */
899 memset((void *)table, 0, htab_size_bytes);
900
901 if (!cpu_has_feature(CPU_FTR_ARCH_300))
902 /* Set SDR1 */
903 mtspr(SPRN_SDR1, _SDR1);
904 else
905 hash_init_partition_table(table, htab_size_bytes);
906 }
907
908 prot = pgprot_val(PAGE_KERNEL);
909
910 #ifdef CONFIG_DEBUG_PAGEALLOC
911 if (debug_pagealloc_enabled()) {
912 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
913 linear_map_hash_slots = __va(memblock_alloc_base(
914 linear_map_hash_count, 1, ppc64_rma_size));
915 memset(linear_map_hash_slots, 0, linear_map_hash_count);
916 }
917 #endif /* CONFIG_DEBUG_PAGEALLOC */
918
919 /* On U3 based machines, we need to reserve the DART area and
920 * _NOT_ map it to avoid cache paradoxes as it's remapped non
921 * cacheable later on
922 */
923
924 /* create bolted the linear mapping in the hash table */
925 for_each_memblock(memory, reg) {
926 base = (unsigned long)__va(reg->base);
927 size = reg->size;
928
929 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
930 base, size, prot);
931
932 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
933 prot, mmu_linear_psize, mmu_kernel_ssize));
934 }
935 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
936
937 /*
938 * If we have a memory_limit and we've allocated TCEs then we need to
939 * explicitly map the TCE area at the top of RAM. We also cope with the
940 * case that the TCEs start below memory_limit.
941 * tce_alloc_start/end are 16MB aligned so the mapping should work
942 * for either 4K or 16MB pages.
943 */
944 if (tce_alloc_start) {
945 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
946 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
947
948 if (base + size >= tce_alloc_start)
949 tce_alloc_start = base + size + 1;
950
951 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
952 __pa(tce_alloc_start), prot,
953 mmu_linear_psize, mmu_kernel_ssize));
954 }
955
956
957 DBG(" <- htab_initialize()\n");
958 }
959 #undef KB
960 #undef MB
961
hash__early_init_devtree(void)962 void __init hash__early_init_devtree(void)
963 {
964 /* Initialize segment sizes */
965 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
966
967 /* Initialize page sizes */
968 htab_scan_page_sizes();
969 }
970
hash__early_init_mmu(void)971 void __init hash__early_init_mmu(void)
972 {
973 htab_init_page_sizes();
974
975 /*
976 * initialize page table size
977 */
978 __pte_frag_nr = H_PTE_FRAG_NR;
979 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
980
981 __pte_index_size = H_PTE_INDEX_SIZE;
982 __pmd_index_size = H_PMD_INDEX_SIZE;
983 __pud_index_size = H_PUD_INDEX_SIZE;
984 __pgd_index_size = H_PGD_INDEX_SIZE;
985 __pmd_cache_index = H_PMD_CACHE_INDEX;
986 __pte_table_size = H_PTE_TABLE_SIZE;
987 __pmd_table_size = H_PMD_TABLE_SIZE;
988 __pud_table_size = H_PUD_TABLE_SIZE;
989 __pgd_table_size = H_PGD_TABLE_SIZE;
990 /*
991 * 4k use hugepd format, so for hash set then to
992 * zero
993 */
994 __pmd_val_bits = 0;
995 __pud_val_bits = 0;
996 __pgd_val_bits = 0;
997
998 __kernel_virt_start = H_KERN_VIRT_START;
999 __kernel_virt_size = H_KERN_VIRT_SIZE;
1000 __vmalloc_start = H_VMALLOC_START;
1001 __vmalloc_end = H_VMALLOC_END;
1002 vmemmap = (struct page *)H_VMEMMAP_BASE;
1003 ioremap_bot = IOREMAP_BASE;
1004
1005 #ifdef CONFIG_PCI
1006 pci_io_base = ISA_IO_BASE;
1007 #endif
1008
1009 /* Select appropriate backend */
1010 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1011 ps3_early_mm_init();
1012 else if (firmware_has_feature(FW_FEATURE_LPAR))
1013 hpte_init_pseries();
1014 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1015 hpte_init_native();
1016
1017 if (!mmu_hash_ops.hpte_insert)
1018 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1019
1020 /* Initialize the MMU Hash table and create the linear mapping
1021 * of memory. Has to be done before SLB initialization as this is
1022 * currently where the page size encoding is obtained.
1023 */
1024 htab_initialize();
1025
1026 pr_info("Initializing hash mmu with SLB\n");
1027 /* Initialize SLB management */
1028 slb_initialize();
1029 }
1030
1031 #ifdef CONFIG_SMP
hash__early_init_mmu_secondary(void)1032 void hash__early_init_mmu_secondary(void)
1033 {
1034 /* Initialize hash table for that CPU */
1035 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1036
1037 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
1038 update_hid_for_hash();
1039
1040 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1041 mtspr(SPRN_SDR1, _SDR1);
1042 else
1043 mtspr(SPRN_PTCR,
1044 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
1045 }
1046 /* Initialize SLB */
1047 slb_initialize();
1048 }
1049 #endif /* CONFIG_SMP */
1050
1051 /*
1052 * Called by asm hashtable.S for doing lazy icache flush
1053 */
hash_page_do_lazy_icache(unsigned int pp,pte_t pte,int trap)1054 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1055 {
1056 struct page *page;
1057
1058 if (!pfn_valid(pte_pfn(pte)))
1059 return pp;
1060
1061 page = pte_page(pte);
1062
1063 /* page is dirty */
1064 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1065 if (trap == 0x400) {
1066 flush_dcache_icache_page(page);
1067 set_bit(PG_arch_1, &page->flags);
1068 } else
1069 pp |= HPTE_R_N;
1070 }
1071 return pp;
1072 }
1073
1074 #ifdef CONFIG_PPC_MM_SLICES
get_paca_psize(unsigned long addr)1075 static unsigned int get_paca_psize(unsigned long addr)
1076 {
1077 u64 lpsizes;
1078 unsigned char *hpsizes;
1079 unsigned long index, mask_index;
1080
1081 if (addr < SLICE_LOW_TOP) {
1082 lpsizes = get_paca()->mm_ctx_low_slices_psize;
1083 index = GET_LOW_SLICE_INDEX(addr);
1084 return (lpsizes >> (index * 4)) & 0xF;
1085 }
1086 hpsizes = get_paca()->mm_ctx_high_slices_psize;
1087 index = GET_HIGH_SLICE_INDEX(addr);
1088 mask_index = index & 0x1;
1089 return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
1090 }
1091
1092 #else
get_paca_psize(unsigned long addr)1093 unsigned int get_paca_psize(unsigned long addr)
1094 {
1095 return get_paca()->mm_ctx_user_psize;
1096 }
1097 #endif
1098
1099 /*
1100 * Demote a segment to using 4k pages.
1101 * For now this makes the whole process use 4k pages.
1102 */
1103 #ifdef CONFIG_PPC_64K_PAGES
demote_segment_4k(struct mm_struct * mm,unsigned long addr)1104 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1105 {
1106 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1107 return;
1108 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1109 copro_flush_all_slbs(mm);
1110 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1111
1112 copy_mm_to_paca(&mm->context);
1113 slb_flush_and_rebolt();
1114 }
1115 }
1116 #endif /* CONFIG_PPC_64K_PAGES */
1117
1118 #ifdef CONFIG_PPC_SUBPAGE_PROT
1119 /*
1120 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1121 * Userspace sets the subpage permissions using the subpage_prot system call.
1122 *
1123 * Result is 0: full permissions, _PAGE_RW: read-only,
1124 * _PAGE_RWX: no access.
1125 */
subpage_protection(struct mm_struct * mm,unsigned long ea)1126 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1127 {
1128 struct subpage_prot_table *spt = &mm->context.spt;
1129 u32 spp = 0;
1130 u32 **sbpm, *sbpp;
1131
1132 if (ea >= spt->maxaddr)
1133 return 0;
1134 if (ea < 0x100000000UL) {
1135 /* addresses below 4GB use spt->low_prot */
1136 sbpm = spt->low_prot;
1137 } else {
1138 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1139 if (!sbpm)
1140 return 0;
1141 }
1142 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1143 if (!sbpp)
1144 return 0;
1145 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1146
1147 /* extract 2-bit bitfield for this 4k subpage */
1148 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1149
1150 /*
1151 * 0 -> full premission
1152 * 1 -> Read only
1153 * 2 -> no access.
1154 * We return the flag that need to be cleared.
1155 */
1156 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1157 return spp;
1158 }
1159
1160 #else /* CONFIG_PPC_SUBPAGE_PROT */
subpage_protection(struct mm_struct * mm,unsigned long ea)1161 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1162 {
1163 return 0;
1164 }
1165 #endif
1166
hash_failure_debug(unsigned long ea,unsigned long access,unsigned long vsid,unsigned long trap,int ssize,int psize,int lpsize,unsigned long pte)1167 void hash_failure_debug(unsigned long ea, unsigned long access,
1168 unsigned long vsid, unsigned long trap,
1169 int ssize, int psize, int lpsize, unsigned long pte)
1170 {
1171 if (!printk_ratelimit())
1172 return;
1173 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1174 ea, access, current->comm);
1175 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1176 trap, vsid, ssize, psize, lpsize, pte);
1177 }
1178
check_paca_psize(unsigned long ea,struct mm_struct * mm,int psize,bool user_region)1179 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1180 int psize, bool user_region)
1181 {
1182 if (user_region) {
1183 if (psize != get_paca_psize(ea)) {
1184 copy_mm_to_paca(&mm->context);
1185 slb_flush_and_rebolt();
1186 }
1187 } else if (get_paca()->vmalloc_sllp !=
1188 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1189 get_paca()->vmalloc_sllp =
1190 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1191 slb_vmalloc_update();
1192 }
1193 }
1194
1195 /* Result code is:
1196 * 0 - handled
1197 * 1 - normal page fault
1198 * -1 - critical hash insertion error
1199 * -2 - access not permitted by subpage protection mechanism
1200 */
hash_page_mm(struct mm_struct * mm,unsigned long ea,unsigned long access,unsigned long trap,unsigned long flags)1201 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1202 unsigned long access, unsigned long trap,
1203 unsigned long flags)
1204 {
1205 bool is_thp;
1206 enum ctx_state prev_state = exception_enter();
1207 pgd_t *pgdir;
1208 unsigned long vsid;
1209 pte_t *ptep;
1210 unsigned hugeshift;
1211 const struct cpumask *tmp;
1212 int rc, user_region = 0;
1213 int psize, ssize;
1214
1215 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1216 ea, access, trap);
1217 trace_hash_fault(ea, access, trap);
1218
1219 /* Get region & vsid */
1220 switch (REGION_ID(ea)) {
1221 case USER_REGION_ID:
1222 user_region = 1;
1223 if (! mm) {
1224 DBG_LOW(" user region with no mm !\n");
1225 rc = 1;
1226 goto bail;
1227 }
1228 psize = get_slice_psize(mm, ea);
1229 ssize = user_segment_size(ea);
1230 vsid = get_vsid(mm->context.id, ea, ssize);
1231 break;
1232 case VMALLOC_REGION_ID:
1233 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1234 if (ea < VMALLOC_END)
1235 psize = mmu_vmalloc_psize;
1236 else
1237 psize = mmu_io_psize;
1238 ssize = mmu_kernel_ssize;
1239 break;
1240 default:
1241 /* Not a valid range
1242 * Send the problem up to do_page_fault
1243 */
1244 rc = 1;
1245 goto bail;
1246 }
1247 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1248
1249 /* Bad address. */
1250 if (!vsid) {
1251 DBG_LOW("Bad address!\n");
1252 rc = 1;
1253 goto bail;
1254 }
1255 /* Get pgdir */
1256 pgdir = mm->pgd;
1257 if (pgdir == NULL) {
1258 rc = 1;
1259 goto bail;
1260 }
1261
1262 /* Check CPU locality */
1263 tmp = cpumask_of(smp_processor_id());
1264 if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
1265 flags |= HPTE_LOCAL_UPDATE;
1266
1267 #ifndef CONFIG_PPC_64K_PAGES
1268 /* If we use 4K pages and our psize is not 4K, then we might
1269 * be hitting a special driver mapping, and need to align the
1270 * address before we fetch the PTE.
1271 *
1272 * It could also be a hugepage mapping, in which case this is
1273 * not necessary, but it's not harmful, either.
1274 */
1275 if (psize != MMU_PAGE_4K)
1276 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1277 #endif /* CONFIG_PPC_64K_PAGES */
1278
1279 /* Get PTE and page size from page tables */
1280 ptep = __find_linux_pte_or_hugepte(pgdir, ea, &is_thp, &hugeshift);
1281 if (ptep == NULL || !pte_present(*ptep)) {
1282 DBG_LOW(" no PTE !\n");
1283 rc = 1;
1284 goto bail;
1285 }
1286
1287 /* Add _PAGE_PRESENT to the required access perm */
1288 access |= _PAGE_PRESENT;
1289
1290 /* Pre-check access permissions (will be re-checked atomically
1291 * in __hash_page_XX but this pre-check is a fast path
1292 */
1293 if (!check_pte_access(access, pte_val(*ptep))) {
1294 DBG_LOW(" no access !\n");
1295 rc = 1;
1296 goto bail;
1297 }
1298
1299 if (hugeshift) {
1300 if (is_thp)
1301 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1302 trap, flags, ssize, psize);
1303 #ifdef CONFIG_HUGETLB_PAGE
1304 else
1305 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1306 flags, ssize, hugeshift, psize);
1307 #else
1308 else {
1309 /*
1310 * if we have hugeshift, and is not transhuge with
1311 * hugetlb disabled, something is really wrong.
1312 */
1313 rc = 1;
1314 WARN_ON(1);
1315 }
1316 #endif
1317 if (current->mm == mm)
1318 check_paca_psize(ea, mm, psize, user_region);
1319
1320 goto bail;
1321 }
1322
1323 #ifndef CONFIG_PPC_64K_PAGES
1324 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1325 #else
1326 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1327 pte_val(*(ptep + PTRS_PER_PTE)));
1328 #endif
1329 /* Do actual hashing */
1330 #ifdef CONFIG_PPC_64K_PAGES
1331 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1332 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1333 demote_segment_4k(mm, ea);
1334 psize = MMU_PAGE_4K;
1335 }
1336
1337 /* If this PTE is non-cacheable and we have restrictions on
1338 * using non cacheable large pages, then we switch to 4k
1339 */
1340 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1341 if (user_region) {
1342 demote_segment_4k(mm, ea);
1343 psize = MMU_PAGE_4K;
1344 } else if (ea < VMALLOC_END) {
1345 /*
1346 * some driver did a non-cacheable mapping
1347 * in vmalloc space, so switch vmalloc
1348 * to 4k pages
1349 */
1350 printk(KERN_ALERT "Reducing vmalloc segment "
1351 "to 4kB pages because of "
1352 "non-cacheable mapping\n");
1353 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1354 copro_flush_all_slbs(mm);
1355 }
1356 }
1357
1358 #endif /* CONFIG_PPC_64K_PAGES */
1359
1360 if (current->mm == mm)
1361 check_paca_psize(ea, mm, psize, user_region);
1362
1363 #ifdef CONFIG_PPC_64K_PAGES
1364 if (psize == MMU_PAGE_64K)
1365 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1366 flags, ssize);
1367 else
1368 #endif /* CONFIG_PPC_64K_PAGES */
1369 {
1370 int spp = subpage_protection(mm, ea);
1371 if (access & spp)
1372 rc = -2;
1373 else
1374 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1375 flags, ssize, spp);
1376 }
1377
1378 /* Dump some info in case of hash insertion failure, they should
1379 * never happen so it is really useful to know if/when they do
1380 */
1381 if (rc == -1)
1382 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1383 psize, pte_val(*ptep));
1384 #ifndef CONFIG_PPC_64K_PAGES
1385 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1386 #else
1387 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1388 pte_val(*(ptep + PTRS_PER_PTE)));
1389 #endif
1390 DBG_LOW(" -> rc=%d\n", rc);
1391
1392 bail:
1393 exception_exit(prev_state);
1394 return rc;
1395 }
1396 EXPORT_SYMBOL_GPL(hash_page_mm);
1397
hash_page(unsigned long ea,unsigned long access,unsigned long trap,unsigned long dsisr)1398 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1399 unsigned long dsisr)
1400 {
1401 unsigned long flags = 0;
1402 struct mm_struct *mm = current->mm;
1403
1404 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1405 mm = &init_mm;
1406
1407 if (dsisr & DSISR_NOHPTE)
1408 flags |= HPTE_NOHPTE_UPDATE;
1409
1410 return hash_page_mm(mm, ea, access, trap, flags);
1411 }
1412 EXPORT_SYMBOL_GPL(hash_page);
1413
__hash_page(unsigned long ea,unsigned long msr,unsigned long trap,unsigned long dsisr)1414 int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1415 unsigned long dsisr)
1416 {
1417 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1418 unsigned long flags = 0;
1419 struct mm_struct *mm = current->mm;
1420
1421 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1422 mm = &init_mm;
1423
1424 if (dsisr & DSISR_NOHPTE)
1425 flags |= HPTE_NOHPTE_UPDATE;
1426
1427 if (dsisr & DSISR_ISSTORE)
1428 access |= _PAGE_WRITE;
1429 /*
1430 * We set _PAGE_PRIVILEGED only when
1431 * kernel mode access kernel space.
1432 *
1433 * _PAGE_PRIVILEGED is NOT set
1434 * 1) when kernel mode access user space
1435 * 2) user space access kernel space.
1436 */
1437 access |= _PAGE_PRIVILEGED;
1438 if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID))
1439 access &= ~_PAGE_PRIVILEGED;
1440
1441 if (trap == 0x400)
1442 access |= _PAGE_EXEC;
1443
1444 return hash_page_mm(mm, ea, access, trap, flags);
1445 }
1446
1447 #ifdef CONFIG_PPC_MM_SLICES
should_hash_preload(struct mm_struct * mm,unsigned long ea)1448 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1449 {
1450 int psize = get_slice_psize(mm, ea);
1451
1452 /* We only prefault standard pages for now */
1453 if (unlikely(psize != mm->context.user_psize))
1454 return false;
1455
1456 /*
1457 * Don't prefault if subpage protection is enabled for the EA.
1458 */
1459 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1460 return false;
1461
1462 return true;
1463 }
1464 #else
should_hash_preload(struct mm_struct * mm,unsigned long ea)1465 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1466 {
1467 return true;
1468 }
1469 #endif
1470
hash_preload(struct mm_struct * mm,unsigned long ea,unsigned long access,unsigned long trap)1471 void hash_preload(struct mm_struct *mm, unsigned long ea,
1472 unsigned long access, unsigned long trap)
1473 {
1474 int hugepage_shift;
1475 unsigned long vsid;
1476 pgd_t *pgdir;
1477 pte_t *ptep;
1478 unsigned long flags;
1479 int rc, ssize, update_flags = 0;
1480
1481 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1482
1483 if (!should_hash_preload(mm, ea))
1484 return;
1485
1486 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1487 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1488
1489 /* Get Linux PTE if available */
1490 pgdir = mm->pgd;
1491 if (pgdir == NULL)
1492 return;
1493
1494 /* Get VSID */
1495 ssize = user_segment_size(ea);
1496 vsid = get_vsid(mm->context.id, ea, ssize);
1497 if (!vsid)
1498 return;
1499 /*
1500 * Hash doesn't like irqs. Walking linux page table with irq disabled
1501 * saves us from holding multiple locks.
1502 */
1503 local_irq_save(flags);
1504
1505 /*
1506 * THP pages use update_mmu_cache_pmd. We don't do
1507 * hash preload there. Hence can ignore THP here
1508 */
1509 ptep = find_linux_pte_or_hugepte(pgdir, ea, NULL, &hugepage_shift);
1510 if (!ptep)
1511 goto out_exit;
1512
1513 WARN_ON(hugepage_shift);
1514 #ifdef CONFIG_PPC_64K_PAGES
1515 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1516 * a 64K kernel), then we don't preload, hash_page() will take
1517 * care of it once we actually try to access the page.
1518 * That way we don't have to duplicate all of the logic for segment
1519 * page size demotion here
1520 */
1521 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1522 goto out_exit;
1523 #endif /* CONFIG_PPC_64K_PAGES */
1524
1525 /* Is that local to this CPU ? */
1526 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1527 update_flags |= HPTE_LOCAL_UPDATE;
1528
1529 /* Hash it in */
1530 #ifdef CONFIG_PPC_64K_PAGES
1531 if (mm->context.user_psize == MMU_PAGE_64K)
1532 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1533 update_flags, ssize);
1534 else
1535 #endif /* CONFIG_PPC_64K_PAGES */
1536 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1537 ssize, subpage_protection(mm, ea));
1538
1539 /* Dump some info in case of hash insertion failure, they should
1540 * never happen so it is really useful to know if/when they do
1541 */
1542 if (rc == -1)
1543 hash_failure_debug(ea, access, vsid, trap, ssize,
1544 mm->context.user_psize,
1545 mm->context.user_psize,
1546 pte_val(*ptep));
1547 out_exit:
1548 local_irq_restore(flags);
1549 }
1550
1551 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
tm_flush_hash_page(int local)1552 static inline void tm_flush_hash_page(int local)
1553 {
1554 /*
1555 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1556 * page back to a block device w/PIO could pick up transactional data
1557 * (bad!) so we force an abort here. Before the sync the page will be
1558 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1559 * kernel uses a page from userspace without unmapping it first, it may
1560 * see the speculated version.
1561 */
1562 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1563 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1564 tm_enable();
1565 tm_abort(TM_CAUSE_TLBI);
1566 }
1567 }
1568 #else
tm_flush_hash_page(int local)1569 static inline void tm_flush_hash_page(int local)
1570 {
1571 }
1572 #endif
1573
1574 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1575 * do not forget to update the assembly call site !
1576 */
flush_hash_page(unsigned long vpn,real_pte_t pte,int psize,int ssize,unsigned long flags)1577 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1578 unsigned long flags)
1579 {
1580 unsigned long hash, index, shift, hidx, slot;
1581 int local = flags & HPTE_LOCAL_UPDATE;
1582
1583 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1584 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1585 hash = hpt_hash(vpn, shift, ssize);
1586 hidx = __rpte_to_hidx(pte, index);
1587 if (hidx & _PTEIDX_SECONDARY)
1588 hash = ~hash;
1589 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1590 slot += hidx & _PTEIDX_GROUP_IX;
1591 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1592 /*
1593 * We use same base page size and actual psize, because we don't
1594 * use these functions for hugepage
1595 */
1596 mmu_hash_ops.hpte_invalidate(slot, vpn, psize, psize,
1597 ssize, local);
1598 } pte_iterate_hashed_end();
1599
1600 tm_flush_hash_page(local);
1601 }
1602
1603 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
flush_hash_hugepage(unsigned long vsid,unsigned long addr,pmd_t * pmdp,unsigned int psize,int ssize,unsigned long flags)1604 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1605 pmd_t *pmdp, unsigned int psize, int ssize,
1606 unsigned long flags)
1607 {
1608 int i, max_hpte_count, valid;
1609 unsigned long s_addr;
1610 unsigned char *hpte_slot_array;
1611 unsigned long hidx, shift, vpn, hash, slot;
1612 int local = flags & HPTE_LOCAL_UPDATE;
1613
1614 s_addr = addr & HPAGE_PMD_MASK;
1615 hpte_slot_array = get_hpte_slot_array(pmdp);
1616 /*
1617 * IF we try to do a HUGE PTE update after a withdraw is done.
1618 * we will find the below NULL. This happens when we do
1619 * split_huge_page_pmd
1620 */
1621 if (!hpte_slot_array)
1622 return;
1623
1624 if (mmu_hash_ops.hugepage_invalidate) {
1625 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1626 psize, ssize, local);
1627 goto tm_abort;
1628 }
1629 /*
1630 * No bluk hpte removal support, invalidate each entry
1631 */
1632 shift = mmu_psize_defs[psize].shift;
1633 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1634 for (i = 0; i < max_hpte_count; i++) {
1635 /*
1636 * 8 bits per each hpte entries
1637 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1638 */
1639 valid = hpte_valid(hpte_slot_array, i);
1640 if (!valid)
1641 continue;
1642 hidx = hpte_hash_index(hpte_slot_array, i);
1643
1644 /* get the vpn */
1645 addr = s_addr + (i * (1ul << shift));
1646 vpn = hpt_vpn(addr, vsid, ssize);
1647 hash = hpt_hash(vpn, shift, ssize);
1648 if (hidx & _PTEIDX_SECONDARY)
1649 hash = ~hash;
1650
1651 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1652 slot += hidx & _PTEIDX_GROUP_IX;
1653 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1654 MMU_PAGE_16M, ssize, local);
1655 }
1656 tm_abort:
1657 tm_flush_hash_page(local);
1658 }
1659 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1660
flush_hash_range(unsigned long number,int local)1661 void flush_hash_range(unsigned long number, int local)
1662 {
1663 if (mmu_hash_ops.flush_hash_range)
1664 mmu_hash_ops.flush_hash_range(number, local);
1665 else {
1666 int i;
1667 struct ppc64_tlb_batch *batch =
1668 this_cpu_ptr(&ppc64_tlb_batch);
1669
1670 for (i = 0; i < number; i++)
1671 flush_hash_page(batch->vpn[i], batch->pte[i],
1672 batch->psize, batch->ssize, local);
1673 }
1674 }
1675
1676 /*
1677 * low_hash_fault is called when we the low level hash code failed
1678 * to instert a PTE due to an hypervisor error
1679 */
low_hash_fault(struct pt_regs * regs,unsigned long address,int rc)1680 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1681 {
1682 enum ctx_state prev_state = exception_enter();
1683
1684 if (user_mode(regs)) {
1685 #ifdef CONFIG_PPC_SUBPAGE_PROT
1686 if (rc == -2)
1687 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1688 else
1689 #endif
1690 _exception(SIGBUS, regs, BUS_ADRERR, address);
1691 } else
1692 bad_page_fault(regs, address, SIGBUS);
1693
1694 exception_exit(prev_state);
1695 }
1696
hpte_insert_repeating(unsigned long hash,unsigned long vpn,unsigned long pa,unsigned long rflags,unsigned long vflags,int psize,int ssize)1697 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1698 unsigned long pa, unsigned long rflags,
1699 unsigned long vflags, int psize, int ssize)
1700 {
1701 unsigned long hpte_group;
1702 long slot;
1703
1704 repeat:
1705 hpte_group = ((hash & htab_hash_mask) *
1706 HPTES_PER_GROUP) & ~0x7UL;
1707
1708 /* Insert into the hash table, primary slot */
1709 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1710 psize, psize, ssize);
1711
1712 /* Primary is full, try the secondary */
1713 if (unlikely(slot == -1)) {
1714 hpte_group = ((~hash & htab_hash_mask) *
1715 HPTES_PER_GROUP) & ~0x7UL;
1716 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1717 vflags | HPTE_V_SECONDARY,
1718 psize, psize, ssize);
1719 if (slot == -1) {
1720 if (mftb() & 0x1)
1721 hpte_group = ((hash & htab_hash_mask) *
1722 HPTES_PER_GROUP)&~0x7UL;
1723
1724 mmu_hash_ops.hpte_remove(hpte_group);
1725 goto repeat;
1726 }
1727 }
1728
1729 return slot;
1730 }
1731
1732 #ifdef CONFIG_DEBUG_PAGEALLOC
kernel_map_linear_page(unsigned long vaddr,unsigned long lmi)1733 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1734 {
1735 unsigned long hash;
1736 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1737 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1738 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1739 long ret;
1740
1741 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1742
1743 /* Don't create HPTE entries for bad address */
1744 if (!vsid)
1745 return;
1746
1747 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1748 HPTE_V_BOLTED,
1749 mmu_linear_psize, mmu_kernel_ssize);
1750
1751 BUG_ON (ret < 0);
1752 spin_lock(&linear_map_hash_lock);
1753 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1754 linear_map_hash_slots[lmi] = ret | 0x80;
1755 spin_unlock(&linear_map_hash_lock);
1756 }
1757
kernel_unmap_linear_page(unsigned long vaddr,unsigned long lmi)1758 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1759 {
1760 unsigned long hash, hidx, slot;
1761 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1762 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1763
1764 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1765 spin_lock(&linear_map_hash_lock);
1766 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1767 hidx = linear_map_hash_slots[lmi] & 0x7f;
1768 linear_map_hash_slots[lmi] = 0;
1769 spin_unlock(&linear_map_hash_lock);
1770 if (hidx & _PTEIDX_SECONDARY)
1771 hash = ~hash;
1772 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1773 slot += hidx & _PTEIDX_GROUP_IX;
1774 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1775 mmu_linear_psize,
1776 mmu_kernel_ssize, 0);
1777 }
1778
__kernel_map_pages(struct page * page,int numpages,int enable)1779 void __kernel_map_pages(struct page *page, int numpages, int enable)
1780 {
1781 unsigned long flags, vaddr, lmi;
1782 int i;
1783
1784 local_irq_save(flags);
1785 for (i = 0; i < numpages; i++, page++) {
1786 vaddr = (unsigned long)page_address(page);
1787 lmi = __pa(vaddr) >> PAGE_SHIFT;
1788 if (lmi >= linear_map_hash_count)
1789 continue;
1790 if (enable)
1791 kernel_map_linear_page(vaddr, lmi);
1792 else
1793 kernel_unmap_linear_page(vaddr, lmi);
1794 }
1795 local_irq_restore(flags);
1796 }
1797 #endif /* CONFIG_DEBUG_PAGEALLOC */
1798
hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,phys_addr_t first_memblock_size)1799 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1800 phys_addr_t first_memblock_size)
1801 {
1802 /* We don't currently support the first MEMBLOCK not mapping 0
1803 * physical on those processors
1804 */
1805 BUG_ON(first_memblock_base != 0);
1806
1807 /* On LPAR systems, the first entry is our RMA region,
1808 * non-LPAR 64-bit hash MMU systems don't have a limitation
1809 * on real mode access, but using the first entry works well
1810 * enough. We also clamp it to 1G to avoid some funky things
1811 * such as RTAS bugs etc...
1812 */
1813 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1814
1815 /* Finally limit subsequent allocations */
1816 memblock_set_current_limit(ppc64_rma_size);
1817 }
1818