1 #ifndef _ASM_X86_PGTABLE_DEFS_H
2 #define _ASM_X86_PGTABLE_DEFS_H
3
4 #include <linux/const.h>
5 #include <asm/page_types.h>
6
7 #define FIRST_USER_ADDRESS 0UL
8
9 #define _PAGE_BIT_PRESENT 0 /* is present */
10 #define _PAGE_BIT_RW 1 /* writeable */
11 #define _PAGE_BIT_USER 2 /* userspace addressable */
12 #define _PAGE_BIT_PWT 3 /* page write through */
13 #define _PAGE_BIT_PCD 4 /* page cache disabled */
14 #define _PAGE_BIT_ACCESSED 5 /* was accessed (raised by CPU) */
15 #define _PAGE_BIT_DIRTY 6 /* was written to (raised by CPU) */
16 #define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page */
17 #define _PAGE_BIT_PAT 7 /* on 4KB pages */
18 #define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
19 #define _PAGE_BIT_SOFTW1 9 /* available for programmer */
20 #define _PAGE_BIT_SOFTW2 10 /* " */
21 #define _PAGE_BIT_SOFTW3 11 /* " */
22 #define _PAGE_BIT_PAT_LARGE 12 /* On 2MB or 1GB pages */
23 #define _PAGE_BIT_SOFTW4 58 /* available for programmer */
24 #define _PAGE_BIT_PKEY_BIT0 59 /* Protection Keys, bit 1/4 */
25 #define _PAGE_BIT_PKEY_BIT1 60 /* Protection Keys, bit 2/4 */
26 #define _PAGE_BIT_PKEY_BIT2 61 /* Protection Keys, bit 3/4 */
27 #define _PAGE_BIT_PKEY_BIT3 62 /* Protection Keys, bit 4/4 */
28 #define _PAGE_BIT_NX 63 /* No execute: only valid after cpuid check */
29
30 #define _PAGE_BIT_SPECIAL _PAGE_BIT_SOFTW1
31 #define _PAGE_BIT_CPA_TEST _PAGE_BIT_SOFTW1
32 #define _PAGE_BIT_HIDDEN _PAGE_BIT_SOFTW3 /* hidden by kmemcheck */
33 #define _PAGE_BIT_SOFT_DIRTY _PAGE_BIT_SOFTW3 /* software dirty tracking */
34 #define _PAGE_BIT_DEVMAP _PAGE_BIT_SOFTW4
35
36 /* If _PAGE_BIT_PRESENT is clear, we use these: */
37 /* - if the user mapped it with PROT_NONE; pte_present gives true */
38 #define _PAGE_BIT_PROTNONE _PAGE_BIT_GLOBAL
39
40 #define _PAGE_PRESENT (_AT(pteval_t, 1) << _PAGE_BIT_PRESENT)
41 #define _PAGE_RW (_AT(pteval_t, 1) << _PAGE_BIT_RW)
42 #define _PAGE_USER (_AT(pteval_t, 1) << _PAGE_BIT_USER)
43 #define _PAGE_PWT (_AT(pteval_t, 1) << _PAGE_BIT_PWT)
44 #define _PAGE_PCD (_AT(pteval_t, 1) << _PAGE_BIT_PCD)
45 #define _PAGE_ACCESSED (_AT(pteval_t, 1) << _PAGE_BIT_ACCESSED)
46 #define _PAGE_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_DIRTY)
47 #define _PAGE_PSE (_AT(pteval_t, 1) << _PAGE_BIT_PSE)
48 #define _PAGE_GLOBAL (_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL)
49 #define _PAGE_SOFTW1 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW1)
50 #define _PAGE_SOFTW2 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW2)
51 #define _PAGE_PAT (_AT(pteval_t, 1) << _PAGE_BIT_PAT)
52 #define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE)
53 #define _PAGE_SPECIAL (_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL)
54 #define _PAGE_CPA_TEST (_AT(pteval_t, 1) << _PAGE_BIT_CPA_TEST)
55 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
56 #define _PAGE_PKEY_BIT0 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT0)
57 #define _PAGE_PKEY_BIT1 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT1)
58 #define _PAGE_PKEY_BIT2 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT2)
59 #define _PAGE_PKEY_BIT3 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT3)
60 #else
61 #define _PAGE_PKEY_BIT0 (_AT(pteval_t, 0))
62 #define _PAGE_PKEY_BIT1 (_AT(pteval_t, 0))
63 #define _PAGE_PKEY_BIT2 (_AT(pteval_t, 0))
64 #define _PAGE_PKEY_BIT3 (_AT(pteval_t, 0))
65 #endif
66 #define __HAVE_ARCH_PTE_SPECIAL
67
68 #define _PAGE_PKEY_MASK (_PAGE_PKEY_BIT0 | \
69 _PAGE_PKEY_BIT1 | \
70 _PAGE_PKEY_BIT2 | \
71 _PAGE_PKEY_BIT3)
72
73 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
74 #define _PAGE_KNL_ERRATUM_MASK (_PAGE_DIRTY | _PAGE_ACCESSED)
75 #else
76 #define _PAGE_KNL_ERRATUM_MASK 0
77 #endif
78
79 #ifdef CONFIG_KMEMCHECK
80 #define _PAGE_HIDDEN (_AT(pteval_t, 1) << _PAGE_BIT_HIDDEN)
81 #else
82 #define _PAGE_HIDDEN (_AT(pteval_t, 0))
83 #endif
84
85 /*
86 * The same hidden bit is used by kmemcheck, but since kmemcheck
87 * works on kernel pages while soft-dirty engine on user space,
88 * they do not conflict with each other.
89 */
90
91 #ifdef CONFIG_MEM_SOFT_DIRTY
92 #define _PAGE_SOFT_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_SOFT_DIRTY)
93 #else
94 #define _PAGE_SOFT_DIRTY (_AT(pteval_t, 0))
95 #endif
96
97 /*
98 * Tracking soft dirty bit when a page goes to a swap is tricky.
99 * We need a bit which can be stored in pte _and_ not conflict
100 * with swap entry format. On x86 bits 6 and 7 are *not* involved
101 * into swap entry computation, but bit 6 is used for nonlinear
102 * file mapping, so we borrow bit 7 for soft dirty tracking.
103 *
104 * Please note that this bit must be treated as swap dirty page
105 * mark if and only if the PTE has present bit clear!
106 */
107 #ifdef CONFIG_MEM_SOFT_DIRTY
108 #define _PAGE_SWP_SOFT_DIRTY _PAGE_PSE
109 #else
110 #define _PAGE_SWP_SOFT_DIRTY (_AT(pteval_t, 0))
111 #endif
112
113 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
114 #define _PAGE_NX (_AT(pteval_t, 1) << _PAGE_BIT_NX)
115 #define _PAGE_DEVMAP (_AT(u64, 1) << _PAGE_BIT_DEVMAP)
116 #define __HAVE_ARCH_PTE_DEVMAP
117 #else
118 #define _PAGE_NX (_AT(pteval_t, 0))
119 #define _PAGE_DEVMAP (_AT(pteval_t, 0))
120 #endif
121
122 #define _PAGE_PROTNONE (_AT(pteval_t, 1) << _PAGE_BIT_PROTNONE)
123
124 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
125 _PAGE_ACCESSED | _PAGE_DIRTY)
126 #define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | \
127 _PAGE_DIRTY)
128
129 /*
130 * Set of bits not changed in pte_modify. The pte's
131 * protection key is treated like _PAGE_RW, for
132 * instance, and is *not* included in this mask since
133 * pte_modify() does modify it.
134 */
135 #define _PAGE_CHG_MASK (PTE_PFN_MASK | _PAGE_PCD | _PAGE_PWT | \
136 _PAGE_SPECIAL | _PAGE_ACCESSED | _PAGE_DIRTY | \
137 _PAGE_SOFT_DIRTY)
138 #define _HPAGE_CHG_MASK (_PAGE_CHG_MASK | _PAGE_PSE)
139
140 /* The ASID is the lower 12 bits of CR3 */
141 #define X86_CR3_PCID_ASID_MASK (_AC((1<<12)-1,UL))
142
143 /* Mask for all the PCID-related bits in CR3: */
144 #define X86_CR3_PCID_MASK (X86_CR3_PCID_NOFLUSH | X86_CR3_PCID_ASID_MASK)
145 #define X86_CR3_PCID_ASID_KERN (_AC(0x0,UL))
146
147 #if defined(CONFIG_PAGE_TABLE_ISOLATION) && defined(CONFIG_X86_64)
148 /* Let X86_CR3_PCID_ASID_USER be usable for the X86_CR3_PCID_NOFLUSH bit */
149 #define X86_CR3_PCID_ASID_USER (_AC(0x80,UL))
150
151 #define X86_CR3_PCID_KERN_FLUSH (X86_CR3_PCID_ASID_KERN)
152 #define X86_CR3_PCID_USER_FLUSH (X86_CR3_PCID_ASID_USER)
153 #define X86_CR3_PCID_KERN_NOFLUSH (X86_CR3_PCID_NOFLUSH | X86_CR3_PCID_ASID_KERN)
154 #define X86_CR3_PCID_USER_NOFLUSH (X86_CR3_PCID_NOFLUSH | X86_CR3_PCID_ASID_USER)
155 #else
156 #define X86_CR3_PCID_ASID_USER (_AC(0x0,UL))
157 /*
158 * PCIDs are unsupported on 32-bit and none of these bits can be
159 * set in CR3:
160 */
161 #define X86_CR3_PCID_KERN_FLUSH (0)
162 #define X86_CR3_PCID_USER_FLUSH (0)
163 #define X86_CR3_PCID_KERN_NOFLUSH (0)
164 #define X86_CR3_PCID_USER_NOFLUSH (0)
165 #endif
166
167 /*
168 * The cache modes defined here are used to translate between pure SW usage
169 * and the HW defined cache mode bits and/or PAT entries.
170 *
171 * The resulting bits for PWT, PCD and PAT should be chosen in a way
172 * to have the WB mode at index 0 (all bits clear). This is the default
173 * right now and likely would break too much if changed.
174 */
175 #ifndef __ASSEMBLY__
176 enum page_cache_mode {
177 _PAGE_CACHE_MODE_WB = 0,
178 _PAGE_CACHE_MODE_WC = 1,
179 _PAGE_CACHE_MODE_UC_MINUS = 2,
180 _PAGE_CACHE_MODE_UC = 3,
181 _PAGE_CACHE_MODE_WT = 4,
182 _PAGE_CACHE_MODE_WP = 5,
183 _PAGE_CACHE_MODE_NUM = 8
184 };
185 #endif
186
187 #define _PAGE_CACHE_MASK (_PAGE_PAT | _PAGE_PCD | _PAGE_PWT)
188 #define _PAGE_NOCACHE (cachemode2protval(_PAGE_CACHE_MODE_UC))
189
190 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
191 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
192 _PAGE_ACCESSED | _PAGE_NX)
193
194 #define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | _PAGE_RW | \
195 _PAGE_USER | _PAGE_ACCESSED)
196 #define PAGE_COPY_NOEXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \
197 _PAGE_ACCESSED | _PAGE_NX)
198 #define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \
199 _PAGE_ACCESSED)
200 #define PAGE_COPY PAGE_COPY_NOEXEC
201 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | \
202 _PAGE_ACCESSED | _PAGE_NX)
203 #define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \
204 _PAGE_ACCESSED)
205
206 #define __PAGE_KERNEL_EXEC \
207 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_GLOBAL)
208 #define __PAGE_KERNEL (__PAGE_KERNEL_EXEC | _PAGE_NX)
209
210 #define __PAGE_KERNEL_RO (__PAGE_KERNEL & ~_PAGE_RW)
211 #define __PAGE_KERNEL_RX (__PAGE_KERNEL_EXEC & ~_PAGE_RW)
212 #define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL | _PAGE_NOCACHE)
213 #define __PAGE_KERNEL_VSYSCALL (__PAGE_KERNEL_RX | _PAGE_USER)
214 #define __PAGE_KERNEL_VVAR (__PAGE_KERNEL_RO | _PAGE_USER)
215 #define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE)
216 #define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE)
217
218 #define __PAGE_KERNEL_IO (__PAGE_KERNEL)
219 #define __PAGE_KERNEL_IO_NOCACHE (__PAGE_KERNEL_NOCACHE)
220
221 #define PAGE_KERNEL __pgprot(__PAGE_KERNEL)
222 #define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO)
223 #define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC)
224 #define PAGE_KERNEL_RX __pgprot(__PAGE_KERNEL_RX)
225 #define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE)
226 #define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE)
227 #define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC)
228 #define PAGE_KERNEL_VSYSCALL __pgprot(__PAGE_KERNEL_VSYSCALL)
229 #define PAGE_KERNEL_VVAR __pgprot(__PAGE_KERNEL_VVAR)
230
231 #define PAGE_KERNEL_IO __pgprot(__PAGE_KERNEL_IO)
232 #define PAGE_KERNEL_IO_NOCACHE __pgprot(__PAGE_KERNEL_IO_NOCACHE)
233
234 /* xwr */
235 #define __P000 PAGE_NONE
236 #define __P001 PAGE_READONLY
237 #define __P010 PAGE_COPY
238 #define __P011 PAGE_COPY
239 #define __P100 PAGE_READONLY_EXEC
240 #define __P101 PAGE_READONLY_EXEC
241 #define __P110 PAGE_COPY_EXEC
242 #define __P111 PAGE_COPY_EXEC
243
244 #define __S000 PAGE_NONE
245 #define __S001 PAGE_READONLY
246 #define __S010 PAGE_SHARED
247 #define __S011 PAGE_SHARED
248 #define __S100 PAGE_READONLY_EXEC
249 #define __S101 PAGE_READONLY_EXEC
250 #define __S110 PAGE_SHARED_EXEC
251 #define __S111 PAGE_SHARED_EXEC
252
253 /*
254 * early identity mapping pte attrib macros.
255 */
256 #ifdef CONFIG_X86_64
257 #define __PAGE_KERNEL_IDENT_LARGE_EXEC __PAGE_KERNEL_LARGE_EXEC
258 #else
259 #define PTE_IDENT_ATTR 0x003 /* PRESENT+RW */
260 #define PDE_IDENT_ATTR 0x063 /* PRESENT+RW+DIRTY+ACCESSED */
261 #define PGD_IDENT_ATTR 0x001 /* PRESENT (no other attributes) */
262 #endif
263
264 #ifdef CONFIG_X86_32
265 # include <asm/pgtable_32_types.h>
266 #else
267 # include <asm/pgtable_64_types.h>
268 #endif
269
270 #ifndef __ASSEMBLY__
271
272 #include <linux/types.h>
273
274 /* Extracts the PFN from a (pte|pmd|pud|pgd)val_t of a 4KB page */
275 #define PTE_PFN_MASK ((pteval_t)PHYSICAL_PAGE_MASK)
276
277 /*
278 * Extracts the flags from a (pte|pmd|pud|pgd)val_t
279 * This includes the protection key value.
280 */
281 #define PTE_FLAGS_MASK (~PTE_PFN_MASK)
282
283 typedef struct pgprot { pgprotval_t pgprot; } pgprot_t;
284
285 typedef struct { pgdval_t pgd; } pgd_t;
286
native_make_pgd(pgdval_t val)287 static inline pgd_t native_make_pgd(pgdval_t val)
288 {
289 return (pgd_t) { val };
290 }
291
native_pgd_val(pgd_t pgd)292 static inline pgdval_t native_pgd_val(pgd_t pgd)
293 {
294 return pgd.pgd;
295 }
296
pgd_flags(pgd_t pgd)297 static inline pgdval_t pgd_flags(pgd_t pgd)
298 {
299 return native_pgd_val(pgd) & PTE_FLAGS_MASK;
300 }
301
302 #if CONFIG_PGTABLE_LEVELS > 3
303 typedef struct { pudval_t pud; } pud_t;
304
native_make_pud(pmdval_t val)305 static inline pud_t native_make_pud(pmdval_t val)
306 {
307 return (pud_t) { val };
308 }
309
native_pud_val(pud_t pud)310 static inline pudval_t native_pud_val(pud_t pud)
311 {
312 return pud.pud;
313 }
314 #else
315 #include <asm-generic/pgtable-nopud.h>
316
native_pud_val(pud_t pud)317 static inline pudval_t native_pud_val(pud_t pud)
318 {
319 return native_pgd_val(pud.pgd);
320 }
321 #endif
322
323 #if CONFIG_PGTABLE_LEVELS > 2
324 typedef struct { pmdval_t pmd; } pmd_t;
325
native_make_pmd(pmdval_t val)326 static inline pmd_t native_make_pmd(pmdval_t val)
327 {
328 return (pmd_t) { val };
329 }
330
native_pmd_val(pmd_t pmd)331 static inline pmdval_t native_pmd_val(pmd_t pmd)
332 {
333 return pmd.pmd;
334 }
335 #else
336 #include <asm-generic/pgtable-nopmd.h>
337
native_pmd_val(pmd_t pmd)338 static inline pmdval_t native_pmd_val(pmd_t pmd)
339 {
340 return native_pgd_val(pmd.pud.pgd);
341 }
342 #endif
343
pud_pfn_mask(pud_t pud)344 static inline pudval_t pud_pfn_mask(pud_t pud)
345 {
346 if (native_pud_val(pud) & _PAGE_PSE)
347 return PHYSICAL_PUD_PAGE_MASK;
348 else
349 return PTE_PFN_MASK;
350 }
351
pud_flags_mask(pud_t pud)352 static inline pudval_t pud_flags_mask(pud_t pud)
353 {
354 return ~pud_pfn_mask(pud);
355 }
356
pud_flags(pud_t pud)357 static inline pudval_t pud_flags(pud_t pud)
358 {
359 return native_pud_val(pud) & pud_flags_mask(pud);
360 }
361
pmd_pfn_mask(pmd_t pmd)362 static inline pmdval_t pmd_pfn_mask(pmd_t pmd)
363 {
364 if (native_pmd_val(pmd) & _PAGE_PSE)
365 return PHYSICAL_PMD_PAGE_MASK;
366 else
367 return PTE_PFN_MASK;
368 }
369
pmd_flags_mask(pmd_t pmd)370 static inline pmdval_t pmd_flags_mask(pmd_t pmd)
371 {
372 return ~pmd_pfn_mask(pmd);
373 }
374
pmd_flags(pmd_t pmd)375 static inline pmdval_t pmd_flags(pmd_t pmd)
376 {
377 return native_pmd_val(pmd) & pmd_flags_mask(pmd);
378 }
379
native_make_pte(pteval_t val)380 static inline pte_t native_make_pte(pteval_t val)
381 {
382 return (pte_t) { .pte = val };
383 }
384
native_pte_val(pte_t pte)385 static inline pteval_t native_pte_val(pte_t pte)
386 {
387 return pte.pte;
388 }
389
pte_flags(pte_t pte)390 static inline pteval_t pte_flags(pte_t pte)
391 {
392 return native_pte_val(pte) & PTE_FLAGS_MASK;
393 }
394
395 #define pgprot_val(x) ((x).pgprot)
396 #define __pgprot(x) ((pgprot_t) { (x) } )
397
398 extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
399 extern uint8_t __pte2cachemode_tbl[8];
400
401 #define __pte2cm_idx(cb) \
402 ((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) | \
403 (((cb) >> (_PAGE_BIT_PCD - 1)) & 2) | \
404 (((cb) >> _PAGE_BIT_PWT) & 1))
405 #define __cm_idx2pte(i) \
406 ((((i) & 4) << (_PAGE_BIT_PAT - 2)) | \
407 (((i) & 2) << (_PAGE_BIT_PCD - 1)) | \
408 (((i) & 1) << _PAGE_BIT_PWT))
409
cachemode2protval(enum page_cache_mode pcm)410 static inline unsigned long cachemode2protval(enum page_cache_mode pcm)
411 {
412 if (likely(pcm == 0))
413 return 0;
414 return __cachemode2pte_tbl[pcm];
415 }
cachemode2pgprot(enum page_cache_mode pcm)416 static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
417 {
418 return __pgprot(cachemode2protval(pcm));
419 }
pgprot2cachemode(pgprot_t pgprot)420 static inline enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
421 {
422 unsigned long masked;
423
424 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
425 if (likely(masked == 0))
426 return 0;
427 return __pte2cachemode_tbl[__pte2cm_idx(masked)];
428 }
pgprot_4k_2_large(pgprot_t pgprot)429 static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
430 {
431 pgprotval_t val = pgprot_val(pgprot);
432 pgprot_t new;
433
434 pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
435 ((val & _PAGE_PAT) << (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
436 return new;
437 }
pgprot_large_2_4k(pgprot_t pgprot)438 static inline pgprot_t pgprot_large_2_4k(pgprot_t pgprot)
439 {
440 pgprotval_t val = pgprot_val(pgprot);
441 pgprot_t new;
442
443 pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
444 ((val & _PAGE_PAT_LARGE) >>
445 (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
446 return new;
447 }
448
449
450 typedef struct page *pgtable_t;
451
452 extern pteval_t __supported_pte_mask;
453 extern void set_nx(void);
454 extern int nx_enabled;
455
456 #define pgprot_writecombine pgprot_writecombine
457 extern pgprot_t pgprot_writecombine(pgprot_t prot);
458
459 #define pgprot_writethrough pgprot_writethrough
460 extern pgprot_t pgprot_writethrough(pgprot_t prot);
461
462 /* Indicate that x86 has its own track and untrack pfn vma functions */
463 #define __HAVE_PFNMAP_TRACKING
464
465 #define __HAVE_PHYS_MEM_ACCESS_PROT
466 struct file;
467 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
468 unsigned long size, pgprot_t vma_prot);
469
470 /* Install a pte for a particular vaddr in kernel space. */
471 void set_pte_vaddr(unsigned long vaddr, pte_t pte);
472
473 #ifdef CONFIG_X86_32
474 extern void native_pagetable_init(void);
475 #else
476 #define native_pagetable_init paging_init
477 #endif
478
479 struct seq_file;
480 extern void arch_report_meminfo(struct seq_file *m);
481
482 enum pg_level {
483 PG_LEVEL_NONE,
484 PG_LEVEL_4K,
485 PG_LEVEL_2M,
486 PG_LEVEL_1G,
487 PG_LEVEL_NUM
488 };
489
490 #ifdef CONFIG_PROC_FS
491 extern void update_page_count(int level, unsigned long pages);
492 #else
update_page_count(int level,unsigned long pages)493 static inline void update_page_count(int level, unsigned long pages) { }
494 #endif
495
496 /*
497 * Helper function that returns the kernel pagetable entry controlling
498 * the virtual address 'address'. NULL means no pagetable entry present.
499 * NOTE: the return type is pte_t but if the pmd is PSE then we return it
500 * as a pte too.
501 */
502 extern pte_t *lookup_address(unsigned long address, unsigned int *level);
503 extern pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address,
504 unsigned int *level);
505 extern pmd_t *lookup_pmd_address(unsigned long address);
506 extern phys_addr_t slow_virt_to_phys(void *__address);
507 extern int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address,
508 unsigned numpages, unsigned long page_flags);
509 #endif /* !__ASSEMBLY__ */
510
511 #endif /* _ASM_X86_PGTABLE_DEFS_H */
512