1 /*
2 * Support for NI general purpose counters
3 *
4 * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 /*
18 * Module: ni_tio
19 * Description: National Instruments general purpose counters
20 * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
21 * Herman.Bruyninckx@mech.kuleuven.ac.be,
22 * Wim.Meeussen@mech.kuleuven.ac.be,
23 * Klaas.Gadeyne@mech.kuleuven.ac.be,
24 * Frank Mori Hess <fmhess@users.sourceforge.net>
25 * Updated: Thu Nov 16 09:50:32 EST 2006
26 * Status: works
27 *
28 * This module is not used directly by end-users. Rather, it
29 * is used by other drivers (for example ni_660x and ni_pcimio)
30 * to provide support for NI's general purpose counters. It was
31 * originally based on the counter code from ni_660x.c and
32 * ni_mio_common.c.
33 *
34 * References:
35 * DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
36 * DAQ 6601/6602 User Manual (NI 322137B-01)
37 * 340934b.pdf DAQ-STC reference manual
38 *
39 * TODO: Support use of both banks X and Y
40 */
41
42 #include <linux/module.h>
43 #include <linux/slab.h>
44
45 #include "ni_tio_internal.h"
46
47 /*
48 * clock sources for ni e and m series boards,
49 * get bits with GI_SRC_SEL()
50 */
51 #define NI_M_TIMEBASE_1_CLK 0x0 /* 20MHz */
52 #define NI_M_PFI_CLK(x) (((x) < 10) ? (1 + (x)) : (0xb + (x)))
53 #define NI_M_RTSI_CLK(x) (((x) == 7) ? 0x1b : (0xb + (x)))
54 #define NI_M_TIMEBASE_2_CLK 0x12 /* 100KHz */
55 #define NI_M_NEXT_TC_CLK 0x13
56 #define NI_M_NEXT_GATE_CLK 0x14 /* Gi_Src_SubSelect=0 */
57 #define NI_M_PXI_STAR_TRIGGER_CLK 0x14 /* Gi_Src_SubSelect=1 */
58 #define NI_M_PXI10_CLK 0x1d
59 #define NI_M_TIMEBASE_3_CLK 0x1e /* 80MHz, Gi_Src_SubSelect=0 */
60 #define NI_M_ANALOG_TRIGGER_OUT_CLK 0x1e /* Gi_Src_SubSelect=1 */
61 #define NI_M_LOGIC_LOW_CLK 0x1f
62 #define NI_M_MAX_PFI_CHAN 15
63 #define NI_M_MAX_RTSI_CHAN 7
64
65 /*
66 * clock sources for ni_660x boards,
67 * get bits with GI_SRC_SEL()
68 */
69 #define NI_660X_TIMEBASE_1_CLK 0x0 /* 20MHz */
70 #define NI_660X_SRC_PIN_I_CLK 0x1
71 #define NI_660X_SRC_PIN_CLK(x) (0x2 + (x))
72 #define NI_660X_NEXT_GATE_CLK 0xa
73 #define NI_660X_RTSI_CLK(x) (0xb + (x))
74 #define NI_660X_TIMEBASE_2_CLK 0x12 /* 100KHz */
75 #define NI_660X_NEXT_TC_CLK 0x13
76 #define NI_660X_TIMEBASE_3_CLK 0x1e /* 80MHz */
77 #define NI_660X_LOGIC_LOW_CLK 0x1f
78 #define NI_660X_MAX_SRC_PIN 7
79 #define NI_660X_MAX_RTSI_CHAN 6
80
81 /* ni m series gate_select */
82 #define NI_M_TIMESTAMP_MUX_GATE_SEL 0x0
83 #define NI_M_PFI_GATE_SEL(x) (((x) < 10) ? (1 + (x)) : (0xb + (x)))
84 #define NI_M_RTSI_GATE_SEL(x) (((x) == 7) ? 0x1b : (0xb + (x)))
85 #define NI_M_AI_START2_GATE_SEL 0x12
86 #define NI_M_PXI_STAR_TRIGGER_GATE_SEL 0x13
87 #define NI_M_NEXT_OUT_GATE_SEL 0x14
88 #define NI_M_AI_START1_GATE_SEL 0x1c
89 #define NI_M_NEXT_SRC_GATE_SEL 0x1d
90 #define NI_M_ANALOG_TRIG_OUT_GATE_SEL 0x1e
91 #define NI_M_LOGIC_LOW_GATE_SEL 0x1f
92
93 /* ni_660x gate select */
94 #define NI_660X_SRC_PIN_I_GATE_SEL 0x0
95 #define NI_660X_GATE_PIN_I_GATE_SEL 0x1
96 #define NI_660X_PIN_GATE_SEL(x) (0x2 + (x))
97 #define NI_660X_NEXT_SRC_GATE_SEL 0xa
98 #define NI_660X_RTSI_GATE_SEL(x) (0xb + (x))
99 #define NI_660X_NEXT_OUT_GATE_SEL 0x14
100 #define NI_660X_LOGIC_LOW_GATE_SEL 0x1f
101 #define NI_660X_MAX_GATE_PIN 7
102
103 /* ni_660x second gate select */
104 #define NI_660X_SRC_PIN_I_GATE2_SEL 0x0
105 #define NI_660X_UD_PIN_I_GATE2_SEL 0x1
106 #define NI_660X_UD_PIN_GATE2_SEL(x) (0x2 + (x))
107 #define NI_660X_NEXT_SRC_GATE2_SEL 0xa
108 #define NI_660X_RTSI_GATE2_SEL(x) (0xb + (x))
109 #define NI_660X_NEXT_OUT_GATE2_SEL 0x14
110 #define NI_660X_SELECTED_GATE2_SEL 0x1e
111 #define NI_660X_LOGIC_LOW_GATE2_SEL 0x1f
112 #define NI_660X_MAX_UP_DOWN_PIN 7
113
GI_PRESCALE_X2(enum ni_gpct_variant variant)114 static inline unsigned int GI_PRESCALE_X2(enum ni_gpct_variant variant)
115 {
116 switch (variant) {
117 case ni_gpct_variant_e_series:
118 default:
119 return 0;
120 case ni_gpct_variant_m_series:
121 return GI_M_PRESCALE_X2;
122 case ni_gpct_variant_660x:
123 return GI_660X_PRESCALE_X2;
124 }
125 }
126
GI_PRESCALE_X8(enum ni_gpct_variant variant)127 static inline unsigned int GI_PRESCALE_X8(enum ni_gpct_variant variant)
128 {
129 switch (variant) {
130 case ni_gpct_variant_e_series:
131 default:
132 return 0;
133 case ni_gpct_variant_m_series:
134 return GI_M_PRESCALE_X8;
135 case ni_gpct_variant_660x:
136 return GI_660X_PRESCALE_X8;
137 }
138 }
139
ni_tio_has_gate2_registers(const struct ni_gpct_device * counter_dev)140 static bool ni_tio_has_gate2_registers(const struct ni_gpct_device *counter_dev)
141 {
142 switch (counter_dev->variant) {
143 case ni_gpct_variant_e_series:
144 default:
145 return false;
146 case ni_gpct_variant_m_series:
147 case ni_gpct_variant_660x:
148 return true;
149 }
150 }
151
152 /**
153 * ni_tio_write() - Write a TIO register using the driver provided callback.
154 * @counter: struct ni_gpct counter.
155 * @value: the value to write
156 * @reg: the register to write.
157 */
ni_tio_write(struct ni_gpct * counter,unsigned int value,enum ni_gpct_register reg)158 void ni_tio_write(struct ni_gpct *counter, unsigned int value,
159 enum ni_gpct_register reg)
160 {
161 if (reg < NITIO_NUM_REGS)
162 counter->counter_dev->write(counter, value, reg);
163 }
164 EXPORT_SYMBOL_GPL(ni_tio_write);
165
166 /**
167 * ni_tio_read() - Read a TIO register using the driver provided callback.
168 * @counter: struct ni_gpct counter.
169 * @reg: the register to read.
170 */
ni_tio_read(struct ni_gpct * counter,enum ni_gpct_register reg)171 unsigned int ni_tio_read(struct ni_gpct *counter, enum ni_gpct_register reg)
172 {
173 if (reg < NITIO_NUM_REGS)
174 return counter->counter_dev->read(counter, reg);
175 return 0;
176 }
177 EXPORT_SYMBOL_GPL(ni_tio_read);
178
ni_tio_reset_count_and_disarm(struct ni_gpct * counter)179 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
180 {
181 unsigned int cidx = counter->counter_index;
182
183 ni_tio_write(counter, GI_RESET(cidx), NITIO_RESET_REG(cidx));
184 }
185
ni_tio_clock_period_ps(const struct ni_gpct * counter,unsigned int generic_clock_source,u64 * period_ps)186 static int ni_tio_clock_period_ps(const struct ni_gpct *counter,
187 unsigned int generic_clock_source,
188 u64 *period_ps)
189 {
190 u64 clock_period_ps;
191
192 switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
193 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
194 clock_period_ps = 50000;
195 break;
196 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
197 clock_period_ps = 10000000;
198 break;
199 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
200 clock_period_ps = 12500;
201 break;
202 case NI_GPCT_PXI10_CLOCK_SRC_BITS:
203 clock_period_ps = 100000;
204 break;
205 default:
206 /*
207 * clock period is specified by user with prescaling
208 * already taken into account.
209 */
210 *period_ps = counter->clock_period_ps;
211 return 0;
212 }
213
214 switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
215 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
216 break;
217 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
218 clock_period_ps *= 2;
219 break;
220 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
221 clock_period_ps *= 8;
222 break;
223 default:
224 return -EINVAL;
225 }
226 *period_ps = clock_period_ps;
227 return 0;
228 }
229
ni_tio_set_bits_transient(struct ni_gpct * counter,enum ni_gpct_register reg,unsigned int mask,unsigned int value,unsigned int transient)230 static void ni_tio_set_bits_transient(struct ni_gpct *counter,
231 enum ni_gpct_register reg,
232 unsigned int mask, unsigned int value,
233 unsigned int transient)
234 {
235 struct ni_gpct_device *counter_dev = counter->counter_dev;
236 unsigned long flags;
237
238 if (reg < NITIO_NUM_REGS) {
239 spin_lock_irqsave(&counter_dev->regs_lock, flags);
240 counter_dev->regs[reg] &= ~mask;
241 counter_dev->regs[reg] |= (value & mask);
242 ni_tio_write(counter, counter_dev->regs[reg] | transient, reg);
243 mmiowb();
244 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
245 }
246 }
247
248 /**
249 * ni_tio_set_bits() - Safely write a counter register.
250 * @counter: struct ni_gpct counter.
251 * @reg: the register to write.
252 * @mask: the bits to change.
253 * @value: the new bits value.
254 *
255 * Used to write to, and update the software copy, a register whose bits may
256 * be twiddled in interrupt context, or whose software copy may be read in
257 * interrupt context.
258 */
ni_tio_set_bits(struct ni_gpct * counter,enum ni_gpct_register reg,unsigned int mask,unsigned int value)259 void ni_tio_set_bits(struct ni_gpct *counter, enum ni_gpct_register reg,
260 unsigned int mask, unsigned int value)
261 {
262 ni_tio_set_bits_transient(counter, reg, mask, value, 0x0);
263 }
264 EXPORT_SYMBOL_GPL(ni_tio_set_bits);
265
266 /**
267 * ni_tio_get_soft_copy() - Safely read the software copy of a counter register.
268 * @counter: struct ni_gpct counter.
269 * @reg: the register to read.
270 *
271 * Used to get the software copy of a register whose bits might be modified
272 * in interrupt context, or whose software copy might need to be read in
273 * interrupt context.
274 */
ni_tio_get_soft_copy(const struct ni_gpct * counter,enum ni_gpct_register reg)275 unsigned int ni_tio_get_soft_copy(const struct ni_gpct *counter,
276 enum ni_gpct_register reg)
277 {
278 struct ni_gpct_device *counter_dev = counter->counter_dev;
279 unsigned int value = 0;
280 unsigned long flags;
281
282 if (reg < NITIO_NUM_REGS) {
283 spin_lock_irqsave(&counter_dev->regs_lock, flags);
284 value = counter_dev->regs[reg];
285 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
286 }
287 return value;
288 }
289 EXPORT_SYMBOL_GPL(ni_tio_get_soft_copy);
290
ni_tio_clock_src_modifiers(const struct ni_gpct * counter)291 static unsigned int ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
292 {
293 struct ni_gpct_device *counter_dev = counter->counter_dev;
294 unsigned int cidx = counter->counter_index;
295 unsigned int counting_mode_bits =
296 ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx));
297 unsigned int bits = 0;
298
299 if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
300 GI_SRC_POL_INVERT)
301 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
302 if (counting_mode_bits & GI_PRESCALE_X2(counter_dev->variant))
303 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
304 if (counting_mode_bits & GI_PRESCALE_X8(counter_dev->variant))
305 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
306 return bits;
307 }
308
ni_m_series_clock_src_select(const struct ni_gpct * counter,unsigned int * clk_src)309 static int ni_m_series_clock_src_select(const struct ni_gpct *counter,
310 unsigned int *clk_src)
311 {
312 struct ni_gpct_device *counter_dev = counter->counter_dev;
313 unsigned int cidx = counter->counter_index;
314 unsigned int second_gate_reg = NITIO_GATE2_REG(cidx);
315 unsigned int clock_source = 0;
316 unsigned int src;
317 unsigned int i;
318
319 src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
320 NITIO_INPUT_SEL_REG(cidx)));
321
322 switch (src) {
323 case NI_M_TIMEBASE_1_CLK:
324 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
325 break;
326 case NI_M_TIMEBASE_2_CLK:
327 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
328 break;
329 case NI_M_TIMEBASE_3_CLK:
330 if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL)
331 clock_source =
332 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
333 else
334 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
335 break;
336 case NI_M_LOGIC_LOW_CLK:
337 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
338 break;
339 case NI_M_NEXT_GATE_CLK:
340 if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL)
341 clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
342 else
343 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
344 break;
345 case NI_M_PXI10_CLK:
346 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
347 break;
348 case NI_M_NEXT_TC_CLK:
349 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
350 break;
351 default:
352 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
353 if (src == NI_M_RTSI_CLK(i)) {
354 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
355 break;
356 }
357 }
358 if (i <= NI_M_MAX_RTSI_CHAN)
359 break;
360 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
361 if (src == NI_M_PFI_CLK(i)) {
362 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
363 break;
364 }
365 }
366 if (i <= NI_M_MAX_PFI_CHAN)
367 break;
368 return -EINVAL;
369 }
370 clock_source |= ni_tio_clock_src_modifiers(counter);
371 *clk_src = clock_source;
372 return 0;
373 }
374
ni_660x_clock_src_select(const struct ni_gpct * counter,unsigned int * clk_src)375 static int ni_660x_clock_src_select(const struct ni_gpct *counter,
376 unsigned int *clk_src)
377 {
378 unsigned int clock_source = 0;
379 unsigned int cidx = counter->counter_index;
380 unsigned int src;
381 unsigned int i;
382
383 src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
384 NITIO_INPUT_SEL_REG(cidx)));
385
386 switch (src) {
387 case NI_660X_TIMEBASE_1_CLK:
388 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
389 break;
390 case NI_660X_TIMEBASE_2_CLK:
391 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
392 break;
393 case NI_660X_TIMEBASE_3_CLK:
394 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
395 break;
396 case NI_660X_LOGIC_LOW_CLK:
397 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
398 break;
399 case NI_660X_SRC_PIN_I_CLK:
400 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
401 break;
402 case NI_660X_NEXT_GATE_CLK:
403 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
404 break;
405 case NI_660X_NEXT_TC_CLK:
406 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
407 break;
408 default:
409 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
410 if (src == NI_660X_RTSI_CLK(i)) {
411 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
412 break;
413 }
414 }
415 if (i <= NI_660X_MAX_RTSI_CHAN)
416 break;
417 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
418 if (src == NI_660X_SRC_PIN_CLK(i)) {
419 clock_source =
420 NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
421 break;
422 }
423 }
424 if (i <= NI_660X_MAX_SRC_PIN)
425 break;
426 return -EINVAL;
427 }
428 clock_source |= ni_tio_clock_src_modifiers(counter);
429 *clk_src = clock_source;
430 return 0;
431 }
432
ni_tio_generic_clock_src_select(const struct ni_gpct * counter,unsigned int * clk_src)433 static int ni_tio_generic_clock_src_select(const struct ni_gpct *counter,
434 unsigned int *clk_src)
435 {
436 switch (counter->counter_dev->variant) {
437 case ni_gpct_variant_e_series:
438 case ni_gpct_variant_m_series:
439 default:
440 return ni_m_series_clock_src_select(counter, clk_src);
441 case ni_gpct_variant_660x:
442 return ni_660x_clock_src_select(counter, clk_src);
443 }
444 }
445
ni_tio_set_sync_mode(struct ni_gpct * counter)446 static void ni_tio_set_sync_mode(struct ni_gpct *counter)
447 {
448 struct ni_gpct_device *counter_dev = counter->counter_dev;
449 unsigned int cidx = counter->counter_index;
450 static const u64 min_normal_sync_period_ps = 25000;
451 unsigned int mask = 0;
452 unsigned int bits = 0;
453 unsigned int reg;
454 unsigned int mode;
455 unsigned int clk_src;
456 u64 ps;
457 bool force_alt_sync;
458
459 /* only m series and 660x variants have counting mode registers */
460 switch (counter_dev->variant) {
461 case ni_gpct_variant_e_series:
462 default:
463 return;
464 case ni_gpct_variant_m_series:
465 mask = GI_M_ALT_SYNC;
466 break;
467 case ni_gpct_variant_660x:
468 mask = GI_660X_ALT_SYNC;
469 break;
470 }
471
472 reg = NITIO_CNT_MODE_REG(cidx);
473 mode = ni_tio_get_soft_copy(counter, reg);
474 switch (mode & GI_CNT_MODE_MASK) {
475 case GI_CNT_MODE_QUADX1:
476 case GI_CNT_MODE_QUADX2:
477 case GI_CNT_MODE_QUADX4:
478 case GI_CNT_MODE_SYNC_SRC:
479 force_alt_sync = true;
480 break;
481 default:
482 force_alt_sync = false;
483 break;
484 }
485
486 ni_tio_generic_clock_src_select(counter, &clk_src);
487 ni_tio_clock_period_ps(counter, clk_src, &ps);
488
489 /*
490 * It's not clear what we should do if clock_period is unknown, so we
491 * are not using the alt sync bit in that case.
492 */
493 if (force_alt_sync || (ps && ps < min_normal_sync_period_ps))
494 bits = mask;
495
496 ni_tio_set_bits(counter, reg, mask, bits);
497 }
498
ni_tio_set_counter_mode(struct ni_gpct * counter,unsigned int mode)499 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned int mode)
500 {
501 struct ni_gpct_device *counter_dev = counter->counter_dev;
502 unsigned int cidx = counter->counter_index;
503 unsigned int mode_reg_mask;
504 unsigned int mode_reg_values;
505 unsigned int input_select_bits = 0;
506 /* these bits map directly on to the mode register */
507 static const unsigned int mode_reg_direct_mask =
508 NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
509 NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
510 NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
511 NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
512
513 mode_reg_mask = mode_reg_direct_mask | GI_RELOAD_SRC_SWITCHING;
514 mode_reg_values = mode & mode_reg_direct_mask;
515 switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
516 case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
517 break;
518 case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
519 mode_reg_values |= GI_RELOAD_SRC_SWITCHING;
520 break;
521 case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
522 input_select_bits |= GI_GATE_SEL_LOAD_SRC;
523 mode_reg_mask |= GI_GATING_MODE_MASK;
524 mode_reg_values |= GI_LEVEL_GATING;
525 break;
526 default:
527 break;
528 }
529 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
530 mode_reg_mask, mode_reg_values);
531
532 if (ni_tio_counting_mode_registers_present(counter_dev)) {
533 unsigned int bits = 0;
534
535 bits |= GI_CNT_MODE(mode >> NI_GPCT_COUNTING_MODE_SHIFT);
536 bits |= GI_INDEX_PHASE((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT));
537 if (mode & NI_GPCT_INDEX_ENABLE_BIT)
538 bits |= GI_INDEX_MODE;
539 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
540 GI_CNT_MODE_MASK | GI_INDEX_PHASE_MASK |
541 GI_INDEX_MODE, bits);
542 ni_tio_set_sync_mode(counter);
543 }
544
545 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_CNT_DIR_MASK,
546 GI_CNT_DIR(mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT));
547
548 if (mode & NI_GPCT_OR_GATE_BIT)
549 input_select_bits |= GI_OR_GATE;
550 if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
551 input_select_bits |= GI_OUTPUT_POL_INVERT;
552 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
553 GI_GATE_SEL_LOAD_SRC | GI_OR_GATE |
554 GI_OUTPUT_POL_INVERT, input_select_bits);
555
556 return 0;
557 }
558
ni_tio_arm(struct ni_gpct * counter,bool arm,unsigned int start_trigger)559 int ni_tio_arm(struct ni_gpct *counter, bool arm, unsigned int start_trigger)
560 {
561 struct ni_gpct_device *counter_dev = counter->counter_dev;
562 unsigned int cidx = counter->counter_index;
563 unsigned int transient_bits = 0;
564
565 if (arm) {
566 unsigned int mask = 0;
567 unsigned int bits = 0;
568
569 /* only m series and 660x have counting mode registers */
570 switch (counter_dev->variant) {
571 case ni_gpct_variant_e_series:
572 default:
573 break;
574 case ni_gpct_variant_m_series:
575 mask = GI_M_HW_ARM_SEL_MASK;
576 break;
577 case ni_gpct_variant_660x:
578 mask = GI_660X_HW_ARM_SEL_MASK;
579 break;
580 }
581
582 switch (start_trigger) {
583 case NI_GPCT_ARM_IMMEDIATE:
584 transient_bits |= GI_ARM;
585 break;
586 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
587 transient_bits |= GI_ARM | GI_ARM_COPY;
588 break;
589 default:
590 /*
591 * for m series and 660x, pass-through the least
592 * significant bits so we can figure out what select
593 * later
594 */
595 if (mask && (start_trigger & NI_GPCT_ARM_UNKNOWN)) {
596 bits |= GI_HW_ARM_ENA |
597 (GI_HW_ARM_SEL(start_trigger) & mask);
598 } else {
599 return -EINVAL;
600 }
601 break;
602 }
603
604 if (mask)
605 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
606 GI_HW_ARM_ENA | mask, bits);
607 } else {
608 transient_bits |= GI_DISARM;
609 }
610 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
611 0, 0, transient_bits);
612 return 0;
613 }
614 EXPORT_SYMBOL_GPL(ni_tio_arm);
615
ni_660x_clk_src(unsigned int clock_source,unsigned int * bits)616 static int ni_660x_clk_src(unsigned int clock_source, unsigned int *bits)
617 {
618 unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
619 unsigned int ni_660x_clock;
620 unsigned int i;
621
622 switch (clk_src) {
623 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
624 ni_660x_clock = NI_660X_TIMEBASE_1_CLK;
625 break;
626 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
627 ni_660x_clock = NI_660X_TIMEBASE_2_CLK;
628 break;
629 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
630 ni_660x_clock = NI_660X_TIMEBASE_3_CLK;
631 break;
632 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
633 ni_660x_clock = NI_660X_LOGIC_LOW_CLK;
634 break;
635 case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
636 ni_660x_clock = NI_660X_SRC_PIN_I_CLK;
637 break;
638 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
639 ni_660x_clock = NI_660X_NEXT_GATE_CLK;
640 break;
641 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
642 ni_660x_clock = NI_660X_NEXT_TC_CLK;
643 break;
644 default:
645 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
646 if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
647 ni_660x_clock = NI_660X_RTSI_CLK(i);
648 break;
649 }
650 }
651 if (i <= NI_660X_MAX_RTSI_CHAN)
652 break;
653 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
654 if (clk_src == NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
655 ni_660x_clock = NI_660X_SRC_PIN_CLK(i);
656 break;
657 }
658 }
659 if (i <= NI_660X_MAX_SRC_PIN)
660 break;
661 return -EINVAL;
662 }
663 *bits = GI_SRC_SEL(ni_660x_clock);
664 return 0;
665 }
666
ni_m_clk_src(unsigned int clock_source,unsigned int * bits)667 static int ni_m_clk_src(unsigned int clock_source, unsigned int *bits)
668 {
669 unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
670 unsigned int ni_m_series_clock;
671 unsigned int i;
672
673 switch (clk_src) {
674 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
675 ni_m_series_clock = NI_M_TIMEBASE_1_CLK;
676 break;
677 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
678 ni_m_series_clock = NI_M_TIMEBASE_2_CLK;
679 break;
680 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
681 ni_m_series_clock = NI_M_TIMEBASE_3_CLK;
682 break;
683 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
684 ni_m_series_clock = NI_M_LOGIC_LOW_CLK;
685 break;
686 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
687 ni_m_series_clock = NI_M_NEXT_GATE_CLK;
688 break;
689 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
690 ni_m_series_clock = NI_M_NEXT_TC_CLK;
691 break;
692 case NI_GPCT_PXI10_CLOCK_SRC_BITS:
693 ni_m_series_clock = NI_M_PXI10_CLK;
694 break;
695 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
696 ni_m_series_clock = NI_M_PXI_STAR_TRIGGER_CLK;
697 break;
698 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
699 ni_m_series_clock = NI_M_ANALOG_TRIGGER_OUT_CLK;
700 break;
701 default:
702 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
703 if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
704 ni_m_series_clock = NI_M_RTSI_CLK(i);
705 break;
706 }
707 }
708 if (i <= NI_M_MAX_RTSI_CHAN)
709 break;
710 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
711 if (clk_src == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
712 ni_m_series_clock = NI_M_PFI_CLK(i);
713 break;
714 }
715 }
716 if (i <= NI_M_MAX_PFI_CHAN)
717 break;
718 return -EINVAL;
719 }
720 *bits = GI_SRC_SEL(ni_m_series_clock);
721 return 0;
722 };
723
ni_tio_set_source_subselect(struct ni_gpct * counter,unsigned int clock_source)724 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
725 unsigned int clock_source)
726 {
727 struct ni_gpct_device *counter_dev = counter->counter_dev;
728 unsigned int cidx = counter->counter_index;
729 unsigned int second_gate_reg = NITIO_GATE2_REG(cidx);
730
731 if (counter_dev->variant != ni_gpct_variant_m_series)
732 return;
733 switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
734 /* Gi_Source_Subselect is zero */
735 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
736 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
737 counter_dev->regs[second_gate_reg] &= ~GI_SRC_SUBSEL;
738 break;
739 /* Gi_Source_Subselect is one */
740 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
741 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
742 counter_dev->regs[second_gate_reg] |= GI_SRC_SUBSEL;
743 break;
744 /* Gi_Source_Subselect doesn't matter */
745 default:
746 return;
747 }
748 ni_tio_write(counter, counter_dev->regs[second_gate_reg],
749 second_gate_reg);
750 }
751
ni_tio_set_clock_src(struct ni_gpct * counter,unsigned int clock_source,unsigned int period_ns)752 static int ni_tio_set_clock_src(struct ni_gpct *counter,
753 unsigned int clock_source,
754 unsigned int period_ns)
755 {
756 struct ni_gpct_device *counter_dev = counter->counter_dev;
757 unsigned int cidx = counter->counter_index;
758 unsigned int bits = 0;
759 int ret;
760
761 switch (counter_dev->variant) {
762 case ni_gpct_variant_660x:
763 ret = ni_660x_clk_src(clock_source, &bits);
764 break;
765 case ni_gpct_variant_e_series:
766 case ni_gpct_variant_m_series:
767 default:
768 ret = ni_m_clk_src(clock_source, &bits);
769 break;
770 }
771 if (ret) {
772 struct comedi_device *dev = counter_dev->dev;
773
774 dev_err(dev->class_dev, "invalid clock source 0x%x\n",
775 clock_source);
776 return ret;
777 }
778
779 if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
780 bits |= GI_SRC_POL_INVERT;
781 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
782 GI_SRC_SEL_MASK | GI_SRC_POL_INVERT, bits);
783 ni_tio_set_source_subselect(counter, clock_source);
784
785 if (ni_tio_counting_mode_registers_present(counter_dev)) {
786 bits = 0;
787 switch (clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
788 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
789 break;
790 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
791 bits |= GI_PRESCALE_X2(counter_dev->variant);
792 break;
793 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
794 bits |= GI_PRESCALE_X8(counter_dev->variant);
795 break;
796 default:
797 return -EINVAL;
798 }
799 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
800 GI_PRESCALE_X2(counter_dev->variant) |
801 GI_PRESCALE_X8(counter_dev->variant), bits);
802 }
803 counter->clock_period_ps = period_ns * 1000;
804 ni_tio_set_sync_mode(counter);
805 return 0;
806 }
807
ni_tio_get_clock_src(struct ni_gpct * counter,unsigned int * clock_source,unsigned int * period_ns)808 static int ni_tio_get_clock_src(struct ni_gpct *counter,
809 unsigned int *clock_source,
810 unsigned int *period_ns)
811 {
812 u64 temp64;
813 int ret;
814
815 ret = ni_tio_generic_clock_src_select(counter, clock_source);
816 if (ret)
817 return ret;
818 ret = ni_tio_clock_period_ps(counter, *clock_source, &temp64);
819 if (ret)
820 return ret;
821 do_div(temp64, 1000); /* ps to ns */
822 *period_ns = temp64;
823 return 0;
824 }
825
ni_660x_set_gate(struct ni_gpct * counter,unsigned int gate_source)826 static int ni_660x_set_gate(struct ni_gpct *counter, unsigned int gate_source)
827 {
828 unsigned int chan = CR_CHAN(gate_source);
829 unsigned int cidx = counter->counter_index;
830 unsigned int gate_sel;
831 unsigned int i;
832
833 switch (chan) {
834 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
835 gate_sel = NI_660X_NEXT_SRC_GATE_SEL;
836 break;
837 case NI_GPCT_NEXT_OUT_GATE_SELECT:
838 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
839 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
840 case NI_GPCT_GATE_PIN_i_GATE_SELECT:
841 gate_sel = chan & 0x1f;
842 break;
843 default:
844 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
845 if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
846 gate_sel = chan & 0x1f;
847 break;
848 }
849 }
850 if (i <= NI_660X_MAX_RTSI_CHAN)
851 break;
852 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
853 if (chan == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
854 gate_sel = chan & 0x1f;
855 break;
856 }
857 }
858 if (i <= NI_660X_MAX_GATE_PIN)
859 break;
860 return -EINVAL;
861 }
862 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
863 GI_GATE_SEL_MASK, GI_GATE_SEL(gate_sel));
864 return 0;
865 }
866
ni_m_set_gate(struct ni_gpct * counter,unsigned int gate_source)867 static int ni_m_set_gate(struct ni_gpct *counter, unsigned int gate_source)
868 {
869 unsigned int chan = CR_CHAN(gate_source);
870 unsigned int cidx = counter->counter_index;
871 unsigned int gate_sel;
872 unsigned int i;
873
874 switch (chan) {
875 case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
876 case NI_GPCT_AI_START2_GATE_SELECT:
877 case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
878 case NI_GPCT_NEXT_OUT_GATE_SELECT:
879 case NI_GPCT_AI_START1_GATE_SELECT:
880 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
881 case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
882 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
883 gate_sel = chan & 0x1f;
884 break;
885 default:
886 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
887 if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
888 gate_sel = chan & 0x1f;
889 break;
890 }
891 }
892 if (i <= NI_M_MAX_RTSI_CHAN)
893 break;
894 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
895 if (chan == NI_GPCT_PFI_GATE_SELECT(i)) {
896 gate_sel = chan & 0x1f;
897 break;
898 }
899 }
900 if (i <= NI_M_MAX_PFI_CHAN)
901 break;
902 return -EINVAL;
903 }
904 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
905 GI_GATE_SEL_MASK, GI_GATE_SEL(gate_sel));
906 return 0;
907 }
908
ni_660x_set_gate2(struct ni_gpct * counter,unsigned int gate_source)909 static int ni_660x_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
910 {
911 struct ni_gpct_device *counter_dev = counter->counter_dev;
912 unsigned int cidx = counter->counter_index;
913 unsigned int chan = CR_CHAN(gate_source);
914 unsigned int gate2_reg = NITIO_GATE2_REG(cidx);
915 unsigned int gate2_sel;
916 unsigned int i;
917
918 switch (chan) {
919 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
920 case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
921 case NI_GPCT_SELECTED_GATE_GATE_SELECT:
922 case NI_GPCT_NEXT_OUT_GATE_SELECT:
923 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
924 gate2_sel = chan & 0x1f;
925 break;
926 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
927 gate2_sel = NI_660X_NEXT_SRC_GATE2_SEL;
928 break;
929 default:
930 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
931 if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
932 gate2_sel = chan & 0x1f;
933 break;
934 }
935 }
936 if (i <= NI_660X_MAX_RTSI_CHAN)
937 break;
938 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
939 if (chan == NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
940 gate2_sel = chan & 0x1f;
941 break;
942 }
943 }
944 if (i <= NI_660X_MAX_UP_DOWN_PIN)
945 break;
946 return -EINVAL;
947 }
948 counter_dev->regs[gate2_reg] |= GI_GATE2_MODE;
949 counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK;
950 counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel);
951 ni_tio_write(counter, counter_dev->regs[gate2_reg], gate2_reg);
952 return 0;
953 }
954
ni_m_set_gate2(struct ni_gpct * counter,unsigned int gate_source)955 static int ni_m_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
956 {
957 struct ni_gpct_device *counter_dev = counter->counter_dev;
958 unsigned int cidx = counter->counter_index;
959 unsigned int chan = CR_CHAN(gate_source);
960 unsigned int gate2_reg = NITIO_GATE2_REG(cidx);
961 unsigned int gate2_sel;
962
963 /*
964 * FIXME: We don't know what the m-series second gate codes are,
965 * so we'll just pass the bits through for now.
966 */
967 switch (chan) {
968 default:
969 gate2_sel = chan & 0x1f;
970 break;
971 }
972 counter_dev->regs[gate2_reg] |= GI_GATE2_MODE;
973 counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK;
974 counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel);
975 ni_tio_write(counter, counter_dev->regs[gate2_reg], gate2_reg);
976 return 0;
977 }
978
ni_tio_set_gate_src(struct ni_gpct * counter,unsigned int gate,unsigned int src)979 int ni_tio_set_gate_src(struct ni_gpct *counter,
980 unsigned int gate, unsigned int src)
981 {
982 struct ni_gpct_device *counter_dev = counter->counter_dev;
983 unsigned int cidx = counter->counter_index;
984 unsigned int chan = CR_CHAN(src);
985 unsigned int gate2_reg = NITIO_GATE2_REG(cidx);
986 unsigned int mode = 0;
987
988 switch (gate) {
989 case 0:
990 if (chan == NI_GPCT_DISABLED_GATE_SELECT) {
991 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
992 GI_GATING_MODE_MASK,
993 GI_GATING_DISABLED);
994 return 0;
995 }
996 if (src & CR_INVERT)
997 mode |= GI_GATE_POL_INVERT;
998 if (src & CR_EDGE)
999 mode |= GI_RISING_EDGE_GATING;
1000 else
1001 mode |= GI_LEVEL_GATING;
1002 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
1003 GI_GATE_POL_INVERT | GI_GATING_MODE_MASK,
1004 mode);
1005 switch (counter_dev->variant) {
1006 case ni_gpct_variant_e_series:
1007 case ni_gpct_variant_m_series:
1008 default:
1009 return ni_m_set_gate(counter, src);
1010 case ni_gpct_variant_660x:
1011 return ni_660x_set_gate(counter, src);
1012 }
1013 break;
1014 case 1:
1015 if (!ni_tio_has_gate2_registers(counter_dev))
1016 return -EINVAL;
1017
1018 if (chan == NI_GPCT_DISABLED_GATE_SELECT) {
1019 counter_dev->regs[gate2_reg] &= ~GI_GATE2_MODE;
1020 ni_tio_write(counter, counter_dev->regs[gate2_reg],
1021 gate2_reg);
1022 return 0;
1023 }
1024 if (src & CR_INVERT)
1025 counter_dev->regs[gate2_reg] |= GI_GATE2_POL_INVERT;
1026 else
1027 counter_dev->regs[gate2_reg] &= ~GI_GATE2_POL_INVERT;
1028 switch (counter_dev->variant) {
1029 case ni_gpct_variant_m_series:
1030 return ni_m_set_gate2(counter, src);
1031 case ni_gpct_variant_660x:
1032 return ni_660x_set_gate2(counter, src);
1033 default:
1034 return -EINVAL;
1035 }
1036 break;
1037 default:
1038 return -EINVAL;
1039 }
1040 return 0;
1041 }
1042 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
1043
ni_tio_set_other_src(struct ni_gpct * counter,unsigned int index,unsigned int source)1044 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned int index,
1045 unsigned int source)
1046 {
1047 struct ni_gpct_device *counter_dev = counter->counter_dev;
1048 unsigned int cidx = counter->counter_index;
1049 unsigned int abz_reg, shift, mask;
1050
1051 if (counter_dev->variant != ni_gpct_variant_m_series)
1052 return -EINVAL;
1053
1054 abz_reg = NITIO_ABZ_REG(cidx);
1055 switch (index) {
1056 case NI_GPCT_SOURCE_ENCODER_A:
1057 shift = 10;
1058 break;
1059 case NI_GPCT_SOURCE_ENCODER_B:
1060 shift = 5;
1061 break;
1062 case NI_GPCT_SOURCE_ENCODER_Z:
1063 shift = 0;
1064 break;
1065 default:
1066 return -EINVAL;
1067 }
1068 mask = 0x1f << shift;
1069 if (source > 0x1f)
1070 source = 0x1f; /* Disable gate */
1071
1072 counter_dev->regs[abz_reg] &= ~mask;
1073 counter_dev->regs[abz_reg] |= (source << shift) & mask;
1074 ni_tio_write(counter, counter_dev->regs[abz_reg], abz_reg);
1075 return 0;
1076 }
1077
ni_660x_gate_to_generic_gate(unsigned int gate,unsigned int * src)1078 static int ni_660x_gate_to_generic_gate(unsigned int gate, unsigned int *src)
1079 {
1080 unsigned int source;
1081 unsigned int i;
1082
1083 switch (gate) {
1084 case NI_660X_SRC_PIN_I_GATE_SEL:
1085 source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1086 break;
1087 case NI_660X_GATE_PIN_I_GATE_SEL:
1088 source = NI_GPCT_GATE_PIN_i_GATE_SELECT;
1089 break;
1090 case NI_660X_NEXT_SRC_GATE_SEL:
1091 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1092 break;
1093 case NI_660X_NEXT_OUT_GATE_SEL:
1094 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1095 break;
1096 case NI_660X_LOGIC_LOW_GATE_SEL:
1097 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1098 break;
1099 default:
1100 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1101 if (gate == NI_660X_RTSI_GATE_SEL(i)) {
1102 source = NI_GPCT_RTSI_GATE_SELECT(i);
1103 break;
1104 }
1105 }
1106 if (i <= NI_660X_MAX_RTSI_CHAN)
1107 break;
1108 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
1109 if (gate == NI_660X_PIN_GATE_SEL(i)) {
1110 source = NI_GPCT_GATE_PIN_GATE_SELECT(i);
1111 break;
1112 }
1113 }
1114 if (i <= NI_660X_MAX_GATE_PIN)
1115 break;
1116 return -EINVAL;
1117 }
1118 *src = source;
1119 return 0;
1120 };
1121
ni_m_gate_to_generic_gate(unsigned int gate,unsigned int * src)1122 static int ni_m_gate_to_generic_gate(unsigned int gate, unsigned int *src)
1123 {
1124 unsigned int source;
1125 unsigned int i;
1126
1127 switch (gate) {
1128 case NI_M_TIMESTAMP_MUX_GATE_SEL:
1129 source = NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1130 break;
1131 case NI_M_AI_START2_GATE_SEL:
1132 source = NI_GPCT_AI_START2_GATE_SELECT;
1133 break;
1134 case NI_M_PXI_STAR_TRIGGER_GATE_SEL:
1135 source = NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1136 break;
1137 case NI_M_NEXT_OUT_GATE_SEL:
1138 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1139 break;
1140 case NI_M_AI_START1_GATE_SEL:
1141 source = NI_GPCT_AI_START1_GATE_SELECT;
1142 break;
1143 case NI_M_NEXT_SRC_GATE_SEL:
1144 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1145 break;
1146 case NI_M_ANALOG_TRIG_OUT_GATE_SEL:
1147 source = NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1148 break;
1149 case NI_M_LOGIC_LOW_GATE_SEL:
1150 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1151 break;
1152 default:
1153 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
1154 if (gate == NI_M_RTSI_GATE_SEL(i)) {
1155 source = NI_GPCT_RTSI_GATE_SELECT(i);
1156 break;
1157 }
1158 }
1159 if (i <= NI_M_MAX_RTSI_CHAN)
1160 break;
1161 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
1162 if (gate == NI_M_PFI_GATE_SEL(i)) {
1163 source = NI_GPCT_PFI_GATE_SELECT(i);
1164 break;
1165 }
1166 }
1167 if (i <= NI_M_MAX_PFI_CHAN)
1168 break;
1169 return -EINVAL;
1170 }
1171 *src = source;
1172 return 0;
1173 };
1174
ni_660x_gate2_to_generic_gate(unsigned int gate,unsigned int * src)1175 static int ni_660x_gate2_to_generic_gate(unsigned int gate, unsigned int *src)
1176 {
1177 unsigned int source;
1178 unsigned int i;
1179
1180 switch (gate) {
1181 case NI_660X_SRC_PIN_I_GATE2_SEL:
1182 source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1183 break;
1184 case NI_660X_UD_PIN_I_GATE2_SEL:
1185 source = NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1186 break;
1187 case NI_660X_NEXT_SRC_GATE2_SEL:
1188 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1189 break;
1190 case NI_660X_NEXT_OUT_GATE2_SEL:
1191 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1192 break;
1193 case NI_660X_SELECTED_GATE2_SEL:
1194 source = NI_GPCT_SELECTED_GATE_GATE_SELECT;
1195 break;
1196 case NI_660X_LOGIC_LOW_GATE2_SEL:
1197 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1198 break;
1199 default:
1200 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1201 if (gate == NI_660X_RTSI_GATE2_SEL(i)) {
1202 source = NI_GPCT_RTSI_GATE_SELECT(i);
1203 break;
1204 }
1205 }
1206 if (i <= NI_660X_MAX_RTSI_CHAN)
1207 break;
1208 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
1209 if (gate == NI_660X_UD_PIN_GATE2_SEL(i)) {
1210 source = NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1211 break;
1212 }
1213 }
1214 if (i <= NI_660X_MAX_UP_DOWN_PIN)
1215 break;
1216 return -EINVAL;
1217 }
1218 *src = source;
1219 return 0;
1220 };
1221
ni_m_gate2_to_generic_gate(unsigned int gate,unsigned int * src)1222 static int ni_m_gate2_to_generic_gate(unsigned int gate, unsigned int *src)
1223 {
1224 /*
1225 * FIXME: the second gate sources for the m series are undocumented,
1226 * so we just return the raw bits for now.
1227 */
1228 *src = gate;
1229 return 0;
1230 };
1231
ni_tio_get_gate_src(struct ni_gpct * counter,unsigned int gate_index,unsigned int * gate_source)1232 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned int gate_index,
1233 unsigned int *gate_source)
1234 {
1235 struct ni_gpct_device *counter_dev = counter->counter_dev;
1236 unsigned int cidx = counter->counter_index;
1237 unsigned int mode;
1238 unsigned int reg;
1239 unsigned int gate;
1240 int ret;
1241
1242 mode = ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx));
1243 if (((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED) ||
1244 (gate_index == 1 &&
1245 !(counter_dev->regs[NITIO_GATE2_REG(cidx)] & GI_GATE2_MODE))) {
1246 *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1247 return 0;
1248 }
1249
1250 switch (gate_index) {
1251 case 0:
1252 reg = NITIO_INPUT_SEL_REG(cidx);
1253 gate = GI_BITS_TO_GATE(ni_tio_get_soft_copy(counter, reg));
1254
1255 switch (counter_dev->variant) {
1256 case ni_gpct_variant_e_series:
1257 case ni_gpct_variant_m_series:
1258 default:
1259 ret = ni_m_gate_to_generic_gate(gate, gate_source);
1260 break;
1261 case ni_gpct_variant_660x:
1262 ret = ni_660x_gate_to_generic_gate(gate, gate_source);
1263 break;
1264 }
1265 if (ret)
1266 return ret;
1267 if (mode & GI_GATE_POL_INVERT)
1268 *gate_source |= CR_INVERT;
1269 if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
1270 *gate_source |= CR_EDGE;
1271 break;
1272 case 1:
1273 reg = NITIO_GATE2_REG(cidx);
1274 gate = GI_BITS_TO_GATE2(counter_dev->regs[reg]);
1275
1276 switch (counter_dev->variant) {
1277 case ni_gpct_variant_e_series:
1278 case ni_gpct_variant_m_series:
1279 default:
1280 ret = ni_m_gate2_to_generic_gate(gate, gate_source);
1281 break;
1282 case ni_gpct_variant_660x:
1283 ret = ni_660x_gate2_to_generic_gate(gate, gate_source);
1284 break;
1285 }
1286 if (ret)
1287 return ret;
1288 if (counter_dev->regs[reg] & GI_GATE2_POL_INVERT)
1289 *gate_source |= CR_INVERT;
1290 /* second gate can't have edge/level mode set independently */
1291 if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
1292 *gate_source |= CR_EDGE;
1293 break;
1294 default:
1295 return -EINVAL;
1296 }
1297 return 0;
1298 }
1299
ni_tio_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)1300 int ni_tio_insn_config(struct comedi_device *dev,
1301 struct comedi_subdevice *s,
1302 struct comedi_insn *insn,
1303 unsigned int *data)
1304 {
1305 struct ni_gpct *counter = s->private;
1306 unsigned int cidx = counter->counter_index;
1307 unsigned int status;
1308 int ret = 0;
1309
1310 switch (data[0]) {
1311 case INSN_CONFIG_SET_COUNTER_MODE:
1312 ret = ni_tio_set_counter_mode(counter, data[1]);
1313 break;
1314 case INSN_CONFIG_ARM:
1315 ret = ni_tio_arm(counter, true, data[1]);
1316 break;
1317 case INSN_CONFIG_DISARM:
1318 ret = ni_tio_arm(counter, false, 0);
1319 break;
1320 case INSN_CONFIG_GET_COUNTER_STATUS:
1321 data[1] = 0;
1322 status = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx));
1323 if (status & GI_ARMED(cidx)) {
1324 data[1] |= COMEDI_COUNTER_ARMED;
1325 if (status & GI_COUNTING(cidx))
1326 data[1] |= COMEDI_COUNTER_COUNTING;
1327 }
1328 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
1329 break;
1330 case INSN_CONFIG_SET_CLOCK_SRC:
1331 ret = ni_tio_set_clock_src(counter, data[1], data[2]);
1332 break;
1333 case INSN_CONFIG_GET_CLOCK_SRC:
1334 ret = ni_tio_get_clock_src(counter, &data[1], &data[2]);
1335 break;
1336 case INSN_CONFIG_SET_GATE_SRC:
1337 ret = ni_tio_set_gate_src(counter, data[1], data[2]);
1338 break;
1339 case INSN_CONFIG_GET_GATE_SRC:
1340 ret = ni_tio_get_gate_src(counter, data[1], &data[2]);
1341 break;
1342 case INSN_CONFIG_SET_OTHER_SRC:
1343 ret = ni_tio_set_other_src(counter, data[1], data[2]);
1344 break;
1345 case INSN_CONFIG_RESET:
1346 ni_tio_reset_count_and_disarm(counter);
1347 break;
1348 default:
1349 return -EINVAL;
1350 }
1351 return ret ? ret : insn->n;
1352 }
1353 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1354
ni_tio_read_sw_save_reg(struct comedi_device * dev,struct comedi_subdevice * s)1355 static unsigned int ni_tio_read_sw_save_reg(struct comedi_device *dev,
1356 struct comedi_subdevice *s)
1357 {
1358 struct ni_gpct *counter = s->private;
1359 unsigned int cidx = counter->counter_index;
1360 unsigned int val;
1361
1362 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
1363 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1364 GI_SAVE_TRACE, GI_SAVE_TRACE);
1365
1366 /*
1367 * The count doesn't get latched until the next clock edge, so it is
1368 * possible the count may change (once) while we are reading. Since
1369 * the read of the SW_Save_Reg isn't atomic (apparently even when it's
1370 * a 32 bit register according to 660x docs), we need to read twice
1371 * and make sure the reading hasn't changed. If it has, a third read
1372 * will be correct since the count value will definitely have latched
1373 * by then.
1374 */
1375 val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx));
1376 if (val != ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx)))
1377 val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx));
1378
1379 return val;
1380 }
1381
ni_tio_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)1382 int ni_tio_insn_read(struct comedi_device *dev,
1383 struct comedi_subdevice *s,
1384 struct comedi_insn *insn,
1385 unsigned int *data)
1386 {
1387 struct ni_gpct *counter = s->private;
1388 struct ni_gpct_device *counter_dev = counter->counter_dev;
1389 unsigned int channel = CR_CHAN(insn->chanspec);
1390 unsigned int cidx = counter->counter_index;
1391 int i;
1392
1393 for (i = 0; i < insn->n; i++) {
1394 switch (channel) {
1395 case 0:
1396 data[i] = ni_tio_read_sw_save_reg(dev, s);
1397 break;
1398 case 1:
1399 data[i] = counter_dev->regs[NITIO_LOADA_REG(cidx)];
1400 break;
1401 case 2:
1402 data[i] = counter_dev->regs[NITIO_LOADB_REG(cidx)];
1403 break;
1404 }
1405 }
1406 return insn->n;
1407 }
1408 EXPORT_SYMBOL_GPL(ni_tio_insn_read);
1409
ni_tio_next_load_register(struct ni_gpct * counter)1410 static unsigned int ni_tio_next_load_register(struct ni_gpct *counter)
1411 {
1412 unsigned int cidx = counter->counter_index;
1413 unsigned int bits = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx));
1414
1415 return (bits & GI_NEXT_LOAD_SRC(cidx))
1416 ? NITIO_LOADB_REG(cidx)
1417 : NITIO_LOADA_REG(cidx);
1418 }
1419
ni_tio_insn_write(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)1420 int ni_tio_insn_write(struct comedi_device *dev,
1421 struct comedi_subdevice *s,
1422 struct comedi_insn *insn,
1423 unsigned int *data)
1424 {
1425 struct ni_gpct *counter = s->private;
1426 struct ni_gpct_device *counter_dev = counter->counter_dev;
1427 unsigned int channel = CR_CHAN(insn->chanspec);
1428 unsigned int cidx = counter->counter_index;
1429 unsigned int load_reg;
1430
1431 if (insn->n < 1)
1432 return 0;
1433 switch (channel) {
1434 case 0:
1435 /*
1436 * Unsafe if counter is armed.
1437 * Should probably check status and return -EBUSY if armed.
1438 */
1439
1440 /*
1441 * Don't disturb load source select, just use whichever
1442 * load register is already selected.
1443 */
1444 load_reg = ni_tio_next_load_register(counter);
1445 ni_tio_write(counter, data[0], load_reg);
1446 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
1447 0, 0, GI_LOAD);
1448 /* restore load reg */
1449 ni_tio_write(counter, counter_dev->regs[load_reg], load_reg);
1450 break;
1451 case 1:
1452 counter_dev->regs[NITIO_LOADA_REG(cidx)] = data[0];
1453 ni_tio_write(counter, data[0], NITIO_LOADA_REG(cidx));
1454 break;
1455 case 2:
1456 counter_dev->regs[NITIO_LOADB_REG(cidx)] = data[0];
1457 ni_tio_write(counter, data[0], NITIO_LOADB_REG(cidx));
1458 break;
1459 default:
1460 return -EINVAL;
1461 }
1462 return 0;
1463 }
1464 EXPORT_SYMBOL_GPL(ni_tio_insn_write);
1465
ni_tio_init_counter(struct ni_gpct * counter)1466 void ni_tio_init_counter(struct ni_gpct *counter)
1467 {
1468 struct ni_gpct_device *counter_dev = counter->counter_dev;
1469 unsigned int cidx = counter->counter_index;
1470
1471 ni_tio_reset_count_and_disarm(counter);
1472
1473 /* initialize counter registers */
1474 counter_dev->regs[NITIO_AUTO_INC_REG(cidx)] = 0x0;
1475 ni_tio_write(counter, 0x0, NITIO_AUTO_INC_REG(cidx));
1476
1477 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1478 ~0, GI_SYNC_GATE);
1479
1480 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0);
1481
1482 counter_dev->regs[NITIO_LOADA_REG(cidx)] = 0x0;
1483 ni_tio_write(counter, 0x0, NITIO_LOADA_REG(cidx));
1484
1485 counter_dev->regs[NITIO_LOADB_REG(cidx)] = 0x0;
1486 ni_tio_write(counter, 0x0, NITIO_LOADB_REG(cidx));
1487
1488 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0);
1489
1490 if (ni_tio_counting_mode_registers_present(counter_dev))
1491 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ~0, 0);
1492
1493 if (ni_tio_has_gate2_registers(counter_dev)) {
1494 counter_dev->regs[NITIO_GATE2_REG(cidx)] = 0x0;
1495 ni_tio_write(counter, 0x0, NITIO_GATE2_REG(cidx));
1496 }
1497
1498 ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0);
1499
1500 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ~0, 0x0);
1501 }
1502 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
1503
1504 struct ni_gpct_device *
ni_gpct_device_construct(struct comedi_device * dev,void (* write)(struct ni_gpct * counter,unsigned int value,enum ni_gpct_register reg),unsigned int (* read)(struct ni_gpct * counter,enum ni_gpct_register reg),enum ni_gpct_variant variant,unsigned int num_counters)1505 ni_gpct_device_construct(struct comedi_device *dev,
1506 void (*write)(struct ni_gpct *counter,
1507 unsigned int value,
1508 enum ni_gpct_register reg),
1509 unsigned int (*read)(struct ni_gpct *counter,
1510 enum ni_gpct_register reg),
1511 enum ni_gpct_variant variant,
1512 unsigned int num_counters)
1513 {
1514 struct ni_gpct_device *counter_dev;
1515 struct ni_gpct *counter;
1516 unsigned int i;
1517
1518 if (num_counters == 0)
1519 return NULL;
1520
1521 counter_dev = kzalloc(sizeof(*counter_dev), GFP_KERNEL);
1522 if (!counter_dev)
1523 return NULL;
1524
1525 counter_dev->dev = dev;
1526 counter_dev->write = write;
1527 counter_dev->read = read;
1528 counter_dev->variant = variant;
1529
1530 spin_lock_init(&counter_dev->regs_lock);
1531
1532 counter_dev->counters = kcalloc(num_counters, sizeof(*counter),
1533 GFP_KERNEL);
1534 if (!counter_dev->counters) {
1535 kfree(counter_dev);
1536 return NULL;
1537 }
1538
1539 for (i = 0; i < num_counters; ++i) {
1540 counter = &counter_dev->counters[i];
1541 counter->counter_dev = counter_dev;
1542 spin_lock_init(&counter->lock);
1543 }
1544 counter_dev->num_counters = num_counters;
1545
1546 return counter_dev;
1547 }
1548 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
1549
ni_gpct_device_destroy(struct ni_gpct_device * counter_dev)1550 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
1551 {
1552 if (!counter_dev)
1553 return;
1554 kfree(counter_dev->counters);
1555 kfree(counter_dev);
1556 }
1557 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
1558
ni_tio_init_module(void)1559 static int __init ni_tio_init_module(void)
1560 {
1561 return 0;
1562 }
1563 module_init(ni_tio_init_module);
1564
ni_tio_cleanup_module(void)1565 static void __exit ni_tio_cleanup_module(void)
1566 {
1567 }
1568 module_exit(ni_tio_cleanup_module);
1569
1570 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
1571 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
1572 MODULE_LICENSE("GPL");
1573