1 #ifndef _ASM_POWERPC_IO_H
2 #define _ASM_POWERPC_IO_H
3 #ifdef __KERNEL__
4
5 #define ARCH_HAS_IOREMAP_WC
6
7 /*
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14 /* Check of existence of legacy devices */
15 extern int check_legacy_ioport(unsigned long base_port);
16 #define I8042_DATA_REG 0x60
17 #define FDC_BASE 0x3f0
18
19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
20 extern struct pci_dev *isa_bridge_pcidev;
21 /*
22 * has legacy ISA devices ?
23 */
24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
25 #endif
26
27 #include <linux/device.h>
28 #include <linux/io.h>
29
30 #include <linux/compiler.h>
31 #include <asm/page.h>
32 #include <asm/byteorder.h>
33 #include <asm/synch.h>
34 #include <asm/delay.h>
35 #include <asm/mmu.h>
36
37 #include <asm-generic/iomap.h>
38
39 #ifdef CONFIG_PPC64
40 #include <asm/paca.h>
41 #endif
42
43 #define SIO_CONFIG_RA 0x398
44 #define SIO_CONFIG_RD 0x399
45
46 #define SLOW_DOWN_IO
47
48 /* 32 bits uses slightly different variables for the various IO
49 * bases. Most of this file only uses _IO_BASE though which we
50 * define properly based on the platform
51 */
52 #ifndef CONFIG_PCI
53 #define _IO_BASE 0
54 #define _ISA_MEM_BASE 0
55 #define PCI_DRAM_OFFSET 0
56 #elif defined(CONFIG_PPC32)
57 #define _IO_BASE isa_io_base
58 #define _ISA_MEM_BASE isa_mem_base
59 #define PCI_DRAM_OFFSET pci_dram_offset
60 #else
61 #define _IO_BASE pci_io_base
62 #define _ISA_MEM_BASE isa_mem_base
63 #define PCI_DRAM_OFFSET 0
64 #endif
65
66 extern unsigned long isa_io_base;
67 extern unsigned long pci_io_base;
68 extern unsigned long pci_dram_offset;
69
70 extern resource_size_t isa_mem_base;
71
72 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
73 * is not set or addresses cannot be translated to MMIO. This is typically
74 * set when the platform supports "special" PIO accesses via a non memory
75 * mapped mechanism, and allows things like the early udbg UART code to
76 * function.
77 */
78 extern bool isa_io_special;
79
80 #ifdef CONFIG_PPC32
81 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
82 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
83 #endif
84 #endif
85
86 /*
87 *
88 * Low level MMIO accessors
89 *
90 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
91 * specific and thus shouldn't be used in generic code. The accessors
92 * provided here are:
93 *
94 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
95 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
96 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
97 *
98 * Those operate directly on a kernel virtual address. Note that the prototype
99 * for the out_* accessors has the arguments in opposite order from the usual
100 * linux PCI accessors. Unlike those, they take the address first and the value
101 * next.
102 *
103 * Note: I might drop the _ns suffix on the stream operations soon as it is
104 * simply normal for stream operations to not swap in the first place.
105 *
106 */
107
108 #ifdef CONFIG_PPC64
109 #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0)
110 #else
111 #define IO_SET_SYNC_FLAG()
112 #endif
113
114 /* gcc 4.0 and older doesn't have 'Z' constraint */
115 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
116 #define DEF_MMIO_IN_X(name, size, insn) \
117 static inline u##size name(const volatile u##size __iomem *addr) \
118 { \
119 u##size ret; \
120 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \
121 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \
122 return ret; \
123 }
124
125 #define DEF_MMIO_OUT_X(name, size, insn) \
126 static inline void name(volatile u##size __iomem *addr, u##size val) \
127 { \
128 __asm__ __volatile__("sync;"#insn" %1,0,%2" \
129 : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \
130 IO_SET_SYNC_FLAG(); \
131 }
132 #else /* newer gcc */
133 #define DEF_MMIO_IN_X(name, size, insn) \
134 static inline u##size name(const volatile u##size __iomem *addr) \
135 { \
136 u##size ret; \
137 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
138 : "=r" (ret) : "Z" (*addr) : "memory"); \
139 return ret; \
140 }
141
142 #define DEF_MMIO_OUT_X(name, size, insn) \
143 static inline void name(volatile u##size __iomem *addr, u##size val) \
144 { \
145 __asm__ __volatile__("sync;"#insn" %1,%y0" \
146 : "=Z" (*addr) : "r" (val) : "memory"); \
147 IO_SET_SYNC_FLAG(); \
148 }
149 #endif
150
151 #define DEF_MMIO_IN_D(name, size, insn) \
152 static inline u##size name(const volatile u##size __iomem *addr) \
153 { \
154 u##size ret; \
155 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
156 : "=r" (ret) : "m" (*addr) : "memory"); \
157 return ret; \
158 }
159
160 #define DEF_MMIO_OUT_D(name, size, insn) \
161 static inline void name(volatile u##size __iomem *addr, u##size val) \
162 { \
163 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
164 : "=m" (*addr) : "r" (val) : "memory"); \
165 IO_SET_SYNC_FLAG(); \
166 }
167
168 DEF_MMIO_IN_D(in_8, 8, lbz);
169 DEF_MMIO_OUT_D(out_8, 8, stb);
170
171 #ifdef __BIG_ENDIAN__
172 DEF_MMIO_IN_D(in_be16, 16, lhz);
173 DEF_MMIO_IN_D(in_be32, 32, lwz);
174 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
175 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
176
177 DEF_MMIO_OUT_D(out_be16, 16, sth);
178 DEF_MMIO_OUT_D(out_be32, 32, stw);
179 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
180 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
181 #else
182 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
183 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
184 DEF_MMIO_IN_D(in_le16, 16, lhz);
185 DEF_MMIO_IN_D(in_le32, 32, lwz);
186
187 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
188 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
189 DEF_MMIO_OUT_D(out_le16, 16, sth);
190 DEF_MMIO_OUT_D(out_le32, 32, stw);
191
192 #endif /* __BIG_ENDIAN */
193
194 /*
195 * Cache inhibitied accessors for use in real mode, you don't want to use these
196 * unless you know what you're doing.
197 *
198 * NB. These use the cpu byte ordering.
199 */
200 DEF_MMIO_OUT_X(out_rm8, 8, stbcix);
201 DEF_MMIO_OUT_X(out_rm16, 16, sthcix);
202 DEF_MMIO_OUT_X(out_rm32, 32, stwcix);
203 DEF_MMIO_IN_X(in_rm8, 8, lbzcix);
204 DEF_MMIO_IN_X(in_rm16, 16, lhzcix);
205 DEF_MMIO_IN_X(in_rm32, 32, lwzcix);
206
207 #ifdef __powerpc64__
208
209 DEF_MMIO_OUT_X(out_rm64, 64, stdcix);
210 DEF_MMIO_IN_X(in_rm64, 64, ldcix);
211
212 #ifdef __BIG_ENDIAN__
213 DEF_MMIO_OUT_D(out_be64, 64, std);
214 DEF_MMIO_IN_D(in_be64, 64, ld);
215
216 /* There is no asm instructions for 64 bits reverse loads and stores */
in_le64(const volatile u64 __iomem * addr)217 static inline u64 in_le64(const volatile u64 __iomem *addr)
218 {
219 return swab64(in_be64(addr));
220 }
221
out_le64(volatile u64 __iomem * addr,u64 val)222 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
223 {
224 out_be64(addr, swab64(val));
225 }
226 #else
227 DEF_MMIO_OUT_D(out_le64, 64, std);
228 DEF_MMIO_IN_D(in_le64, 64, ld);
229
230 /* There is no asm instructions for 64 bits reverse loads and stores */
in_be64(const volatile u64 __iomem * addr)231 static inline u64 in_be64(const volatile u64 __iomem *addr)
232 {
233 return swab64(in_le64(addr));
234 }
235
out_be64(volatile u64 __iomem * addr,u64 val)236 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
237 {
238 out_le64(addr, swab64(val));
239 }
240
241 #endif
242 #endif /* __powerpc64__ */
243
244
245 /*
246 * Simple Cache inhibited accessors
247 * Unlike the DEF_MMIO_* macros, these don't include any h/w memory
248 * barriers, callers need to manage memory barriers on their own.
249 * These can only be used in hypervisor real mode.
250 */
251
_lwzcix(unsigned long addr)252 static inline u32 _lwzcix(unsigned long addr)
253 {
254 u32 ret;
255
256 __asm__ __volatile__("lwzcix %0,0, %1"
257 : "=r" (ret) : "r" (addr) : "memory");
258 return ret;
259 }
260
_stbcix(u64 addr,u8 val)261 static inline void _stbcix(u64 addr, u8 val)
262 {
263 __asm__ __volatile__("stbcix %0,0,%1"
264 : : "r" (val), "r" (addr) : "memory");
265 }
266
_stwcix(u64 addr,u32 val)267 static inline void _stwcix(u64 addr, u32 val)
268 {
269 __asm__ __volatile__("stwcix %0,0,%1"
270 : : "r" (val), "r" (addr) : "memory");
271 }
272
273 /*
274 * Low level IO stream instructions are defined out of line for now
275 */
276 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
277 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
278 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
279 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
280 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
281 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
282
283 /* The _ns naming is historical and will be removed. For now, just #define
284 * the non _ns equivalent names
285 */
286 #define _insw _insw_ns
287 #define _insl _insl_ns
288 #define _outsw _outsw_ns
289 #define _outsl _outsl_ns
290
291
292 /*
293 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
294 */
295
296 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
297 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
298 unsigned long n);
299 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
300 unsigned long n);
301
302 /*
303 *
304 * PCI and standard ISA accessors
305 *
306 * Those are globally defined linux accessors for devices on PCI or ISA
307 * busses. They follow the Linux defined semantics. The current implementation
308 * for PowerPC is as close as possible to the x86 version of these, and thus
309 * provides fairly heavy weight barriers for the non-raw versions
310 *
311 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
312 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
313 * own implementation of some or all of the accessors.
314 */
315
316 /*
317 * Include the EEH definitions when EEH is enabled only so they don't get
318 * in the way when building for 32 bits
319 */
320 #ifdef CONFIG_EEH
321 #include <asm/eeh.h>
322 #endif
323
324 /* Shortcut to the MMIO argument pointer */
325 #define PCI_IO_ADDR volatile void __iomem *
326
327 /* Indirect IO address tokens:
328 *
329 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
330 * on all MMIOs. (Note that this is all 64 bits only for now)
331 *
332 * To help platforms who may need to differentiate MMIO addresses in
333 * their hooks, a bitfield is reserved for use by the platform near the
334 * top of MMIO addresses (not PIO, those have to cope the hard way).
335 *
336 * This bit field is 12 bits and is at the top of the IO virtual
337 * addresses PCI_IO_INDIRECT_TOKEN_MASK.
338 *
339 * The kernel virtual space is thus:
340 *
341 * 0xD000000000000000 : vmalloc
342 * 0xD000080000000000 : PCI PHB IO space
343 * 0xD000080080000000 : ioremap
344 * 0xD0000fffffffffff : end of ioremap region
345 *
346 * Since the top 4 bits are reserved as the region ID, we use thus
347 * the next 12 bits and keep 4 bits available for the future if the
348 * virtual address space is ever to be extended.
349 *
350 * The direct IO mapping operations will then mask off those bits
351 * before doing the actual access, though that only happen when
352 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
353 * mechanism
354 *
355 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
356 * all PIO functions call through a hook.
357 */
358
359 #ifdef CONFIG_PPC_INDIRECT_MMIO
360 #define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul
361 #define PCI_IO_IND_TOKEN_SHIFT 48
362 #define PCI_FIX_ADDR(addr) \
363 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
364 #define PCI_GET_ADDR_TOKEN(addr) \
365 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
366 PCI_IO_IND_TOKEN_SHIFT)
367 #define PCI_SET_ADDR_TOKEN(addr, token) \
368 do { \
369 unsigned long __a = (unsigned long)(addr); \
370 __a &= ~PCI_IO_IND_TOKEN_MASK; \
371 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
372 (addr) = (void __iomem *)__a; \
373 } while(0)
374 #else
375 #define PCI_FIX_ADDR(addr) (addr)
376 #endif
377
378
379 /*
380 * Non ordered and non-swapping "raw" accessors
381 */
382
__raw_readb(const volatile void __iomem * addr)383 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
384 {
385 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
386 }
__raw_readw(const volatile void __iomem * addr)387 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
388 {
389 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
390 }
__raw_readl(const volatile void __iomem * addr)391 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
392 {
393 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
394 }
__raw_writeb(unsigned char v,volatile void __iomem * addr)395 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
396 {
397 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
398 }
__raw_writew(unsigned short v,volatile void __iomem * addr)399 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
400 {
401 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
402 }
__raw_writel(unsigned int v,volatile void __iomem * addr)403 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
404 {
405 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
406 }
407
408 #ifdef __powerpc64__
__raw_readq(const volatile void __iomem * addr)409 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
410 {
411 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
412 }
__raw_writeq(unsigned long v,volatile void __iomem * addr)413 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
414 {
415 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
416 }
417
418 /*
419 * Real mode version of the above. stdcix is only supposed to be used
420 * in hypervisor real mode as per the architecture spec.
421 */
__raw_rm_writeq(u64 val,volatile void __iomem * paddr)422 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
423 {
424 __asm__ __volatile__("stdcix %0,0,%1"
425 : : "r" (val), "r" (paddr) : "memory");
426 }
427
428 #endif /* __powerpc64__ */
429
430 /*
431 *
432 * PCI PIO and MMIO accessors.
433 *
434 *
435 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
436 * machine checks (which they occasionally do when probing non existing
437 * IO ports on some platforms, like PowerMac and 8xx).
438 * I always found it to be of dubious reliability and I am tempted to get
439 * rid of it one of these days. So if you think it's important to keep it,
440 * please voice up asap. We never had it for 64 bits and I do not intend
441 * to port it over
442 */
443
444 #ifdef CONFIG_PPC32
445
446 #define __do_in_asm(name, op) \
447 static inline unsigned int name(unsigned int port) \
448 { \
449 unsigned int x; \
450 __asm__ __volatile__( \
451 "sync\n" \
452 "0:" op " %0,0,%1\n" \
453 "1: twi 0,%0,0\n" \
454 "2: isync\n" \
455 "3: nop\n" \
456 "4:\n" \
457 ".section .fixup,\"ax\"\n" \
458 "5: li %0,-1\n" \
459 " b 4b\n" \
460 ".previous\n" \
461 ".section __ex_table,\"a\"\n" \
462 " .align 2\n" \
463 " .long 0b,5b\n" \
464 " .long 1b,5b\n" \
465 " .long 2b,5b\n" \
466 " .long 3b,5b\n" \
467 ".previous" \
468 : "=&r" (x) \
469 : "r" (port + _IO_BASE) \
470 : "memory"); \
471 return x; \
472 }
473
474 #define __do_out_asm(name, op) \
475 static inline void name(unsigned int val, unsigned int port) \
476 { \
477 __asm__ __volatile__( \
478 "sync\n" \
479 "0:" op " %0,0,%1\n" \
480 "1: sync\n" \
481 "2:\n" \
482 ".section __ex_table,\"a\"\n" \
483 " .align 2\n" \
484 " .long 0b,2b\n" \
485 " .long 1b,2b\n" \
486 ".previous" \
487 : : "r" (val), "r" (port + _IO_BASE) \
488 : "memory"); \
489 }
490
491 __do_in_asm(_rec_inb, "lbzx")
492 __do_in_asm(_rec_inw, "lhbrx")
493 __do_in_asm(_rec_inl, "lwbrx")
494 __do_out_asm(_rec_outb, "stbx")
495 __do_out_asm(_rec_outw, "sthbrx")
496 __do_out_asm(_rec_outl, "stwbrx")
497
498 #endif /* CONFIG_PPC32 */
499
500 /* The "__do_*" operations below provide the actual "base" implementation
501 * for each of the defined accessors. Some of them use the out_* functions
502 * directly, some of them still use EEH, though we might change that in the
503 * future. Those macros below provide the necessary argument swapping and
504 * handling of the IO base for PIO.
505 *
506 * They are themselves used by the macros that define the actual accessors
507 * and can be used by the hooks if any.
508 *
509 * Note that PIO operations are always defined in terms of their corresonding
510 * MMIO operations. That allows platforms like iSeries who want to modify the
511 * behaviour of both to only hook on the MMIO version and get both. It's also
512 * possible to hook directly at the toplevel PIO operation if they have to
513 * be handled differently
514 */
515 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
516 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
517 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
518 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
519 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
520 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
521 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
522
523 #ifdef CONFIG_EEH
524 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
525 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
526 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
527 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
528 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
529 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
530 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
531 #else /* CONFIG_EEH */
532 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
533 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
534 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
535 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
536 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
537 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
538 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
539 #endif /* !defined(CONFIG_EEH) */
540
541 #ifdef CONFIG_PPC32
542 #define __do_outb(val, port) _rec_outb(val, port)
543 #define __do_outw(val, port) _rec_outw(val, port)
544 #define __do_outl(val, port) _rec_outl(val, port)
545 #define __do_inb(port) _rec_inb(port)
546 #define __do_inw(port) _rec_inw(port)
547 #define __do_inl(port) _rec_inl(port)
548 #else /* CONFIG_PPC32 */
549 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
550 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
551 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
552 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
553 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
554 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
555 #endif /* !CONFIG_PPC32 */
556
557 #ifdef CONFIG_EEH
558 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
559 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
560 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
561 #else /* CONFIG_EEH */
562 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
563 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
564 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
565 #endif /* !CONFIG_EEH */
566 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
567 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
568 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
569
570 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
571 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
572 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
573 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
574 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
575 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
576
577 #define __do_memset_io(addr, c, n) \
578 _memset_io(PCI_FIX_ADDR(addr), c, n)
579 #define __do_memcpy_toio(dst, src, n) \
580 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
581
582 #ifdef CONFIG_EEH
583 #define __do_memcpy_fromio(dst, src, n) \
584 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
585 #else /* CONFIG_EEH */
586 #define __do_memcpy_fromio(dst, src, n) \
587 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
588 #endif /* !CONFIG_EEH */
589
590 #ifdef CONFIG_PPC_INDIRECT_PIO
591 #define DEF_PCI_HOOK_pio(x) x
592 #else
593 #define DEF_PCI_HOOK_pio(x) NULL
594 #endif
595
596 #ifdef CONFIG_PPC_INDIRECT_MMIO
597 #define DEF_PCI_HOOK_mem(x) x
598 #else
599 #define DEF_PCI_HOOK_mem(x) NULL
600 #endif
601
602 /* Structure containing all the hooks */
603 extern struct ppc_pci_io {
604
605 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
606 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
607
608 #include <asm/io-defs.h>
609
610 #undef DEF_PCI_AC_RET
611 #undef DEF_PCI_AC_NORET
612
613 } ppc_pci_io;
614
615 /* The inline wrappers */
616 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
617 static inline ret name at \
618 { \
619 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
620 return ppc_pci_io.name al; \
621 return __do_##name al; \
622 }
623
624 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
625 static inline void name at \
626 { \
627 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
628 ppc_pci_io.name al; \
629 else \
630 __do_##name al; \
631 }
632
633 #include <asm/io-defs.h>
634
635 #undef DEF_PCI_AC_RET
636 #undef DEF_PCI_AC_NORET
637
638 /* Some drivers check for the presence of readq & writeq with
639 * a #ifdef, so we make them happy here.
640 */
641 #ifdef __powerpc64__
642 #define readq readq
643 #define writeq writeq
644 #endif
645
646 /*
647 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
648 * access
649 */
650 #define xlate_dev_mem_ptr(p) __va(p)
651
652 /*
653 * Convert a virtual cached pointer to an uncached pointer
654 */
655 #define xlate_dev_kmem_ptr(p) p
656
657 /*
658 * We don't do relaxed operations yet, at least not with this semantic
659 */
660 #define readb_relaxed(addr) readb(addr)
661 #define readw_relaxed(addr) readw(addr)
662 #define readl_relaxed(addr) readl(addr)
663 #define readq_relaxed(addr) readq(addr)
664 #define writeb_relaxed(v, addr) writeb(v, addr)
665 #define writew_relaxed(v, addr) writew(v, addr)
666 #define writel_relaxed(v, addr) writel(v, addr)
667 #define writeq_relaxed(v, addr) writeq(v, addr)
668
669 #ifdef CONFIG_PPC32
670 #define mmiowb()
671 #else
672 /*
673 * Enforce synchronisation of stores vs. spin_unlock
674 * (this does it explicitly, though our implementation of spin_unlock
675 * does it implicitely too)
676 */
mmiowb(void)677 static inline void mmiowb(void)
678 {
679 unsigned long tmp;
680
681 __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
682 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
683 : "memory");
684 }
685 #endif /* !CONFIG_PPC32 */
686
iosync(void)687 static inline void iosync(void)
688 {
689 __asm__ __volatile__ ("sync" : : : "memory");
690 }
691
692 /* Enforce in-order execution of data I/O.
693 * No distinction between read/write on PPC; use eieio for all three.
694 * Those are fairly week though. They don't provide a barrier between
695 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
696 * they only provide barriers between 2 __raw MMIO operations and
697 * possibly break write combining.
698 */
699 #define iobarrier_rw() eieio()
700 #define iobarrier_r() eieio()
701 #define iobarrier_w() eieio()
702
703
704 /*
705 * output pause versions need a delay at least for the
706 * w83c105 ide controller in a p610.
707 */
708 #define inb_p(port) inb(port)
709 #define outb_p(val, port) (udelay(1), outb((val), (port)))
710 #define inw_p(port) inw(port)
711 #define outw_p(val, port) (udelay(1), outw((val), (port)))
712 #define inl_p(port) inl(port)
713 #define outl_p(val, port) (udelay(1), outl((val), (port)))
714
715
716 #define IO_SPACE_LIMIT ~(0UL)
717
718
719 /**
720 * ioremap - map bus memory into CPU space
721 * @address: bus address of the memory
722 * @size: size of the resource to map
723 *
724 * ioremap performs a platform specific sequence of operations to
725 * make bus memory CPU accessible via the readb/readw/readl/writeb/
726 * writew/writel functions and the other mmio helpers. The returned
727 * address is not guaranteed to be usable directly as a virtual
728 * address.
729 *
730 * We provide a few variations of it:
731 *
732 * * ioremap is the standard one and provides non-cacheable guarded mappings
733 * and can be hooked by the platform via ppc_md
734 *
735 * * ioremap_prot allows to specify the page flags as an argument and can
736 * also be hooked by the platform via ppc_md.
737 *
738 * * ioremap_nocache is identical to ioremap
739 *
740 * * ioremap_wc enables write combining
741 *
742 * * iounmap undoes such a mapping and can be hooked
743 *
744 * * __ioremap_at (and the pending __iounmap_at) are low level functions to
745 * create hand-made mappings for use only by the PCI code and cannot
746 * currently be hooked. Must be page aligned.
747 *
748 * * __ioremap is the low level implementation used by ioremap and
749 * ioremap_prot and cannot be hooked (but can be used by a hook on one
750 * of the previous ones)
751 *
752 * * __ioremap_caller is the same as above but takes an explicit caller
753 * reference rather than using __builtin_return_address(0)
754 *
755 * * __iounmap, is the low level implementation used by iounmap and cannot
756 * be hooked (but can be used by a hook on iounmap)
757 *
758 */
759 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
760 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
761 unsigned long flags);
762 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
763 #define ioremap_nocache(addr, size) ioremap((addr), (size))
764 #define ioremap_uc(addr, size) ioremap((addr), (size))
765
766 extern void iounmap(volatile void __iomem *addr);
767
768 extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
769 unsigned long flags);
770 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
771 unsigned long flags, void *caller);
772
773 extern void __iounmap(volatile void __iomem *addr);
774
775 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
776 unsigned long size, unsigned long flags);
777 extern void __iounmap_at(void *ea, unsigned long size);
778
779 /*
780 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
781 * which needs some additional definitions here. They basically allow PIO
782 * space overall to be 1GB. This will work as long as we never try to use
783 * iomap to map MMIO below 1GB which should be fine on ppc64
784 */
785 #define HAVE_ARCH_PIO_SIZE 1
786 #define PIO_OFFSET 0x00000000UL
787 #define PIO_MASK (FULL_IO_SIZE - 1)
788 #define PIO_RESERVED (FULL_IO_SIZE)
789
790 #define mmio_read16be(addr) readw_be(addr)
791 #define mmio_read32be(addr) readl_be(addr)
792 #define mmio_write16be(val, addr) writew_be(val, addr)
793 #define mmio_write32be(val, addr) writel_be(val, addr)
794 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
795 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
796 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
797 #define mmio_outsb(addr, src, count) writesb(addr, src, count)
798 #define mmio_outsw(addr, src, count) writesw(addr, src, count)
799 #define mmio_outsl(addr, src, count) writesl(addr, src, count)
800
801 /**
802 * virt_to_phys - map virtual addresses to physical
803 * @address: address to remap
804 *
805 * The returned physical address is the physical (CPU) mapping for
806 * the memory address given. It is only valid to use this function on
807 * addresses directly mapped or allocated via kmalloc.
808 *
809 * This function does not give bus mappings for DMA transfers. In
810 * almost all conceivable cases a device driver should not be using
811 * this function
812 */
virt_to_phys(volatile void * address)813 static inline unsigned long virt_to_phys(volatile void * address)
814 {
815 return __pa((unsigned long)address);
816 }
817
818 /**
819 * phys_to_virt - map physical address to virtual
820 * @address: address to remap
821 *
822 * The returned virtual address is a current CPU mapping for
823 * the memory address given. It is only valid to use this function on
824 * addresses that have a kernel mapping
825 *
826 * This function does not handle bus mappings for DMA transfers. In
827 * almost all conceivable cases a device driver should not be using
828 * this function
829 */
phys_to_virt(unsigned long address)830 static inline void * phys_to_virt(unsigned long address)
831 {
832 return (void *)__va(address);
833 }
834
835 /*
836 * Change "struct page" to physical address.
837 */
838 #define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)
839
840 /*
841 * 32 bits still uses virt_to_bus() for it's implementation of DMA
842 * mappings se we have to keep it defined here. We also have some old
843 * drivers (shame shame shame) that use bus_to_virt() and haven't been
844 * fixed yet so I need to define it here.
845 */
846 #ifdef CONFIG_PPC32
847
virt_to_bus(volatile void * address)848 static inline unsigned long virt_to_bus(volatile void * address)
849 {
850 if (address == NULL)
851 return 0;
852 return __pa(address) + PCI_DRAM_OFFSET;
853 }
854
bus_to_virt(unsigned long address)855 static inline void * bus_to_virt(unsigned long address)
856 {
857 if (address == 0)
858 return NULL;
859 return __va(address - PCI_DRAM_OFFSET);
860 }
861
862 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
863
864 #endif /* CONFIG_PPC32 */
865
866 /* access ports */
867 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
868 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
869
870 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
871 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
872
873 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
874 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
875
876 /* Clear and set bits in one shot. These macros can be used to clear and
877 * set multiple bits in a register using a single read-modify-write. These
878 * macros can also be used to set a multiple-bit bit pattern using a mask,
879 * by specifying the mask in the 'clear' parameter and the new bit pattern
880 * in the 'set' parameter.
881 */
882
883 #define clrsetbits(type, addr, clear, set) \
884 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
885
886 #ifdef __powerpc64__
887 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
888 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
889 #endif
890
891 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
892 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
893
894 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
895 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
896
897 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
898
899 #endif /* __KERNEL__ */
900
901 #endif /* _ASM_POWERPC_IO_H */
902