1 /*
2 * Copyright 2014 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/errno.h>
16 #include <linux/spinlock.h>
17 #include <linux/module.h>
18 #include <linux/atomic.h>
19
20 #include <asm/processor.h>
21 #include <asm/pmc.h>
22
23 perf_irq_t perf_irq = NULL;
handle_perf_interrupt(struct pt_regs * regs,int fault)24 int handle_perf_interrupt(struct pt_regs *regs, int fault)
25 {
26 int retval;
27
28 if (!perf_irq)
29 panic("Unexpected PERF_COUNT interrupt %d\n", fault);
30
31 retval = perf_irq(regs, fault);
32 return retval;
33 }
34
35 /* Reserve PMC hardware if it is available. */
reserve_pmc_hardware(perf_irq_t new_perf_irq)36 perf_irq_t reserve_pmc_hardware(perf_irq_t new_perf_irq)
37 {
38 return cmpxchg(&perf_irq, NULL, new_perf_irq);
39 }
40 EXPORT_SYMBOL(reserve_pmc_hardware);
41
42 /* Release PMC hardware. */
release_pmc_hardware(void)43 void release_pmc_hardware(void)
44 {
45 perf_irq = NULL;
46 }
47 EXPORT_SYMBOL(release_pmc_hardware);
48
49
50 /*
51 * Get current overflow status of each performance counter,
52 * and auxiliary performance counter.
53 */
54 unsigned long
pmc_get_overflow(void)55 pmc_get_overflow(void)
56 {
57 unsigned long status;
58
59 /*
60 * merge base+aux into a single vector
61 */
62 status = __insn_mfspr(SPR_PERF_COUNT_STS);
63 status |= __insn_mfspr(SPR_AUX_PERF_COUNT_STS) << TILE_BASE_COUNTERS;
64 return status;
65 }
66
67 /*
68 * Clear the status bit for the corresponding counter, if written
69 * with a one.
70 */
71 void
pmc_ack_overflow(unsigned long status)72 pmc_ack_overflow(unsigned long status)
73 {
74 /*
75 * clear overflow status by writing ones
76 */
77 __insn_mtspr(SPR_PERF_COUNT_STS, status);
78 __insn_mtspr(SPR_AUX_PERF_COUNT_STS, status >> TILE_BASE_COUNTERS);
79 }
80
81 /*
82 * The perf count interrupts are masked and unmasked explicitly,
83 * and only here. The normal irq_enable() does not enable them,
84 * and irq_disable() does not disable them. That lets these
85 * routines drive the perf count interrupts orthogonally.
86 *
87 * We also mask the perf count interrupts on entry to the perf count
88 * interrupt handler in assembly code, and by default unmask them
89 * again (with interrupt critical section protection) just before
90 * returning from the interrupt. If the perf count handler returns
91 * a non-zero error code, then we don't re-enable them before returning.
92 *
93 * For Pro, we rely on both interrupts being in the same word to update
94 * them atomically so we never have one enabled and one disabled.
95 */
96
97 #if CHIP_HAS_SPLIT_INTR_MASK()
98 # if INT_PERF_COUNT < 32 || INT_AUX_PERF_COUNT < 32
99 # error Fix assumptions about which word PERF_COUNT interrupts are in
100 # endif
101 #endif
102
pmc_mask(void)103 static inline unsigned long long pmc_mask(void)
104 {
105 unsigned long long mask = 1ULL << INT_PERF_COUNT;
106 mask |= 1ULL << INT_AUX_PERF_COUNT;
107 return mask;
108 }
109
unmask_pmc_interrupts(void)110 void unmask_pmc_interrupts(void)
111 {
112 interrupt_mask_reset_mask(pmc_mask());
113 }
114
mask_pmc_interrupts(void)115 void mask_pmc_interrupts(void)
116 {
117 interrupt_mask_set_mask(pmc_mask());
118 }
119