1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "smumgr.h"
25 #include "smu74.h"
26 #include "smu_ucode_xfer_vi.h"
27 #include "polaris10_smumgr.h"
28 #include "smu74_discrete.h"
29 #include "smu/smu_7_1_3_d.h"
30 #include "smu/smu_7_1_3_sh_mask.h"
31 #include "gmc/gmc_8_1_d.h"
32 #include "gmc/gmc_8_1_sh_mask.h"
33 #include "oss/oss_3_0_d.h"
34 #include "gca/gfx_8_0_d.h"
35 #include "bif/bif_5_0_d.h"
36 #include "bif/bif_5_0_sh_mask.h"
37 #include "polaris10_pwrvirus.h"
38 #include "ppatomctrl.h"
39 #include "pp_debug.h"
40 #include "cgs_common.h"
41 #include "polaris10_smc.h"
42 #include "smu7_ppsmc.h"
43 #include "smu7_smumgr.h"
44
45 #define PPPOLARIS10_TARGETACTIVITY_DFLT 50
46
47 static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
48 /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */
49 /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
50 { 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
51 { 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
52 { 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } },
53 { 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
54 { 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } },
55 { 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
56 { 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } },
57 { 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }
58 };
59
60 static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
61 0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
62
63
polaris10_setup_pwr_virus(struct pp_smumgr * smumgr)64 static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
65 {
66 int i;
67 int result = -1;
68 uint32_t reg, data;
69
70 const PWR_Command_Table *pvirus = pwr_virus_table;
71 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
72
73
74 for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
75 switch (pvirus->command) {
76 case PwrCmdWrite:
77 reg = pvirus->reg;
78 data = pvirus->data;
79 cgs_write_register(smumgr->device, reg, data);
80 break;
81
82 case PwrCmdEnd:
83 result = 0;
84 break;
85
86 default:
87 printk("Table Exit with Invalid Command!");
88 smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
89 result = -1;
90 break;
91 }
92 pvirus++;
93 }
94
95 return result;
96 }
97
polaris10_perform_btc(struct pp_smumgr * smumgr)98 static int polaris10_perform_btc(struct pp_smumgr *smumgr)
99 {
100 int result = 0;
101 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
102
103 if (0 != smu_data->avfs.avfs_btc_param) {
104 if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
105 printk("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
106 result = -1;
107 }
108 }
109 if (smu_data->avfs.avfs_btc_param > 1) {
110 /* Soft-Reset to reset the engine before loading uCode */
111 /* halt */
112 cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000);
113 /* reset everything */
114 cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
115 cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
116 }
117 return result;
118 }
119
120
polaris10_setup_graphics_level_structure(struct pp_smumgr * smumgr)121 int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
122 {
123 uint32_t vr_config;
124 uint32_t dpm_table_start;
125
126 uint16_t u16_boot_mvdd;
127 uint32_t graphics_level_address, vr_config_address, graphics_level_size;
128
129 graphics_level_size = sizeof(avfs_graphics_level_polaris10);
130 u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
131
132 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr,
133 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
134 &dpm_table_start, 0x40000),
135 "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
136 return -1);
137
138 /* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
139 vr_config = 0x01000500; /* Real value:0x50001 */
140
141 vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
142
143 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_address,
144 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
145 "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
146 return -1);
147
148 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
149
150 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
151 (uint8_t *)(&avfs_graphics_level_polaris10),
152 graphics_level_size, 0x40000),
153 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
154 return -1);
155
156 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
157
158 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
159 (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
160 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
161 return -1);
162
163 /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
164
165 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
166
167 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
168 (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
169 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
170 return -1);
171
172 return 0;
173 }
174
polaris10_avfs_event_mgr(struct pp_smumgr * smumgr,bool SMU_VFT_INTACT)175 int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
176 {
177 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
178
179 switch (smu_data->avfs.avfs_btc_status) {
180 case AVFS_BTC_COMPLETED_PREVIOUSLY:
181 break;
182
183 case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
184
185 smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
186 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(smumgr),
187 "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
188 return -1);
189
190 if (smu_data->avfs.avfs_btc_param > 1) {
191 printk("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
192 smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
193 PP_ASSERT_WITH_CODE(-1 == polaris10_setup_pwr_virus(smumgr),
194 "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
195 return -1);
196 }
197
198 smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
199 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(smumgr),
200 "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
201 return -1);
202
203 break;
204
205 case AVFS_BTC_DISABLED:
206 case AVFS_BTC_NOTSUPPORTED:
207 break;
208
209 default:
210 printk("[AVFS] Something is broken. See log!");
211 break;
212 }
213
214 return 0;
215 }
216
polaris10_start_smu_in_protection_mode(struct pp_smumgr * smumgr)217 static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
218 {
219 int result = 0;
220
221 /* Wait for smc boot up */
222 /* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
223
224 /* Assert reset */
225 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
226 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
227
228 result = smu7_upload_smu_firmware_image(smumgr);
229 if (result != 0)
230 return result;
231
232 /* Clear status */
233 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
234
235 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
236 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
237
238 /* De-assert reset */
239 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
240 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
241
242
243 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
244
245
246 /* Call Test SMU message with 0x20000 offset to trigger SMU start */
247 smu7_send_msg_to_smc_offset(smumgr);
248
249 /* Wait done bit to be set */
250 /* Check pass/failed indicator */
251
252 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
253
254 if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
255 SMU_STATUS, SMU_PASS))
256 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
257
258 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
259
260 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
261 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
262
263 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
264 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
265
266 /* Wait for firmware to initialize */
267 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
268
269 return result;
270 }
271
polaris10_start_smu_in_non_protection_mode(struct pp_smumgr * smumgr)272 static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
273 {
274 int result = 0;
275
276 /* wait for smc boot up */
277 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
278
279 /* Clear firmware interrupt enable flag */
280 /* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
281 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
282 ixFIRMWARE_FLAGS, 0);
283
284 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
285 SMC_SYSCON_RESET_CNTL,
286 rst_reg, 1);
287
288 result = smu7_upload_smu_firmware_image(smumgr);
289 if (result != 0)
290 return result;
291
292 /* Set smc instruct start point at 0x0 */
293 smu7_program_jump_on_start(smumgr);
294
295 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
296 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
297
298 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
299 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
300
301 /* Wait for firmware to initialize */
302
303 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
304 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
305
306 return result;
307 }
308
polaris10_start_smu(struct pp_smumgr * smumgr)309 static int polaris10_start_smu(struct pp_smumgr *smumgr)
310 {
311 int result = 0;
312 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
313 bool SMU_VFT_INTACT;
314
315 /* Only start SMC if SMC RAM is not running */
316 if (!smu7_is_smc_ram_running(smumgr)) {
317 SMU_VFT_INTACT = false;
318 smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
319 smu_data->smu7_data.security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
320
321 /* Check if SMU is running in protected mode */
322 if (smu_data->protected_mode == 0) {
323 result = polaris10_start_smu_in_non_protection_mode(smumgr);
324 } else {
325 result = polaris10_start_smu_in_protection_mode(smumgr);
326
327 /* If failed, try with different security Key. */
328 if (result != 0) {
329 smu_data->smu7_data.security_hard_key ^= 1;
330 result = polaris10_start_smu_in_protection_mode(smumgr);
331 }
332 }
333
334 if (result != 0)
335 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
336
337 polaris10_avfs_event_mgr(smumgr, true);
338 } else
339 SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
340
341 polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT);
342 /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
343 smu7_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
344 &(smu_data->smu7_data.soft_regs_start), 0x40000);
345
346 result = smu7_request_smu_load_fw(smumgr);
347
348 return result;
349 }
350
polaris10_is_hw_avfs_present(struct pp_smumgr * smumgr)351 static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr)
352 {
353 uint32_t efuse;
354
355 efuse = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
356 efuse &= 0x00000001;
357 if (efuse)
358 return true;
359
360 return false;
361 }
362
polaris10_smu_init(struct pp_smumgr * smumgr)363 static int polaris10_smu_init(struct pp_smumgr *smumgr)
364 {
365 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
366 int i;
367
368 if (smu7_init(smumgr))
369 return -EINVAL;
370
371 if (polaris10_is_hw_avfs_present(smumgr))
372 smu_data->avfs.avfs_btc_status = AVFS_BTC_BOOT;
373 else
374 smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;
375
376 for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++)
377 smu_data->activity_target[i] = PPPOLARIS10_TARGETACTIVITY_DFLT;
378
379 return 0;
380 }
381
382 static const struct pp_smumgr_func polaris10_smu_funcs = {
383 .smu_init = polaris10_smu_init,
384 .smu_fini = smu7_smu_fini,
385 .start_smu = polaris10_start_smu,
386 .check_fw_load_finish = smu7_check_fw_load_finish,
387 .request_smu_load_fw = smu7_reload_firmware,
388 .request_smu_load_specific_fw = NULL,
389 .send_msg_to_smc = smu7_send_msg_to_smc,
390 .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
391 .download_pptable_settings = NULL,
392 .upload_pptable_settings = NULL,
393 .update_smc_table = polaris10_update_smc_table,
394 .get_offsetof = polaris10_get_offsetof,
395 .process_firmware_header = polaris10_process_firmware_header,
396 .init_smc_table = polaris10_init_smc_table,
397 .update_sclk_threshold = polaris10_update_sclk_threshold,
398 .thermal_avfs_enable = polaris10_thermal_avfs_enable,
399 .thermal_setup_fan_table = polaris10_thermal_setup_fan_table,
400 .populate_all_graphic_levels = polaris10_populate_all_graphic_levels,
401 .populate_all_memory_levels = polaris10_populate_all_memory_levels,
402 .get_mac_definition = polaris10_get_mac_definition,
403 .is_dpm_running = polaris10_is_dpm_running,
404 };
405
polaris10_smum_init(struct pp_smumgr * smumgr)406 int polaris10_smum_init(struct pp_smumgr *smumgr)
407 {
408 struct polaris10_smumgr *polaris10_smu = NULL;
409
410 polaris10_smu = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
411
412 if (polaris10_smu == NULL)
413 return -EINVAL;
414
415 smumgr->backend = polaris10_smu;
416 smumgr->smumgr_funcs = &polaris10_smu_funcs;
417
418 return 0;
419 }
420