1 /*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16 #ifndef __ASM_PGTABLE_H
17 #define __ASM_PGTABLE_H
18
19 #include <asm/bug.h>
20 #include <asm/proc-fns.h>
21
22 #include <asm/memory.h>
23 #include <asm/pgtable-hwdef.h>
24 #include <asm/pgtable-prot.h>
25
26 /*
27 * VMALLOC range.
28 *
29 * VMALLOC_START: beginning of the kernel vmalloc space
30 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space
31 * and fixed mappings
32 */
33 #define VMALLOC_START (MODULES_END)
34 #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
35
36 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
37
38 #define FIRST_USER_ADDRESS 0UL
39
40 #ifndef __ASSEMBLY__
41
42 #include <asm/fixmap.h>
43 #include <linux/mmdebug.h>
44
45 extern void __pte_error(const char *file, int line, unsigned long val);
46 extern void __pmd_error(const char *file, int line, unsigned long val);
47 extern void __pud_error(const char *file, int line, unsigned long val);
48 extern void __pgd_error(const char *file, int line, unsigned long val);
49
50 /*
51 * ZERO_PAGE is a global shared page that is always zero: used
52 * for zero-mapped memory areas etc..
53 */
54 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
55 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page))
56
57 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
58
59 #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
60
61 #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
62
63 #define pte_none(pte) (!pte_val(pte))
64 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
65 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
66
67 /*
68 * The following only work if pte_present(). Undefined behaviour otherwise.
69 */
70 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
71 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
72 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
73 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
74 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
75 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
76
77 #ifdef CONFIG_ARM64_HW_AFDBM
78 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
79 #else
80 #define pte_hw_dirty(pte) (0)
81 #endif
82 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
83 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
84
85 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
86 /*
87 * Execute-only user mappings do not have the PTE_USER bit set. All valid
88 * kernel mappings have the PTE_UXN bit set.
89 */
90 #define pte_valid_not_user(pte) \
91 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN))
92 #define pte_valid_young(pte) \
93 ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF))
94 #define pte_valid_user(pte) \
95 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
96
97 /*
98 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
99 * so that we don't erroneously return false for pages that have been
100 * remapped as PROT_NONE but are yet to be flushed from the TLB.
101 */
102 #define pte_accessible(mm, pte) \
103 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte))
104
105 /*
106 * p??_access_permitted() is true for valid user mappings (subject to the
107 * write permission check) other than user execute-only which do not have the
108 * PTE_USER bit set. PROT_NONE mappings do not have the PTE_VALID bit set.
109 */
110 #define pte_access_permitted(pte, write) \
111 (pte_valid_user(pte) && (!(write) || pte_write(pte)))
112 #define pmd_access_permitted(pmd, write) \
113 (pte_access_permitted(pmd_pte(pmd), (write)))
114 #define pud_access_permitted(pud, write) \
115 (pte_access_permitted(pud_pte(pud), (write)))
116
clear_pte_bit(pte_t pte,pgprot_t prot)117 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
118 {
119 pte_val(pte) &= ~pgprot_val(prot);
120 return pte;
121 }
122
set_pte_bit(pte_t pte,pgprot_t prot)123 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
124 {
125 pte_val(pte) |= pgprot_val(prot);
126 return pte;
127 }
128
pte_wrprotect(pte_t pte)129 static inline pte_t pte_wrprotect(pte_t pte)
130 {
131 return clear_pte_bit(pte, __pgprot(PTE_WRITE));
132 }
133
pte_mkwrite(pte_t pte)134 static inline pte_t pte_mkwrite(pte_t pte)
135 {
136 return set_pte_bit(pte, __pgprot(PTE_WRITE));
137 }
138
pte_mkclean(pte_t pte)139 static inline pte_t pte_mkclean(pte_t pte)
140 {
141 return clear_pte_bit(pte, __pgprot(PTE_DIRTY));
142 }
143
pte_mkdirty(pte_t pte)144 static inline pte_t pte_mkdirty(pte_t pte)
145 {
146 return set_pte_bit(pte, __pgprot(PTE_DIRTY));
147 }
148
pte_mkold(pte_t pte)149 static inline pte_t pte_mkold(pte_t pte)
150 {
151 return clear_pte_bit(pte, __pgprot(PTE_AF));
152 }
153
pte_mkyoung(pte_t pte)154 static inline pte_t pte_mkyoung(pte_t pte)
155 {
156 return set_pte_bit(pte, __pgprot(PTE_AF));
157 }
158
pte_mkspecial(pte_t pte)159 static inline pte_t pte_mkspecial(pte_t pte)
160 {
161 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
162 }
163
pte_mkcont(pte_t pte)164 static inline pte_t pte_mkcont(pte_t pte)
165 {
166 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
167 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
168 }
169
pte_mknoncont(pte_t pte)170 static inline pte_t pte_mknoncont(pte_t pte)
171 {
172 return clear_pte_bit(pte, __pgprot(PTE_CONT));
173 }
174
pte_clear_rdonly(pte_t pte)175 static inline pte_t pte_clear_rdonly(pte_t pte)
176 {
177 return clear_pte_bit(pte, __pgprot(PTE_RDONLY));
178 }
179
pte_mkpresent(pte_t pte)180 static inline pte_t pte_mkpresent(pte_t pte)
181 {
182 return set_pte_bit(pte, __pgprot(PTE_VALID));
183 }
184
pmd_mkcont(pmd_t pmd)185 static inline pmd_t pmd_mkcont(pmd_t pmd)
186 {
187 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
188 }
189
set_pte(pte_t * ptep,pte_t pte)190 static inline void set_pte(pte_t *ptep, pte_t pte)
191 {
192 *ptep = pte;
193
194 /*
195 * Only if the new pte is valid and kernel, otherwise TLB maintenance
196 * or update_mmu_cache() have the necessary barriers.
197 */
198 if (pte_valid_not_user(pte)) {
199 dsb(ishst);
200 isb();
201 }
202 }
203
204 struct mm_struct;
205 struct vm_area_struct;
206
207 extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
208
209 /*
210 * PTE bits configuration in the presence of hardware Dirty Bit Management
211 * (PTE_WRITE == PTE_DBM):
212 *
213 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
214 * 0 0 | 1 0 0
215 * 0 1 | 1 1 0
216 * 1 0 | 1 0 1
217 * 1 1 | 0 1 x
218 *
219 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
220 * the page fault mechanism. Checking the dirty status of a pte becomes:
221 *
222 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
223 */
set_pte_at(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pte)224 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
225 pte_t *ptep, pte_t pte)
226 {
227 if (pte_present(pte)) {
228 if (pte_sw_dirty(pte) && pte_write(pte))
229 pte_val(pte) &= ~PTE_RDONLY;
230 else
231 pte_val(pte) |= PTE_RDONLY;
232 if (pte_user_exec(pte) && !pte_special(pte))
233 __sync_icache_dcache(pte, addr);
234 }
235
236 /*
237 * If the existing pte is valid, check for potential race with
238 * hardware updates of the pte (ptep_set_access_flags safely changes
239 * valid ptes without going through an invalid entry).
240 */
241 if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) &&
242 pte_valid(*ptep) && pte_valid(pte)) {
243 VM_WARN_ONCE(!pte_young(pte),
244 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
245 __func__, pte_val(*ptep), pte_val(pte));
246 VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(pte),
247 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
248 __func__, pte_val(*ptep), pte_val(pte));
249 }
250
251 set_pte(ptep, pte);
252 }
253
254 #define __HAVE_ARCH_PTE_SAME
pte_same(pte_t pte_a,pte_t pte_b)255 static inline int pte_same(pte_t pte_a, pte_t pte_b)
256 {
257 pteval_t lhs, rhs;
258
259 lhs = pte_val(pte_a);
260 rhs = pte_val(pte_b);
261
262 if (pte_present(pte_a))
263 lhs &= ~PTE_RDONLY;
264
265 if (pte_present(pte_b))
266 rhs &= ~PTE_RDONLY;
267
268 return (lhs == rhs);
269 }
270
271 /*
272 * Huge pte definitions.
273 */
274 #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT))
275 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
276
277 /*
278 * Hugetlb definitions.
279 */
280 #define HUGE_MAX_HSTATE 4
281 #define HPAGE_SHIFT PMD_SHIFT
282 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
283 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
284 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
285
286 #define __HAVE_ARCH_PTE_SPECIAL
287
pud_pte(pud_t pud)288 static inline pte_t pud_pte(pud_t pud)
289 {
290 return __pte(pud_val(pud));
291 }
292
pud_pmd(pud_t pud)293 static inline pmd_t pud_pmd(pud_t pud)
294 {
295 return __pmd(pud_val(pud));
296 }
297
pmd_pte(pmd_t pmd)298 static inline pte_t pmd_pte(pmd_t pmd)
299 {
300 return __pte(pmd_val(pmd));
301 }
302
pte_pmd(pte_t pte)303 static inline pmd_t pte_pmd(pte_t pte)
304 {
305 return __pmd(pte_val(pte));
306 }
307
mk_sect_prot(pgprot_t prot)308 static inline pgprot_t mk_sect_prot(pgprot_t prot)
309 {
310 return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT);
311 }
312
313 #ifdef CONFIG_NUMA_BALANCING
314 /*
315 * See the comment in include/asm-generic/pgtable.h
316 */
pte_protnone(pte_t pte)317 static inline int pte_protnone(pte_t pte)
318 {
319 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
320 }
321
pmd_protnone(pmd_t pmd)322 static inline int pmd_protnone(pmd_t pmd)
323 {
324 return pte_protnone(pmd_pte(pmd));
325 }
326 #endif
327
328 /*
329 * THP definitions.
330 */
331
332 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
333 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
334 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
335
336 #define pmd_present(pmd) pte_present(pmd_pte(pmd))
337 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
338 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
339 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
340 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
341 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
342 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
343 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
344 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
345 #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID))
346
347 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
348
349 #define __HAVE_ARCH_PMD_WRITE
350 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
351
352 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
353
354 #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
355 #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
356 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
357
358 #define pud_write(pud) pte_write(pud_pte(pud))
359 #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
360
361 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
362
363 #define __pgprot_modify(prot,mask,bits) \
364 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
365
366 /*
367 * Mark the prot value as uncacheable and unbufferable.
368 */
369 #define pgprot_noncached(prot) \
370 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
371 #define pgprot_writecombine(prot) \
372 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
373 #define pgprot_device(prot) \
374 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
375 #define __HAVE_PHYS_MEM_ACCESS_PROT
376 struct file;
377 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
378 unsigned long size, pgprot_t vma_prot);
379
380 #define pmd_none(pmd) (!pmd_val(pmd))
381
382 #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT))
383
384 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
385 PMD_TYPE_TABLE)
386 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
387 PMD_TYPE_SECT)
388
389 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
390 #define pud_sect(pud) (0)
391 #define pud_table(pud) (1)
392 #else
393 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
394 PUD_TYPE_SECT)
395 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
396 PUD_TYPE_TABLE)
397 #endif
398
set_pmd(pmd_t * pmdp,pmd_t pmd)399 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
400 {
401 *pmdp = pmd;
402 dsb(ishst);
403 isb();
404 }
405
pmd_clear(pmd_t * pmdp)406 static inline void pmd_clear(pmd_t *pmdp)
407 {
408 set_pmd(pmdp, __pmd(0));
409 }
410
pmd_page_paddr(pmd_t pmd)411 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
412 {
413 return pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK;
414 }
415
416 /* Find an entry in the third-level page table. */
417 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
418
419 #define pte_offset_phys(dir,addr) (pmd_page_paddr(*(dir)) + pte_index(addr) * sizeof(pte_t))
420 #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr))))
421
422 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
423 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
424 #define pte_unmap(pte) do { } while (0)
425 #define pte_unmap_nested(pte) do { } while (0)
426
427 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
428 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
429 #define pte_clear_fixmap() clear_fixmap(FIX_PTE)
430
431 #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
432
433 /* use ONLY for statically allocated translation tables */
434 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
435
436 /*
437 * Conversion functions: convert a page and protection to a page entry,
438 * and a page entry and page directory to the page they refer to.
439 */
440 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
441
442 #if CONFIG_PGTABLE_LEVELS > 2
443
444 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
445
446 #define pud_none(pud) (!pud_val(pud))
447 #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT))
448 #define pud_present(pud) (pud_val(pud))
449
set_pud(pud_t * pudp,pud_t pud)450 static inline void set_pud(pud_t *pudp, pud_t pud)
451 {
452 *pudp = pud;
453 dsb(ishst);
454 isb();
455 }
456
pud_clear(pud_t * pudp)457 static inline void pud_clear(pud_t *pudp)
458 {
459 set_pud(pudp, __pud(0));
460 }
461
pud_page_paddr(pud_t pud)462 static inline phys_addr_t pud_page_paddr(pud_t pud)
463 {
464 return pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK;
465 }
466
467 /* Find an entry in the second-level page table. */
468 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
469
470 #define pmd_offset_phys(dir, addr) (pud_page_paddr(*(dir)) + pmd_index(addr) * sizeof(pmd_t))
471 #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr))))
472
473 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
474 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
475 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
476
477 #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK))
478
479 /* use ONLY for statically allocated translation tables */
480 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
481
482 #else
483
484 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
485
486 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
487 #define pmd_set_fixmap(addr) NULL
488 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
489 #define pmd_clear_fixmap()
490
491 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
492
493 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
494
495 #if CONFIG_PGTABLE_LEVELS > 3
496
497 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
498
499 #define pgd_none(pgd) (!pgd_val(pgd))
500 #define pgd_bad(pgd) (!(pgd_val(pgd) & 2))
501 #define pgd_present(pgd) (pgd_val(pgd))
502
set_pgd(pgd_t * pgdp,pgd_t pgd)503 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
504 {
505 *pgdp = pgd;
506 dsb(ishst);
507 }
508
pgd_clear(pgd_t * pgdp)509 static inline void pgd_clear(pgd_t *pgdp)
510 {
511 set_pgd(pgdp, __pgd(0));
512 }
513
pgd_page_paddr(pgd_t pgd)514 static inline phys_addr_t pgd_page_paddr(pgd_t pgd)
515 {
516 return pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK;
517 }
518
519 /* Find an entry in the frst-level page table. */
520 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
521
522 #define pud_offset_phys(dir, addr) (pgd_page_paddr(*(dir)) + pud_index(addr) * sizeof(pud_t))
523 #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr))))
524
525 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
526 #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr))
527 #define pud_clear_fixmap() clear_fixmap(FIX_PUD)
528
529 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK))
530
531 /* use ONLY for statically allocated translation tables */
532 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
533
534 #else
535
536 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;})
537
538 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
539 #define pud_set_fixmap(addr) NULL
540 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
541 #define pud_clear_fixmap()
542
543 #define pud_offset_kimg(dir,addr) ((pud_t *)dir)
544
545 #endif /* CONFIG_PGTABLE_LEVELS > 3 */
546
547 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
548
549 /* to find an entry in a page-table-directory */
550 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
551
552 #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr))
553
554 #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr)))
555
556 /* to find an entry in a kernel page-table-directory */
557 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
558
559 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
560 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
561
pte_modify(pte_t pte,pgprot_t newprot)562 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
563 {
564 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
565 PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
566 /* preserve the hardware dirty information */
567 if (pte_hw_dirty(pte))
568 pte = pte_mkdirty(pte);
569 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
570 return pte;
571 }
572
pmd_modify(pmd_t pmd,pgprot_t newprot)573 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
574 {
575 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
576 }
577
578 #ifdef CONFIG_ARM64_HW_AFDBM
579 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
580 extern int ptep_set_access_flags(struct vm_area_struct *vma,
581 unsigned long address, pte_t *ptep,
582 pte_t entry, int dirty);
583
584 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
585 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
pmdp_set_access_flags(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp,pmd_t entry,int dirty)586 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
587 unsigned long address, pmd_t *pmdp,
588 pmd_t entry, int dirty)
589 {
590 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
591 }
592 #endif
593
594 /*
595 * Atomic pte/pmd modifications.
596 */
597 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
__ptep_test_and_clear_young(pte_t * ptep)598 static inline int __ptep_test_and_clear_young(pte_t *ptep)
599 {
600 pteval_t pteval;
601 unsigned int tmp, res;
602
603 asm volatile("// __ptep_test_and_clear_young\n"
604 " prfm pstl1strm, %2\n"
605 "1: ldxr %0, %2\n"
606 " ubfx %w3, %w0, %5, #1 // extract PTE_AF (young)\n"
607 " and %0, %0, %4 // clear PTE_AF\n"
608 " stxr %w1, %0, %2\n"
609 " cbnz %w1, 1b\n"
610 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res)
611 : "L" (~PTE_AF), "I" (ilog2(PTE_AF)));
612
613 return res;
614 }
615
ptep_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)616 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
617 unsigned long address,
618 pte_t *ptep)
619 {
620 return __ptep_test_and_clear_young(ptep);
621 }
622
623 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
624 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
pmdp_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp)625 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
626 unsigned long address,
627 pmd_t *pmdp)
628 {
629 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
630 }
631 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
632
633 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
ptep_get_and_clear(struct mm_struct * mm,unsigned long address,pte_t * ptep)634 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
635 unsigned long address, pte_t *ptep)
636 {
637 pteval_t old_pteval;
638 unsigned int tmp;
639
640 asm volatile("// ptep_get_and_clear\n"
641 " prfm pstl1strm, %2\n"
642 "1: ldxr %0, %2\n"
643 " stxr %w1, xzr, %2\n"
644 " cbnz %w1, 1b\n"
645 : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)));
646
647 return __pte(old_pteval);
648 }
649
650 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
651 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
pmdp_huge_get_and_clear(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)652 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
653 unsigned long address, pmd_t *pmdp)
654 {
655 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
656 }
657 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
658
659 /*
660 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
661 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
662 */
663 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
ptep_set_wrprotect(struct mm_struct * mm,unsigned long address,pte_t * ptep)664 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
665 {
666 pteval_t pteval;
667 unsigned long tmp;
668
669 asm volatile("// ptep_set_wrprotect\n"
670 " prfm pstl1strm, %2\n"
671 "1: ldxr %0, %2\n"
672 " tst %0, %4 // check for hw dirty (!PTE_RDONLY)\n"
673 " csel %1, %3, xzr, eq // set PTE_DIRTY|PTE_RDONLY if dirty\n"
674 " orr %0, %0, %1 // if !dirty, PTE_RDONLY is already set\n"
675 " and %0, %0, %5 // clear PTE_WRITE/PTE_DBM\n"
676 " stxr %w1, %0, %2\n"
677 " cbnz %w1, 1b\n"
678 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))
679 : "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE)
680 : "cc");
681 }
682
683 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
684 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
pmdp_set_wrprotect(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)685 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
686 unsigned long address, pmd_t *pmdp)
687 {
688 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
689 }
690 #endif
691 #endif /* CONFIG_ARM64_HW_AFDBM */
692
693 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
694 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
695 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
696
697 /*
698 * Encode and decode a swap entry:
699 * bits 0-1: present (must be zero)
700 * bits 2-7: swap type
701 * bits 8-57: swap offset
702 * bit 58: PTE_PROT_NONE (must be zero)
703 */
704 #define __SWP_TYPE_SHIFT 2
705 #define __SWP_TYPE_BITS 6
706 #define __SWP_OFFSET_BITS 50
707 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
708 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
709 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
710
711 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
712 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
713 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
714
715 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
716 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
717
718 /*
719 * Ensure that there are not more swap files than can be encoded in the kernel
720 * PTEs.
721 */
722 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
723
724 extern int kern_addr_valid(unsigned long addr);
725
726 #include <asm-generic/pgtable.h>
727
728 void pgd_cache_init(void);
729 #define pgtable_cache_init pgd_cache_init
730
731 /*
732 * On AArch64, the cache coherency is handled via the set_pte_at() function.
733 */
update_mmu_cache(struct vm_area_struct * vma,unsigned long addr,pte_t * ptep)734 static inline void update_mmu_cache(struct vm_area_struct *vma,
735 unsigned long addr, pte_t *ptep)
736 {
737 /*
738 * We don't do anything here, so there's a very small chance of
739 * us retaking a user fault which we just fixed up. The alternative
740 * is doing a dsb(ishst), but that penalises the fastpath.
741 */
742 }
743
744 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
745
746 #define kc_vaddr_to_offset(v) ((v) & ~VA_START)
747 #define kc_offset_to_vaddr(o) ((o) | VA_START)
748
749 #endif /* !__ASSEMBLY__ */
750
751 #endif /* __ASM_PGTABLE_H */
752