1 /*
2 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 * Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
7 *
8 * Description:
9 * General Purpose functions for the global management of the
10 * QUICC Engine (QE).
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/param.h>
21 #include <linux/string.h>
22 #include <linux/spinlock.h>
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/delay.h>
27 #include <linux/ioport.h>
28 #include <linux/crc32.h>
29 #include <linux/mod_devicetable.h>
30 #include <linux/of_platform.h>
31 #include <asm/irq.h>
32 #include <asm/page.h>
33 #include <asm/pgtable.h>
34 #include <soc/fsl/qe/immap_qe.h>
35 #include <soc/fsl/qe/qe.h>
36 #include <asm/prom.h>
37 #include <asm/rheap.h>
38
39 static void qe_snums_init(void);
40 static int qe_sdma_init(void);
41
42 static DEFINE_SPINLOCK(qe_lock);
43 DEFINE_SPINLOCK(cmxgcr_lock);
44 EXPORT_SYMBOL(cmxgcr_lock);
45
46 /* QE snum state */
47 enum qe_snum_state {
48 QE_SNUM_STATE_USED,
49 QE_SNUM_STATE_FREE
50 };
51
52 /* QE snum */
53 struct qe_snum {
54 u8 num;
55 enum qe_snum_state state;
56 };
57
58 /* We allocate this here because it is used almost exclusively for
59 * the communication processor devices.
60 */
61 struct qe_immap __iomem *qe_immr;
62 EXPORT_SYMBOL(qe_immr);
63
64 static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
65 static unsigned int qe_num_of_snum;
66
67 static phys_addr_t qebase = -1;
68
get_qe_base(void)69 phys_addr_t get_qe_base(void)
70 {
71 struct device_node *qe;
72 int ret;
73 struct resource res;
74
75 if (qebase != -1)
76 return qebase;
77
78 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
79 if (!qe) {
80 qe = of_find_node_by_type(NULL, "qe");
81 if (!qe)
82 return qebase;
83 }
84
85 ret = of_address_to_resource(qe, 0, &res);
86 if (!ret)
87 qebase = res.start;
88 of_node_put(qe);
89
90 return qebase;
91 }
92
93 EXPORT_SYMBOL(get_qe_base);
94
qe_reset(void)95 void qe_reset(void)
96 {
97 if (qe_immr == NULL)
98 qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
99
100 qe_snums_init();
101
102 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
103 QE_CR_PROTOCOL_UNSPECIFIED, 0);
104
105 /* Reclaim the MURAM memory for our use. */
106 qe_muram_init();
107
108 if (qe_sdma_init())
109 panic("sdma init failed!");
110 }
111
qe_issue_cmd(u32 cmd,u32 device,u8 mcn_protocol,u32 cmd_input)112 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
113 {
114 unsigned long flags;
115 u8 mcn_shift = 0, dev_shift = 0;
116 u32 ret;
117
118 spin_lock_irqsave(&qe_lock, flags);
119 if (cmd == QE_RESET) {
120 out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
121 } else {
122 if (cmd == QE_ASSIGN_PAGE) {
123 /* Here device is the SNUM, not sub-block */
124 dev_shift = QE_CR_SNUM_SHIFT;
125 } else if (cmd == QE_ASSIGN_RISC) {
126 /* Here device is the SNUM, and mcnProtocol is
127 * e_QeCmdRiscAssignment value */
128 dev_shift = QE_CR_SNUM_SHIFT;
129 mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
130 } else {
131 if (device == QE_CR_SUBBLOCK_USB)
132 mcn_shift = QE_CR_MCN_USB_SHIFT;
133 else
134 mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
135 }
136
137 out_be32(&qe_immr->cp.cecdr, cmd_input);
138 out_be32(&qe_immr->cp.cecr,
139 (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
140 mcn_protocol << mcn_shift));
141 }
142
143 /* wait for the QE_CR_FLG to clear */
144 ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
145 100, 0);
146 /* On timeout (e.g. failure), the expression will be false (ret == 0),
147 otherwise it will be true (ret == 1). */
148 spin_unlock_irqrestore(&qe_lock, flags);
149
150 return ret == 1;
151 }
152 EXPORT_SYMBOL(qe_issue_cmd);
153
154 /* Set a baud rate generator. This needs lots of work. There are
155 * 16 BRGs, which can be connected to the QE channels or output
156 * as clocks. The BRGs are in two different block of internal
157 * memory mapped space.
158 * The BRG clock is the QE clock divided by 2.
159 * It was set up long ago during the initial boot phase and is
160 * is given to us.
161 * Baud rate clocks are zero-based in the driver code (as that maps
162 * to port numbers). Documentation uses 1-based numbering.
163 */
164 static unsigned int brg_clk = 0;
165
166 #define CLK_GRAN (1000)
167 #define CLK_GRAN_LIMIT (5)
168
qe_get_brg_clk(void)169 unsigned int qe_get_brg_clk(void)
170 {
171 struct device_node *qe;
172 int size;
173 const u32 *prop;
174 unsigned int mod;
175
176 if (brg_clk)
177 return brg_clk;
178
179 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
180 if (!qe) {
181 qe = of_find_node_by_type(NULL, "qe");
182 if (!qe)
183 return brg_clk;
184 }
185
186 prop = of_get_property(qe, "brg-frequency", &size);
187 if (prop && size == sizeof(*prop))
188 brg_clk = *prop;
189
190 of_node_put(qe);
191
192 /* round this if near to a multiple of CLK_GRAN */
193 mod = brg_clk % CLK_GRAN;
194 if (mod) {
195 if (mod < CLK_GRAN_LIMIT)
196 brg_clk -= mod;
197 else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
198 brg_clk += CLK_GRAN - mod;
199 }
200
201 return brg_clk;
202 }
203 EXPORT_SYMBOL(qe_get_brg_clk);
204
205 /* Program the BRG to the given sampling rate and multiplier
206 *
207 * @brg: the BRG, QE_BRG1 - QE_BRG16
208 * @rate: the desired sampling rate
209 * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
210 * GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
211 * then 'multiplier' should be 8.
212 */
qe_setbrg(enum qe_clock brg,unsigned int rate,unsigned int multiplier)213 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
214 {
215 u32 divisor, tempval;
216 u32 div16 = 0;
217
218 if ((brg < QE_BRG1) || (brg > QE_BRG16))
219 return -EINVAL;
220
221 divisor = qe_get_brg_clk() / (rate * multiplier);
222
223 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
224 div16 = QE_BRGC_DIV16;
225 divisor /= 16;
226 }
227
228 /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
229 that the BRG divisor must be even if you're not using divide-by-16
230 mode. */
231 if (!div16 && (divisor & 1) && (divisor > 3))
232 divisor++;
233
234 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
235 QE_BRGC_ENABLE | div16;
236
237 out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
238
239 return 0;
240 }
241 EXPORT_SYMBOL(qe_setbrg);
242
243 /* Convert a string to a QE clock source enum
244 *
245 * This function takes a string, typically from a property in the device
246 * tree, and returns the corresponding "enum qe_clock" value.
247 */
qe_clock_source(const char * source)248 enum qe_clock qe_clock_source(const char *source)
249 {
250 unsigned int i;
251
252 if (strcasecmp(source, "none") == 0)
253 return QE_CLK_NONE;
254
255 if (strcmp(source, "tsync_pin") == 0)
256 return QE_TSYNC_PIN;
257
258 if (strcmp(source, "rsync_pin") == 0)
259 return QE_RSYNC_PIN;
260
261 if (strncasecmp(source, "brg", 3) == 0) {
262 i = simple_strtoul(source + 3, NULL, 10);
263 if ((i >= 1) && (i <= 16))
264 return (QE_BRG1 - 1) + i;
265 else
266 return QE_CLK_DUMMY;
267 }
268
269 if (strncasecmp(source, "clk", 3) == 0) {
270 i = simple_strtoul(source + 3, NULL, 10);
271 if ((i >= 1) && (i <= 24))
272 return (QE_CLK1 - 1) + i;
273 else
274 return QE_CLK_DUMMY;
275 }
276
277 return QE_CLK_DUMMY;
278 }
279 EXPORT_SYMBOL(qe_clock_source);
280
281 /* Initialize SNUMs (thread serial numbers) according to
282 * QE Module Control chapter, SNUM table
283 */
qe_snums_init(void)284 static void qe_snums_init(void)
285 {
286 int i;
287 static const u8 snum_init_76[] = {
288 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
289 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
290 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
291 0xD8, 0xD9, 0xE8, 0xE9, 0x44, 0x45, 0x4C, 0x4D,
292 0x54, 0x55, 0x5C, 0x5D, 0x64, 0x65, 0x6C, 0x6D,
293 0x74, 0x75, 0x7C, 0x7D, 0x84, 0x85, 0x8C, 0x8D,
294 0x94, 0x95, 0x9C, 0x9D, 0xA4, 0xA5, 0xAC, 0xAD,
295 0xB4, 0xB5, 0xBC, 0xBD, 0xC4, 0xC5, 0xCC, 0xCD,
296 0xD4, 0xD5, 0xDC, 0xDD, 0xE4, 0xE5, 0xEC, 0xED,
297 0xF4, 0xF5, 0xFC, 0xFD,
298 };
299 static const u8 snum_init_46[] = {
300 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
301 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
302 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
303 0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
304 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
305 0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
306 };
307 static const u8 *snum_init;
308
309 qe_num_of_snum = qe_get_num_of_snums();
310
311 if (qe_num_of_snum == 76)
312 snum_init = snum_init_76;
313 else
314 snum_init = snum_init_46;
315
316 for (i = 0; i < qe_num_of_snum; i++) {
317 snums[i].num = snum_init[i];
318 snums[i].state = QE_SNUM_STATE_FREE;
319 }
320 }
321
qe_get_snum(void)322 int qe_get_snum(void)
323 {
324 unsigned long flags;
325 int snum = -EBUSY;
326 int i;
327
328 spin_lock_irqsave(&qe_lock, flags);
329 for (i = 0; i < qe_num_of_snum; i++) {
330 if (snums[i].state == QE_SNUM_STATE_FREE) {
331 snums[i].state = QE_SNUM_STATE_USED;
332 snum = snums[i].num;
333 break;
334 }
335 }
336 spin_unlock_irqrestore(&qe_lock, flags);
337
338 return snum;
339 }
340 EXPORT_SYMBOL(qe_get_snum);
341
qe_put_snum(u8 snum)342 void qe_put_snum(u8 snum)
343 {
344 int i;
345
346 for (i = 0; i < qe_num_of_snum; i++) {
347 if (snums[i].num == snum) {
348 snums[i].state = QE_SNUM_STATE_FREE;
349 break;
350 }
351 }
352 }
353 EXPORT_SYMBOL(qe_put_snum);
354
qe_sdma_init(void)355 static int qe_sdma_init(void)
356 {
357 struct sdma __iomem *sdma = &qe_immr->sdma;
358 static unsigned long sdma_buf_offset = (unsigned long)-ENOMEM;
359
360 if (!sdma)
361 return -ENODEV;
362
363 /* allocate 2 internal temporary buffers (512 bytes size each) for
364 * the SDMA */
365 if (IS_ERR_VALUE(sdma_buf_offset)) {
366 sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
367 if (IS_ERR_VALUE(sdma_buf_offset))
368 return -ENOMEM;
369 }
370
371 out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
372 out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
373 (0x1 << QE_SDMR_CEN_SHIFT)));
374
375 return 0;
376 }
377
378 /* The maximum number of RISCs we support */
379 #define MAX_QE_RISC 4
380
381 /* Firmware information stored here for qe_get_firmware_info() */
382 static struct qe_firmware_info qe_firmware_info;
383
384 /*
385 * Set to 1 if QE firmware has been uploaded, and therefore
386 * qe_firmware_info contains valid data.
387 */
388 static int qe_firmware_uploaded;
389
390 /*
391 * Upload a QE microcode
392 *
393 * This function is a worker function for qe_upload_firmware(). It does
394 * the actual uploading of the microcode.
395 */
qe_upload_microcode(const void * base,const struct qe_microcode * ucode)396 static void qe_upload_microcode(const void *base,
397 const struct qe_microcode *ucode)
398 {
399 const __be32 *code = base + be32_to_cpu(ucode->code_offset);
400 unsigned int i;
401
402 if (ucode->major || ucode->minor || ucode->revision)
403 printk(KERN_INFO "qe-firmware: "
404 "uploading microcode '%s' version %u.%u.%u\n",
405 ucode->id, ucode->major, ucode->minor, ucode->revision);
406 else
407 printk(KERN_INFO "qe-firmware: "
408 "uploading microcode '%s'\n", ucode->id);
409
410 /* Use auto-increment */
411 out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
412 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
413
414 for (i = 0; i < be32_to_cpu(ucode->count); i++)
415 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
416
417 /* Set I-RAM Ready Register */
418 out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
419 }
420
421 /*
422 * Upload a microcode to the I-RAM at a specific address.
423 *
424 * See Documentation/powerpc/qe_firmware.txt for information on QE microcode
425 * uploading.
426 *
427 * Currently, only version 1 is supported, so the 'version' field must be
428 * set to 1.
429 *
430 * The SOC model and revision are not validated, they are only displayed for
431 * informational purposes.
432 *
433 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
434 * all of the microcode structures, minus the CRC.
435 *
436 * 'length' is the size that the structure says it is, including the CRC.
437 */
qe_upload_firmware(const struct qe_firmware * firmware)438 int qe_upload_firmware(const struct qe_firmware *firmware)
439 {
440 unsigned int i;
441 unsigned int j;
442 u32 crc;
443 size_t calc_size = sizeof(struct qe_firmware);
444 size_t length;
445 const struct qe_header *hdr;
446
447 if (!firmware) {
448 printk(KERN_ERR "qe-firmware: invalid pointer\n");
449 return -EINVAL;
450 }
451
452 hdr = &firmware->header;
453 length = be32_to_cpu(hdr->length);
454
455 /* Check the magic */
456 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
457 (hdr->magic[2] != 'F')) {
458 printk(KERN_ERR "qe-firmware: not a microcode\n");
459 return -EPERM;
460 }
461
462 /* Check the version */
463 if (hdr->version != 1) {
464 printk(KERN_ERR "qe-firmware: unsupported version\n");
465 return -EPERM;
466 }
467
468 /* Validate some of the fields */
469 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
470 printk(KERN_ERR "qe-firmware: invalid data\n");
471 return -EINVAL;
472 }
473
474 /* Validate the length and check if there's a CRC */
475 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
476
477 for (i = 0; i < firmware->count; i++)
478 /*
479 * For situations where the second RISC uses the same microcode
480 * as the first, the 'code_offset' and 'count' fields will be
481 * zero, so it's okay to add those.
482 */
483 calc_size += sizeof(__be32) *
484 be32_to_cpu(firmware->microcode[i].count);
485
486 /* Validate the length */
487 if (length != calc_size + sizeof(__be32)) {
488 printk(KERN_ERR "qe-firmware: invalid length\n");
489 return -EPERM;
490 }
491
492 /* Validate the CRC */
493 crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
494 if (crc != crc32(0, firmware, calc_size)) {
495 printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
496 return -EIO;
497 }
498
499 /*
500 * If the microcode calls for it, split the I-RAM.
501 */
502 if (!firmware->split)
503 setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
504
505 if (firmware->soc.model)
506 printk(KERN_INFO
507 "qe-firmware: firmware '%s' for %u V%u.%u\n",
508 firmware->id, be16_to_cpu(firmware->soc.model),
509 firmware->soc.major, firmware->soc.minor);
510 else
511 printk(KERN_INFO "qe-firmware: firmware '%s'\n",
512 firmware->id);
513
514 /*
515 * The QE only supports one microcode per RISC, so clear out all the
516 * saved microcode information and put in the new.
517 */
518 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
519 strlcpy(qe_firmware_info.id, firmware->id, sizeof(qe_firmware_info.id));
520 qe_firmware_info.extended_modes = firmware->extended_modes;
521 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
522 sizeof(firmware->vtraps));
523
524 /* Loop through each microcode. */
525 for (i = 0; i < firmware->count; i++) {
526 const struct qe_microcode *ucode = &firmware->microcode[i];
527
528 /* Upload a microcode if it's present */
529 if (ucode->code_offset)
530 qe_upload_microcode(firmware, ucode);
531
532 /* Program the traps for this processor */
533 for (j = 0; j < 16; j++) {
534 u32 trap = be32_to_cpu(ucode->traps[j]);
535
536 if (trap)
537 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
538 }
539
540 /* Enable traps */
541 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
542 }
543
544 qe_firmware_uploaded = 1;
545
546 return 0;
547 }
548 EXPORT_SYMBOL(qe_upload_firmware);
549
550 /*
551 * Get info on the currently-loaded firmware
552 *
553 * This function also checks the device tree to see if the boot loader has
554 * uploaded a firmware already.
555 */
qe_get_firmware_info(void)556 struct qe_firmware_info *qe_get_firmware_info(void)
557 {
558 static int initialized;
559 struct property *prop;
560 struct device_node *qe;
561 struct device_node *fw = NULL;
562 const char *sprop;
563 unsigned int i;
564
565 /*
566 * If we haven't checked yet, and a driver hasn't uploaded a firmware
567 * yet, then check the device tree for information.
568 */
569 if (qe_firmware_uploaded)
570 return &qe_firmware_info;
571
572 if (initialized)
573 return NULL;
574
575 initialized = 1;
576
577 /*
578 * Newer device trees have an "fsl,qe" compatible property for the QE
579 * node, but we still need to support older device trees.
580 */
581 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
582 if (!qe) {
583 qe = of_find_node_by_type(NULL, "qe");
584 if (!qe)
585 return NULL;
586 }
587
588 /* Find the 'firmware' child node */
589 for_each_child_of_node(qe, fw) {
590 if (strcmp(fw->name, "firmware") == 0)
591 break;
592 }
593
594 of_node_put(qe);
595
596 /* Did we find the 'firmware' node? */
597 if (!fw)
598 return NULL;
599
600 qe_firmware_uploaded = 1;
601
602 /* Copy the data into qe_firmware_info*/
603 sprop = of_get_property(fw, "id", NULL);
604 if (sprop)
605 strlcpy(qe_firmware_info.id, sprop,
606 sizeof(qe_firmware_info.id));
607
608 prop = of_find_property(fw, "extended-modes", NULL);
609 if (prop && (prop->length == sizeof(u64))) {
610 const u64 *iprop = prop->value;
611
612 qe_firmware_info.extended_modes = *iprop;
613 }
614
615 prop = of_find_property(fw, "virtual-traps", NULL);
616 if (prop && (prop->length == 32)) {
617 const u32 *iprop = prop->value;
618
619 for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++)
620 qe_firmware_info.vtraps[i] = iprop[i];
621 }
622
623 of_node_put(fw);
624
625 return &qe_firmware_info;
626 }
627 EXPORT_SYMBOL(qe_get_firmware_info);
628
qe_get_num_of_risc(void)629 unsigned int qe_get_num_of_risc(void)
630 {
631 struct device_node *qe;
632 int size;
633 unsigned int num_of_risc = 0;
634 const u32 *prop;
635
636 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
637 if (!qe) {
638 /* Older devices trees did not have an "fsl,qe"
639 * compatible property, so we need to look for
640 * the QE node by name.
641 */
642 qe = of_find_node_by_type(NULL, "qe");
643 if (!qe)
644 return num_of_risc;
645 }
646
647 prop = of_get_property(qe, "fsl,qe-num-riscs", &size);
648 if (prop && size == sizeof(*prop))
649 num_of_risc = *prop;
650
651 of_node_put(qe);
652
653 return num_of_risc;
654 }
655 EXPORT_SYMBOL(qe_get_num_of_risc);
656
qe_get_num_of_snums(void)657 unsigned int qe_get_num_of_snums(void)
658 {
659 struct device_node *qe;
660 int size;
661 unsigned int num_of_snums;
662 const u32 *prop;
663
664 num_of_snums = 28; /* The default number of snum for threads is 28 */
665 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
666 if (!qe) {
667 /* Older devices trees did not have an "fsl,qe"
668 * compatible property, so we need to look for
669 * the QE node by name.
670 */
671 qe = of_find_node_by_type(NULL, "qe");
672 if (!qe)
673 return num_of_snums;
674 }
675
676 prop = of_get_property(qe, "fsl,qe-num-snums", &size);
677 if (prop && size == sizeof(*prop)) {
678 num_of_snums = *prop;
679 if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) {
680 /* No QE ever has fewer than 28 SNUMs */
681 pr_err("QE: number of snum is invalid\n");
682 of_node_put(qe);
683 return -EINVAL;
684 }
685 }
686
687 of_node_put(qe);
688
689 return num_of_snums;
690 }
691 EXPORT_SYMBOL(qe_get_num_of_snums);
692
qe_init(void)693 static int __init qe_init(void)
694 {
695 struct device_node *np;
696
697 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
698 if (!np)
699 return -ENODEV;
700 qe_reset();
701 of_node_put(np);
702 return 0;
703 }
704 subsys_initcall(qe_init);
705
706 #if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx)
qe_resume(struct platform_device * ofdev)707 static int qe_resume(struct platform_device *ofdev)
708 {
709 if (!qe_alive_during_sleep())
710 qe_reset();
711 return 0;
712 }
713
qe_probe(struct platform_device * ofdev)714 static int qe_probe(struct platform_device *ofdev)
715 {
716 return 0;
717 }
718
719 static const struct of_device_id qe_ids[] = {
720 { .compatible = "fsl,qe", },
721 { },
722 };
723
724 static struct platform_driver qe_driver = {
725 .driver = {
726 .name = "fsl-qe",
727 .of_match_table = qe_ids,
728 },
729 .probe = qe_probe,
730 .resume = qe_resume,
731 };
732
qe_drv_init(void)733 static int __init qe_drv_init(void)
734 {
735 return platform_driver_register(&qe_driver);
736 }
737 device_initcall(qe_drv_init);
738 #endif /* defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx) */
739