1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 ******************************************************************************/
15
16 #include "odm_precomp.h"
17
18 #include <phy.h>
19
20 /* AGC_TAB_1T.TXT */
21
22 static u32 array_agc_tab_1t_8188e[] = {
23 0xC78, 0xFB000001,
24 0xC78, 0xFB010001,
25 0xC78, 0xFB020001,
26 0xC78, 0xFB030001,
27 0xC78, 0xFB040001,
28 0xC78, 0xFB050001,
29 0xC78, 0xFA060001,
30 0xC78, 0xF9070001,
31 0xC78, 0xF8080001,
32 0xC78, 0xF7090001,
33 0xC78, 0xF60A0001,
34 0xC78, 0xF50B0001,
35 0xC78, 0xF40C0001,
36 0xC78, 0xF30D0001,
37 0xC78, 0xF20E0001,
38 0xC78, 0xF10F0001,
39 0xC78, 0xF0100001,
40 0xC78, 0xEF110001,
41 0xC78, 0xEE120001,
42 0xC78, 0xED130001,
43 0xC78, 0xEC140001,
44 0xC78, 0xEB150001,
45 0xC78, 0xEA160001,
46 0xC78, 0xE9170001,
47 0xC78, 0xE8180001,
48 0xC78, 0xE7190001,
49 0xC78, 0xE61A0001,
50 0xC78, 0xE51B0001,
51 0xC78, 0xE41C0001,
52 0xC78, 0xE31D0001,
53 0xC78, 0xE21E0001,
54 0xC78, 0xE11F0001,
55 0xC78, 0x8A200001,
56 0xC78, 0x89210001,
57 0xC78, 0x88220001,
58 0xC78, 0x87230001,
59 0xC78, 0x86240001,
60 0xC78, 0x85250001,
61 0xC78, 0x84260001,
62 0xC78, 0x83270001,
63 0xC78, 0x82280001,
64 0xC78, 0x6B290001,
65 0xC78, 0x6A2A0001,
66 0xC78, 0x692B0001,
67 0xC78, 0x682C0001,
68 0xC78, 0x672D0001,
69 0xC78, 0x662E0001,
70 0xC78, 0x652F0001,
71 0xC78, 0x64300001,
72 0xC78, 0x63310001,
73 0xC78, 0x62320001,
74 0xC78, 0x61330001,
75 0xC78, 0x46340001,
76 0xC78, 0x45350001,
77 0xC78, 0x44360001,
78 0xC78, 0x43370001,
79 0xC78, 0x42380001,
80 0xC78, 0x41390001,
81 0xC78, 0x403A0001,
82 0xC78, 0x403B0001,
83 0xC78, 0x403C0001,
84 0xC78, 0x403D0001,
85 0xC78, 0x403E0001,
86 0xC78, 0x403F0001,
87 0xC78, 0xFB400001,
88 0xC78, 0xFB410001,
89 0xC78, 0xFB420001,
90 0xC78, 0xFB430001,
91 0xC78, 0xFB440001,
92 0xC78, 0xFB450001,
93 0xC78, 0xFB460001,
94 0xC78, 0xFB470001,
95 0xC78, 0xFB480001,
96 0xC78, 0xFA490001,
97 0xC78, 0xF94A0001,
98 0xC78, 0xF84B0001,
99 0xC78, 0xF74C0001,
100 0xC78, 0xF64D0001,
101 0xC78, 0xF54E0001,
102 0xC78, 0xF44F0001,
103 0xC78, 0xF3500001,
104 0xC78, 0xF2510001,
105 0xC78, 0xF1520001,
106 0xC78, 0xF0530001,
107 0xC78, 0xEF540001,
108 0xC78, 0xEE550001,
109 0xC78, 0xED560001,
110 0xC78, 0xEC570001,
111 0xC78, 0xEB580001,
112 0xC78, 0xEA590001,
113 0xC78, 0xE95A0001,
114 0xC78, 0xE85B0001,
115 0xC78, 0xE75C0001,
116 0xC78, 0xE65D0001,
117 0xC78, 0xE55E0001,
118 0xC78, 0xE45F0001,
119 0xC78, 0xE3600001,
120 0xC78, 0xE2610001,
121 0xC78, 0xC3620001,
122 0xC78, 0xC2630001,
123 0xC78, 0xC1640001,
124 0xC78, 0x8B650001,
125 0xC78, 0x8A660001,
126 0xC78, 0x89670001,
127 0xC78, 0x88680001,
128 0xC78, 0x87690001,
129 0xC78, 0x866A0001,
130 0xC78, 0x856B0001,
131 0xC78, 0x846C0001,
132 0xC78, 0x676D0001,
133 0xC78, 0x666E0001,
134 0xC78, 0x656F0001,
135 0xC78, 0x64700001,
136 0xC78, 0x63710001,
137 0xC78, 0x62720001,
138 0xC78, 0x61730001,
139 0xC78, 0x60740001,
140 0xC78, 0x46750001,
141 0xC78, 0x45760001,
142 0xC78, 0x44770001,
143 0xC78, 0x43780001,
144 0xC78, 0x42790001,
145 0xC78, 0x417A0001,
146 0xC78, 0x407B0001,
147 0xC78, 0x407C0001,
148 0xC78, 0x407D0001,
149 0xC78, 0x407E0001,
150 0xC78, 0x407F0001,
151 };
152
set_baseband_agc_config(struct adapter * adapt)153 static bool set_baseband_agc_config(struct adapter *adapt)
154 {
155 u32 i;
156 const u32 arraylen = ARRAY_SIZE(array_agc_tab_1t_8188e);
157 u32 *array = array_agc_tab_1t_8188e;
158
159 for (i = 0; i < arraylen; i += 2) {
160 u32 v1 = array[i];
161 u32 v2 = array[i + 1];
162
163 if (v1 < 0xCDCDCDCD) {
164 phy_set_bb_reg(adapt, v1, bMaskDWord, v2);
165 udelay(1);
166 }
167 }
168 return true;
169 }
170
171 /* PHY_REG_1T.TXT */
172
173 static u32 array_phy_reg_1t_8188e[] = {
174 0x800, 0x80040000,
175 0x804, 0x00000003,
176 0x808, 0x0000FC00,
177 0x80C, 0x0000000A,
178 0x810, 0x10001331,
179 0x814, 0x020C3D10,
180 0x818, 0x02200385,
181 0x81C, 0x00000000,
182 0x820, 0x01000100,
183 0x824, 0x00390204,
184 0x828, 0x00000000,
185 0x82C, 0x00000000,
186 0x830, 0x00000000,
187 0x834, 0x00000000,
188 0x838, 0x00000000,
189 0x83C, 0x00000000,
190 0x840, 0x00010000,
191 0x844, 0x00000000,
192 0x848, 0x00000000,
193 0x84C, 0x00000000,
194 0x850, 0x00000000,
195 0x854, 0x00000000,
196 0x858, 0x569A11A9,
197 0x85C, 0x01000014,
198 0x860, 0x66F60110,
199 0x864, 0x061F0649,
200 0x868, 0x00000000,
201 0x86C, 0x27272700,
202 0x870, 0x07000760,
203 0x874, 0x25004000,
204 0x878, 0x00000808,
205 0x87C, 0x00000000,
206 0x880, 0xB0000C1C,
207 0x884, 0x00000001,
208 0x888, 0x00000000,
209 0x88C, 0xCCC000C0,
210 0x890, 0x00000800,
211 0x894, 0xFFFFFFFE,
212 0x898, 0x40302010,
213 0x89C, 0x00706050,
214 0x900, 0x00000000,
215 0x904, 0x00000023,
216 0x908, 0x00000000,
217 0x90C, 0x81121111,
218 0x910, 0x00000002,
219 0x914, 0x00000201,
220 0xA00, 0x00D047C8,
221 0xA04, 0x80FF000C,
222 0xA08, 0x8C838300,
223 0xA0C, 0x2E7F120F,
224 0xA10, 0x9500BB78,
225 0xA14, 0x1114D028,
226 0xA18, 0x00881117,
227 0xA1C, 0x89140F00,
228 0xA20, 0x1A1B0000,
229 0xA24, 0x090E1317,
230 0xA28, 0x00000204,
231 0xA2C, 0x00D30000,
232 0xA70, 0x101FBF00,
233 0xA74, 0x00000007,
234 0xA78, 0x00000900,
235 0xA7C, 0x225B0606,
236 0xA80, 0x218075B1,
237 0xB2C, 0x80000000,
238 0xC00, 0x48071D40,
239 0xC04, 0x03A05611,
240 0xC08, 0x000000E4,
241 0xC0C, 0x6C6C6C6C,
242 0xC10, 0x08800000,
243 0xC14, 0x40000100,
244 0xC18, 0x08800000,
245 0xC1C, 0x40000100,
246 0xC20, 0x00000000,
247 0xC24, 0x00000000,
248 0xC28, 0x00000000,
249 0xC2C, 0x00000000,
250 0xC30, 0x69E9AC47,
251 0xC34, 0x469652AF,
252 0xC38, 0x49795994,
253 0xC3C, 0x0A97971C,
254 0xC40, 0x1F7C403F,
255 0xC44, 0x000100B7,
256 0xC48, 0xEC020107,
257 0xC4C, 0x007F037F,
258 0xC50, 0x69553420,
259 0xC54, 0x43BC0094,
260 0xC58, 0x00013169,
261 0xC5C, 0x00250492,
262 0xC60, 0x00000000,
263 0xC64, 0x7112848B,
264 0xC68, 0x47C00BFF,
265 0xC6C, 0x00000036,
266 0xC70, 0x2C7F000D,
267 0xC74, 0x020610DB,
268 0xC78, 0x0000001F,
269 0xC7C, 0x00B91612,
270 0xC80, 0x390000E4,
271 0xC84, 0x20F60000,
272 0xC88, 0x40000100,
273 0xC8C, 0x20200000,
274 0xC90, 0x00091521,
275 0xC94, 0x00000000,
276 0xC98, 0x00121820,
277 0xC9C, 0x00007F7F,
278 0xCA0, 0x00000000,
279 0xCA4, 0x000300A0,
280 0xCA8, 0x00000000,
281 0xCAC, 0x00000000,
282 0xCB0, 0x00000000,
283 0xCB4, 0x00000000,
284 0xCB8, 0x00000000,
285 0xCBC, 0x28000000,
286 0xCC0, 0x00000000,
287 0xCC4, 0x00000000,
288 0xCC8, 0x00000000,
289 0xCCC, 0x00000000,
290 0xCD0, 0x00000000,
291 0xCD4, 0x00000000,
292 0xCD8, 0x64B22427,
293 0xCDC, 0x00766932,
294 0xCE0, 0x00222222,
295 0xCE4, 0x00000000,
296 0xCE8, 0x37644302,
297 0xCEC, 0x2F97D40C,
298 0xD00, 0x00000740,
299 0xD04, 0x00020401,
300 0xD08, 0x0000907F,
301 0xD0C, 0x20010201,
302 0xD10, 0xA0633333,
303 0xD14, 0x3333BC43,
304 0xD18, 0x7A8F5B6F,
305 0xD2C, 0xCC979975,
306 0xD30, 0x00000000,
307 0xD34, 0x80608000,
308 0xD38, 0x00000000,
309 0xD3C, 0x00127353,
310 0xD40, 0x00000000,
311 0xD44, 0x00000000,
312 0xD48, 0x00000000,
313 0xD4C, 0x00000000,
314 0xD50, 0x6437140A,
315 0xD54, 0x00000000,
316 0xD58, 0x00000282,
317 0xD5C, 0x30032064,
318 0xD60, 0x4653DE68,
319 0xD64, 0x04518A3C,
320 0xD68, 0x00002101,
321 0xD6C, 0x2A201C16,
322 0xD70, 0x1812362E,
323 0xD74, 0x322C2220,
324 0xD78, 0x000E3C24,
325 0xE00, 0x2D2D2D2D,
326 0xE04, 0x2D2D2D2D,
327 0xE08, 0x0390272D,
328 0xE10, 0x2D2D2D2D,
329 0xE14, 0x2D2D2D2D,
330 0xE18, 0x2D2D2D2D,
331 0xE1C, 0x2D2D2D2D,
332 0xE28, 0x00000000,
333 0xE30, 0x1000DC1F,
334 0xE34, 0x10008C1F,
335 0xE38, 0x02140102,
336 0xE3C, 0x681604C2,
337 0xE40, 0x01007C00,
338 0xE44, 0x01004800,
339 0xE48, 0xFB000000,
340 0xE4C, 0x000028D1,
341 0xE50, 0x1000DC1F,
342 0xE54, 0x10008C1F,
343 0xE58, 0x02140102,
344 0xE5C, 0x28160D05,
345 0xE60, 0x00000008,
346 0xE68, 0x001B25A4,
347 0xE6C, 0x00C00014,
348 0xE70, 0x00C00014,
349 0xE74, 0x01000014,
350 0xE78, 0x01000014,
351 0xE7C, 0x01000014,
352 0xE80, 0x01000014,
353 0xE84, 0x00C00014,
354 0xE88, 0x01000014,
355 0xE8C, 0x00C00014,
356 0xED0, 0x00C00014,
357 0xED4, 0x00C00014,
358 0xED8, 0x00C00014,
359 0xEDC, 0x00000014,
360 0xEE0, 0x00000014,
361 0xEEC, 0x01C00014,
362 0xF14, 0x00000003,
363 0xF4C, 0x00000000,
364 0xF00, 0x00000300,
365 };
366
rtl_bb_delay(struct adapter * adapt,u32 addr,u32 data)367 static void rtl_bb_delay(struct adapter *adapt, u32 addr, u32 data)
368 {
369 if (addr == 0xfe) {
370 msleep(50);
371 } else if (addr == 0xfd) {
372 mdelay(5);
373 } else if (addr == 0xfc) {
374 mdelay(1);
375 } else if (addr == 0xfb) {
376 udelay(50);
377 } else if (addr == 0xfa) {
378 udelay(5);
379 } else if (addr == 0xf9) {
380 udelay(1);
381 } else {
382 phy_set_bb_reg(adapt, addr, bMaskDWord, data);
383 /* Add 1us delay between BB/RF register setting. */
384 udelay(1);
385 }
386 }
387
set_baseband_phy_config(struct adapter * adapt)388 static bool set_baseband_phy_config(struct adapter *adapt)
389 {
390 u32 i;
391 const u32 arraylen = ARRAY_SIZE(array_phy_reg_1t_8188e);
392 u32 *array = array_phy_reg_1t_8188e;
393
394 for (i = 0; i < arraylen; i += 2) {
395 u32 v1 = array[i];
396 u32 v2 = array[i + 1];
397
398 if (v1 < 0xCDCDCDCD)
399 rtl_bb_delay(adapt, v1, v2);
400 }
401 return true;
402 }
403
404 /* PHY_REG_PG.TXT */
405
406 static u32 array_phy_reg_pg_8188e[] = {
407 0xE00, 0xFFFFFFFF, 0x06070809,
408 0xE04, 0xFFFFFFFF, 0x02020405,
409 0xE08, 0x0000FF00, 0x00000006,
410 0x86C, 0xFFFFFF00, 0x00020400,
411 0xE10, 0xFFFFFFFF, 0x08090A0B,
412 0xE14, 0xFFFFFFFF, 0x01030607,
413 0xE18, 0xFFFFFFFF, 0x08090A0B,
414 0xE1C, 0xFFFFFFFF, 0x01030607,
415 0xE00, 0xFFFFFFFF, 0x00000000,
416 0xE04, 0xFFFFFFFF, 0x00000000,
417 0xE08, 0x0000FF00, 0x00000000,
418 0x86C, 0xFFFFFF00, 0x00000000,
419 0xE10, 0xFFFFFFFF, 0x00000000,
420 0xE14, 0xFFFFFFFF, 0x00000000,
421 0xE18, 0xFFFFFFFF, 0x00000000,
422 0xE1C, 0xFFFFFFFF, 0x00000000,
423 0xE00, 0xFFFFFFFF, 0x02020202,
424 0xE04, 0xFFFFFFFF, 0x00020202,
425 0xE08, 0x0000FF00, 0x00000000,
426 0x86C, 0xFFFFFF00, 0x00000000,
427 0xE10, 0xFFFFFFFF, 0x04040404,
428 0xE14, 0xFFFFFFFF, 0x00020404,
429 0xE18, 0xFFFFFFFF, 0x00000000,
430 0xE1C, 0xFFFFFFFF, 0x00000000,
431 0xE00, 0xFFFFFFFF, 0x02020202,
432 0xE04, 0xFFFFFFFF, 0x00020202,
433 0xE08, 0x0000FF00, 0x00000000,
434 0x86C, 0xFFFFFF00, 0x00000000,
435 0xE10, 0xFFFFFFFF, 0x04040404,
436 0xE14, 0xFFFFFFFF, 0x00020404,
437 0xE18, 0xFFFFFFFF, 0x00000000,
438 0xE1C, 0xFFFFFFFF, 0x00000000,
439 0xE00, 0xFFFFFFFF, 0x00000000,
440 0xE04, 0xFFFFFFFF, 0x00000000,
441 0xE08, 0x0000FF00, 0x00000000,
442 0x86C, 0xFFFFFF00, 0x00000000,
443 0xE10, 0xFFFFFFFF, 0x00000000,
444 0xE14, 0xFFFFFFFF, 0x00000000,
445 0xE18, 0xFFFFFFFF, 0x00000000,
446 0xE1C, 0xFFFFFFFF, 0x00000000,
447 0xE00, 0xFFFFFFFF, 0x02020202,
448 0xE04, 0xFFFFFFFF, 0x00020202,
449 0xE08, 0x0000FF00, 0x00000000,
450 0x86C, 0xFFFFFF00, 0x00000000,
451 0xE10, 0xFFFFFFFF, 0x04040404,
452 0xE14, 0xFFFFFFFF, 0x00020404,
453 0xE18, 0xFFFFFFFF, 0x00000000,
454 0xE1C, 0xFFFFFFFF, 0x00000000,
455 0xE00, 0xFFFFFFFF, 0x00000000,
456 0xE04, 0xFFFFFFFF, 0x00000000,
457 0xE08, 0x0000FF00, 0x00000000,
458 0x86C, 0xFFFFFF00, 0x00000000,
459 0xE10, 0xFFFFFFFF, 0x00000000,
460 0xE14, 0xFFFFFFFF, 0x00000000,
461 0xE18, 0xFFFFFFFF, 0x00000000,
462 0xE1C, 0xFFFFFFFF, 0x00000000,
463 0xE00, 0xFFFFFFFF, 0x00000000,
464 0xE04, 0xFFFFFFFF, 0x00000000,
465 0xE08, 0x0000FF00, 0x00000000,
466 0x86C, 0xFFFFFF00, 0x00000000,
467 0xE10, 0xFFFFFFFF, 0x00000000,
468 0xE14, 0xFFFFFFFF, 0x00000000,
469 0xE18, 0xFFFFFFFF, 0x00000000,
470 0xE1C, 0xFFFFFFFF, 0x00000000,
471 0xE00, 0xFFFFFFFF, 0x00000000,
472 0xE04, 0xFFFFFFFF, 0x00000000,
473 0xE08, 0x0000FF00, 0x00000000,
474 0x86C, 0xFFFFFF00, 0x00000000,
475 0xE10, 0xFFFFFFFF, 0x00000000,
476 0xE14, 0xFFFFFFFF, 0x00000000,
477 0xE18, 0xFFFFFFFF, 0x00000000,
478 0xE1C, 0xFFFFFFFF, 0x00000000,
479 0xE00, 0xFFFFFFFF, 0x00000000,
480 0xE04, 0xFFFFFFFF, 0x00000000,
481 0xE08, 0x0000FF00, 0x00000000,
482 0x86C, 0xFFFFFF00, 0x00000000,
483 0xE10, 0xFFFFFFFF, 0x00000000,
484 0xE14, 0xFFFFFFFF, 0x00000000,
485 0xE18, 0xFFFFFFFF, 0x00000000,
486 0xE1C, 0xFFFFFFFF, 0x00000000,
487 0xE00, 0xFFFFFFFF, 0x00000000,
488 0xE04, 0xFFFFFFFF, 0x00000000,
489 0xE08, 0x0000FF00, 0x00000000,
490 0x86C, 0xFFFFFF00, 0x00000000,
491 0xE10, 0xFFFFFFFF, 0x00000000,
492 0xE14, 0xFFFFFFFF, 0x00000000,
493 0xE18, 0xFFFFFFFF, 0x00000000,
494 0xE1C, 0xFFFFFFFF, 0x00000000,
495
496 };
497
store_pwrindex_offset(struct adapter * adapter,u32 regaddr,u32 bitmask,u32 data)498 static void store_pwrindex_offset(struct adapter *adapter,
499 u32 regaddr, u32 bitmask, u32 data)
500 {
501 struct hal_data_8188e *hal_data = adapter->HalData;
502 u32 * const power_level_offset =
503 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt];
504
505 if (regaddr == rTxAGC_A_Rate18_06)
506 power_level_offset[0] = data;
507 if (regaddr == rTxAGC_A_Rate54_24)
508 power_level_offset[1] = data;
509 if (regaddr == rTxAGC_A_CCK1_Mcs32)
510 power_level_offset[6] = data;
511 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
512 power_level_offset[7] = data;
513 if (regaddr == rTxAGC_A_Mcs03_Mcs00)
514 power_level_offset[2] = data;
515 if (regaddr == rTxAGC_A_Mcs07_Mcs04)
516 power_level_offset[3] = data;
517 if (regaddr == rTxAGC_A_Mcs11_Mcs08)
518 power_level_offset[4] = data;
519 if (regaddr == rTxAGC_A_Mcs15_Mcs12) {
520 power_level_offset[5] = data;
521 hal_data->pwrGroupCnt++;
522 }
523 if (regaddr == rTxAGC_B_Rate18_06)
524 power_level_offset[8] = data;
525 if (regaddr == rTxAGC_B_Rate54_24)
526 power_level_offset[9] = data;
527 if (regaddr == rTxAGC_B_CCK1_55_Mcs32)
528 power_level_offset[14] = data;
529 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
530 power_level_offset[15] = data;
531 if (regaddr == rTxAGC_B_Mcs03_Mcs00)
532 power_level_offset[10] = data;
533 if (regaddr == rTxAGC_B_Mcs07_Mcs04)
534 power_level_offset[11] = data;
535 if (regaddr == rTxAGC_B_Mcs11_Mcs08)
536 power_level_offset[12] = data;
537 if (regaddr == rTxAGC_B_Mcs15_Mcs12) {
538 power_level_offset[13] = data;
539 }
540 }
541
rtl_addr_delay(struct adapter * adapt,u32 addr,u32 bit_mask,u32 data)542 static void rtl_addr_delay(struct adapter *adapt,
543 u32 addr, u32 bit_mask, u32 data)
544 {
545 switch (addr) {
546 case 0xfe:
547 msleep(50);
548 break;
549 case 0xfd:
550 mdelay(5);
551 break;
552 case 0xfc:
553 mdelay(1);
554 break;
555 case 0xfb:
556 udelay(50);
557 break;
558 case 0xfa:
559 udelay(5);
560 break;
561 case 0xf9:
562 udelay(1);
563 break;
564 default:
565 store_pwrindex_offset(adapt, addr, bit_mask, data);
566 }
567 }
568
config_bb_with_pgheader(struct adapter * adapt)569 static bool config_bb_with_pgheader(struct adapter *adapt)
570 {
571 u32 i;
572 const u32 arraylen = ARRAY_SIZE(array_phy_reg_pg_8188e);
573 u32 *array = array_phy_reg_pg_8188e;
574
575 for (i = 0; i < arraylen; i += 3) {
576 u32 v1 = array[i];
577 u32 v2 = array[i + 1];
578 u32 v3 = array[i + 2];
579
580 if (v1 < 0xCDCDCDCD)
581 rtl_addr_delay(adapt, v1, v2, v3);
582 }
583 return true;
584 }
585
rtl88e_phy_init_bb_rf_register_definition(struct adapter * adapter)586 static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *adapter)
587 {
588 struct bb_reg_def *reg[4];
589
590 reg[RF_PATH_A] = &adapter->HalData->PHYRegDef[RF_PATH_A];
591 reg[RF_PATH_B] = &adapter->HalData->PHYRegDef[RF_PATH_B];
592
593 reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
594 reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
595
596 reg[RF_PATH_A]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
597 reg[RF_PATH_B]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
598
599 reg[RF_PATH_A]->rfintfo = rFPGA0_XA_RFInterfaceOE;
600 reg[RF_PATH_B]->rfintfo = rFPGA0_XB_RFInterfaceOE;
601
602 reg[RF_PATH_A]->rfintfe = rFPGA0_XA_RFInterfaceOE;
603 reg[RF_PATH_B]->rfintfe = rFPGA0_XB_RFInterfaceOE;
604
605 reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter;
606 reg[RF_PATH_B]->rf3wireOffset = rFPGA0_XB_LSSIParameter;
607
608 reg[RF_PATH_A]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
609 reg[RF_PATH_B]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
610
611 reg[RF_PATH_A]->rfTxGainStage = rFPGA0_TxGainStage;
612 reg[RF_PATH_B]->rfTxGainStage = rFPGA0_TxGainStage;
613
614 reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
615 reg[RF_PATH_B]->rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
616
617 reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
618 reg[RF_PATH_B]->rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
619
620 reg[RF_PATH_A]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
621 reg[RF_PATH_B]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
622
623 reg[RF_PATH_A]->rfAGCControl1 = rOFDM0_XAAGCCore1;
624 reg[RF_PATH_B]->rfAGCControl1 = rOFDM0_XBAGCCore1;
625
626 reg[RF_PATH_A]->rfAGCControl2 = rOFDM0_XAAGCCore2;
627 reg[RF_PATH_B]->rfAGCControl2 = rOFDM0_XBAGCCore2;
628
629 reg[RF_PATH_A]->rfRxIQImbalance = rOFDM0_XARxIQImbalance;
630 reg[RF_PATH_B]->rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
631
632 reg[RF_PATH_A]->rfRxAFE = rOFDM0_XARxAFE;
633 reg[RF_PATH_B]->rfRxAFE = rOFDM0_XBRxAFE;
634
635 reg[RF_PATH_A]->rfTxIQImbalance = rOFDM0_XATxIQImbalance;
636 reg[RF_PATH_B]->rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
637
638 reg[RF_PATH_A]->rfTxAFE = rOFDM0_XATxAFE;
639 reg[RF_PATH_B]->rfTxAFE = rOFDM0_XBTxAFE;
640
641 reg[RF_PATH_A]->rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
642 reg[RF_PATH_B]->rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
643
644 reg[RF_PATH_A]->rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
645 reg[RF_PATH_B]->rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
646 }
647
config_parafile(struct adapter * adapt)648 static bool config_parafile(struct adapter *adapt)
649 {
650 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
651
652 set_baseband_phy_config(adapt);
653
654 /* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
655 if (!eeprom->bautoload_fail_flag) {
656 adapt->HalData->pwrGroupCnt = 0;
657 config_bb_with_pgheader(adapt);
658 }
659 set_baseband_agc_config(adapt);
660 return true;
661 }
662
rtl88eu_phy_bb_config(struct adapter * adapt)663 bool rtl88eu_phy_bb_config(struct adapter *adapt)
664 {
665 int rtstatus = true;
666 u32 regval;
667 u8 crystal_cap;
668
669 rtl88e_phy_init_bb_rf_register_definition(adapt);
670
671 /* Enable BB and RF */
672 regval = usb_read16(adapt, REG_SYS_FUNC_EN);
673 usb_write16(adapt, REG_SYS_FUNC_EN,
674 (u16)(regval | BIT(13) | BIT(0) | BIT(1)));
675
676 usb_write8(adapt, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
677
678 usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA |
679 FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
680
681 /* Config BB and AGC */
682 rtstatus = config_parafile(adapt);
683
684 /* write 0x24[16:11] = 0x24[22:17] = crystal_cap */
685 crystal_cap = adapt->HalData->CrystalCap & 0x3F;
686 phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800,
687 (crystal_cap | (crystal_cap << 6)));
688
689 return rtstatus;
690 }
691