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1 /*
2  * Samsung S5P Multi Format Codec v 5.1
3  *
4  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5  * Kamil Debski, <k.debski@samsung.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  */
12 
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
24 #include <linux/of.h>
25 #include <linux/of_reserved_mem.h>
26 #include <media/videobuf2-v4l2.h>
27 #include "s5p_mfc_common.h"
28 #include "s5p_mfc_ctrl.h"
29 #include "s5p_mfc_debug.h"
30 #include "s5p_mfc_dec.h"
31 #include "s5p_mfc_enc.h"
32 #include "s5p_mfc_intr.h"
33 #include "s5p_mfc_iommu.h"
34 #include "s5p_mfc_opr.h"
35 #include "s5p_mfc_cmd.h"
36 #include "s5p_mfc_pm.h"
37 
38 #define S5P_MFC_DEC_NAME	"s5p-mfc-dec"
39 #define S5P_MFC_ENC_NAME	"s5p-mfc-enc"
40 
41 int mfc_debug_level;
42 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
43 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
44 
45 /* Helper functions for interrupt processing */
46 
47 /* Remove from hw execution round robin */
clear_work_bit(struct s5p_mfc_ctx * ctx)48 void clear_work_bit(struct s5p_mfc_ctx *ctx)
49 {
50 	struct s5p_mfc_dev *dev = ctx->dev;
51 
52 	spin_lock(&dev->condlock);
53 	__clear_bit(ctx->num, &dev->ctx_work_bits);
54 	spin_unlock(&dev->condlock);
55 }
56 
57 /* Add to hw execution round robin */
set_work_bit(struct s5p_mfc_ctx * ctx)58 void set_work_bit(struct s5p_mfc_ctx *ctx)
59 {
60 	struct s5p_mfc_dev *dev = ctx->dev;
61 
62 	spin_lock(&dev->condlock);
63 	__set_bit(ctx->num, &dev->ctx_work_bits);
64 	spin_unlock(&dev->condlock);
65 }
66 
67 /* Remove from hw execution round robin */
clear_work_bit_irqsave(struct s5p_mfc_ctx * ctx)68 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
69 {
70 	struct s5p_mfc_dev *dev = ctx->dev;
71 	unsigned long flags;
72 
73 	spin_lock_irqsave(&dev->condlock, flags);
74 	__clear_bit(ctx->num, &dev->ctx_work_bits);
75 	spin_unlock_irqrestore(&dev->condlock, flags);
76 }
77 
78 /* Add to hw execution round robin */
set_work_bit_irqsave(struct s5p_mfc_ctx * ctx)79 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
80 {
81 	struct s5p_mfc_dev *dev = ctx->dev;
82 	unsigned long flags;
83 
84 	spin_lock_irqsave(&dev->condlock, flags);
85 	__set_bit(ctx->num, &dev->ctx_work_bits);
86 	spin_unlock_irqrestore(&dev->condlock, flags);
87 }
88 
s5p_mfc_get_new_ctx(struct s5p_mfc_dev * dev)89 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
90 {
91 	unsigned long flags;
92 	int ctx;
93 
94 	spin_lock_irqsave(&dev->condlock, flags);
95 	ctx = dev->curr_ctx;
96 	do {
97 		ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
98 		if (ctx == dev->curr_ctx) {
99 			if (!test_bit(ctx, &dev->ctx_work_bits))
100 				ctx = -EAGAIN;
101 			break;
102 		}
103 	} while (!test_bit(ctx, &dev->ctx_work_bits));
104 	spin_unlock_irqrestore(&dev->condlock, flags);
105 
106 	return ctx;
107 }
108 
109 /* Wake up context wait_queue */
wake_up_ctx(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)110 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
111 			unsigned int err)
112 {
113 	ctx->int_cond = 1;
114 	ctx->int_type = reason;
115 	ctx->int_err = err;
116 	wake_up(&ctx->queue);
117 }
118 
119 /* Wake up device wait_queue */
wake_up_dev(struct s5p_mfc_dev * dev,unsigned int reason,unsigned int err)120 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
121 			unsigned int err)
122 {
123 	dev->int_cond = 1;
124 	dev->int_type = reason;
125 	dev->int_err = err;
126 	wake_up(&dev->queue);
127 }
128 
s5p_mfc_cleanup_queue(struct list_head * lh,struct vb2_queue * vq)129 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
130 {
131 	struct s5p_mfc_buf *b;
132 	int i;
133 
134 	while (!list_empty(lh)) {
135 		b = list_entry(lh->next, struct s5p_mfc_buf, list);
136 		for (i = 0; i < b->b->vb2_buf.num_planes; i++)
137 			vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
138 		vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
139 		list_del(&b->list);
140 	}
141 }
142 
s5p_mfc_watchdog(unsigned long arg)143 static void s5p_mfc_watchdog(unsigned long arg)
144 {
145 	struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
146 
147 	if (test_bit(0, &dev->hw_lock))
148 		atomic_inc(&dev->watchdog_cnt);
149 	if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
150 		/* This means that hw is busy and no interrupts were
151 		 * generated by hw for the Nth time of running this
152 		 * watchdog timer. This usually means a serious hw
153 		 * error. Now it is time to kill all instances and
154 		 * reset the MFC. */
155 		mfc_err("Time out during waiting for HW\n");
156 		schedule_work(&dev->watchdog_work);
157 	}
158 	dev->watchdog_timer.expires = jiffies +
159 					msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
160 	add_timer(&dev->watchdog_timer);
161 }
162 
s5p_mfc_watchdog_worker(struct work_struct * work)163 static void s5p_mfc_watchdog_worker(struct work_struct *work)
164 {
165 	struct s5p_mfc_dev *dev;
166 	struct s5p_mfc_ctx *ctx;
167 	unsigned long flags;
168 	int mutex_locked;
169 	int i, ret;
170 
171 	dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
172 
173 	mfc_err("Driver timeout error handling\n");
174 	/* Lock the mutex that protects open and release.
175 	 * This is necessary as they may load and unload firmware. */
176 	mutex_locked = mutex_trylock(&dev->mfc_mutex);
177 	if (!mutex_locked)
178 		mfc_err("Error: some instance may be closing/opening\n");
179 	spin_lock_irqsave(&dev->irqlock, flags);
180 
181 	s5p_mfc_clock_off();
182 
183 	for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
184 		ctx = dev->ctx[i];
185 		if (!ctx)
186 			continue;
187 		ctx->state = MFCINST_ERROR;
188 		s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
189 		s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
190 		clear_work_bit(ctx);
191 		wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
192 	}
193 	clear_bit(0, &dev->hw_lock);
194 	spin_unlock_irqrestore(&dev->irqlock, flags);
195 
196 	/* De-init MFC */
197 	s5p_mfc_deinit_hw(dev);
198 
199 	/* Double check if there is at least one instance running.
200 	 * If no instance is in memory than no firmware should be present */
201 	if (dev->num_inst > 0) {
202 		ret = s5p_mfc_load_firmware(dev);
203 		if (ret) {
204 			mfc_err("Failed to reload FW\n");
205 			goto unlock;
206 		}
207 		s5p_mfc_clock_on();
208 		ret = s5p_mfc_init_hw(dev);
209 		s5p_mfc_clock_off();
210 		if (ret)
211 			mfc_err("Failed to reinit FW\n");
212 	}
213 unlock:
214 	if (mutex_locked)
215 		mutex_unlock(&dev->mfc_mutex);
216 }
217 
s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx * ctx)218 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
219 {
220 	struct s5p_mfc_buf *dst_buf;
221 	struct s5p_mfc_dev *dev = ctx->dev;
222 
223 	ctx->state = MFCINST_FINISHED;
224 	ctx->sequence++;
225 	while (!list_empty(&ctx->dst_queue)) {
226 		dst_buf = list_entry(ctx->dst_queue.next,
227 				     struct s5p_mfc_buf, list);
228 		mfc_debug(2, "Cleaning up buffer: %d\n",
229 					  dst_buf->b->vb2_buf.index);
230 		vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
231 		vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
232 		list_del(&dst_buf->list);
233 		dst_buf->flags |= MFC_BUF_FLAG_EOS;
234 		ctx->dst_queue_cnt--;
235 		dst_buf->b->sequence = (ctx->sequence++);
236 
237 		if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
238 			s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
239 			dst_buf->b->field = V4L2_FIELD_NONE;
240 		else
241 			dst_buf->b->field = V4L2_FIELD_INTERLACED;
242 		dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
243 
244 		ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
245 		vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
246 	}
247 }
248 
s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx * ctx)249 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
250 {
251 	struct s5p_mfc_dev *dev = ctx->dev;
252 	struct s5p_mfc_buf  *dst_buf, *src_buf;
253 	size_t dec_y_addr;
254 	unsigned int frame_type;
255 
256 	/* Make sure we actually have a new frame before continuing. */
257 	frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
258 	if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
259 		return;
260 	dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
261 
262 	/* Copy timestamp / timecode from decoded src to dst and set
263 	   appropriate flags. */
264 	src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
265 	list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
266 		if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
267 				== dec_y_addr) {
268 			dst_buf->b->timecode =
269 						src_buf->b->timecode;
270 			dst_buf->b->vb2_buf.timestamp =
271 						src_buf->b->vb2_buf.timestamp;
272 			dst_buf->b->flags &=
273 				~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
274 			dst_buf->b->flags |=
275 				src_buf->b->flags
276 				& V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
277 			switch (frame_type) {
278 			case S5P_FIMV_DECODE_FRAME_I_FRAME:
279 				dst_buf->b->flags |=
280 						V4L2_BUF_FLAG_KEYFRAME;
281 				break;
282 			case S5P_FIMV_DECODE_FRAME_P_FRAME:
283 				dst_buf->b->flags |=
284 						V4L2_BUF_FLAG_PFRAME;
285 				break;
286 			case S5P_FIMV_DECODE_FRAME_B_FRAME:
287 				dst_buf->b->flags |=
288 						V4L2_BUF_FLAG_BFRAME;
289 				break;
290 			default:
291 				/* Don't know how to handle
292 				   S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
293 				mfc_debug(2, "Unexpected frame type: %d\n",
294 						frame_type);
295 			}
296 			break;
297 		}
298 	}
299 }
300 
s5p_mfc_handle_frame_new(struct s5p_mfc_ctx * ctx,unsigned int err)301 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
302 {
303 	struct s5p_mfc_dev *dev = ctx->dev;
304 	struct s5p_mfc_buf  *dst_buf;
305 	size_t dspl_y_addr;
306 	unsigned int frame_type;
307 
308 	dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
309 	if (IS_MFCV6_PLUS(dev))
310 		frame_type = s5p_mfc_hw_call(dev->mfc_ops,
311 			get_disp_frame_type, ctx);
312 	else
313 		frame_type = s5p_mfc_hw_call(dev->mfc_ops,
314 			get_dec_frame_type, dev);
315 
316 	/* If frame is same as previous then skip and do not dequeue */
317 	if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
318 		if (!ctx->after_packed_pb)
319 			ctx->sequence++;
320 		ctx->after_packed_pb = 0;
321 		return;
322 	}
323 	ctx->sequence++;
324 	/* The MFC returns address of the buffer, now we have to
325 	 * check which videobuf does it correspond to */
326 	list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
327 		/* Check if this is the buffer we're looking for */
328 		if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
329 				== dspl_y_addr) {
330 			list_del(&dst_buf->list);
331 			ctx->dst_queue_cnt--;
332 			dst_buf->b->sequence = ctx->sequence;
333 			if (s5p_mfc_hw_call(dev->mfc_ops,
334 					get_pic_type_top, ctx) ==
335 				s5p_mfc_hw_call(dev->mfc_ops,
336 					get_pic_type_bot, ctx))
337 				dst_buf->b->field = V4L2_FIELD_NONE;
338 			else
339 				dst_buf->b->field =
340 							V4L2_FIELD_INTERLACED;
341 			vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
342 						ctx->luma_size);
343 			vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
344 						ctx->chroma_size);
345 			clear_bit(dst_buf->b->vb2_buf.index,
346 							&ctx->dec_dst_flag);
347 
348 			vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
349 				VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
350 
351 			break;
352 		}
353 	}
354 }
355 
356 /* Handle frame decoding interrupt */
s5p_mfc_handle_frame(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)357 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
358 					unsigned int reason, unsigned int err)
359 {
360 	struct s5p_mfc_dev *dev = ctx->dev;
361 	unsigned int dst_frame_status;
362 	unsigned int dec_frame_status;
363 	struct s5p_mfc_buf *src_buf;
364 	unsigned int res_change;
365 
366 	dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
367 				& S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
368 	dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
369 				& S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
370 	res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
371 				& S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
372 				>> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
373 	mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
374 	if (ctx->state == MFCINST_RES_CHANGE_INIT)
375 		ctx->state = MFCINST_RES_CHANGE_FLUSH;
376 	if (res_change == S5P_FIMV_RES_INCREASE ||
377 		res_change == S5P_FIMV_RES_DECREASE) {
378 		ctx->state = MFCINST_RES_CHANGE_INIT;
379 		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
380 		wake_up_ctx(ctx, reason, err);
381 		WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
382 		s5p_mfc_clock_off();
383 		s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
384 		return;
385 	}
386 	if (ctx->dpb_flush_flag)
387 		ctx->dpb_flush_flag = 0;
388 
389 	/* All frames remaining in the buffer have been extracted  */
390 	if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
391 		if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
392 			static const struct v4l2_event ev_src_ch = {
393 				.type = V4L2_EVENT_SOURCE_CHANGE,
394 				.u.src_change.changes =
395 					V4L2_EVENT_SRC_CH_RESOLUTION,
396 			};
397 
398 			s5p_mfc_handle_frame_all_extracted(ctx);
399 			ctx->state = MFCINST_RES_CHANGE_END;
400 			v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
401 
402 			goto leave_handle_frame;
403 		} else {
404 			s5p_mfc_handle_frame_all_extracted(ctx);
405 		}
406 	}
407 
408 	if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
409 		s5p_mfc_handle_frame_copy_time(ctx);
410 
411 	/* A frame has been decoded and is in the buffer  */
412 	if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
413 	    dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
414 		s5p_mfc_handle_frame_new(ctx, err);
415 	} else {
416 		mfc_debug(2, "No frame decode\n");
417 	}
418 	/* Mark source buffer as complete */
419 	if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
420 		&& !list_empty(&ctx->src_queue)) {
421 		src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
422 								list);
423 		ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
424 						get_consumed_stream, dev);
425 		if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
426 			ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
427 			ctx->consumed_stream + STUFF_BYTE <
428 			src_buf->b->vb2_buf.planes[0].bytesused) {
429 			/* Run MFC again on the same buffer */
430 			mfc_debug(2, "Running again the same buffer\n");
431 			ctx->after_packed_pb = 1;
432 		} else {
433 			mfc_debug(2, "MFC needs next buffer\n");
434 			ctx->consumed_stream = 0;
435 			if (src_buf->flags & MFC_BUF_FLAG_EOS)
436 				ctx->state = MFCINST_FINISHING;
437 			list_del(&src_buf->list);
438 			ctx->src_queue_cnt--;
439 			if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
440 				vb2_buffer_done(&src_buf->b->vb2_buf,
441 						VB2_BUF_STATE_ERROR);
442 			else
443 				vb2_buffer_done(&src_buf->b->vb2_buf,
444 						VB2_BUF_STATE_DONE);
445 		}
446 	}
447 leave_handle_frame:
448 	if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
449 				    || ctx->dst_queue_cnt < ctx->pb_count)
450 		clear_work_bit(ctx);
451 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
452 	wake_up_ctx(ctx, reason, err);
453 	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
454 	s5p_mfc_clock_off();
455 	/* if suspending, wake up device and do not try_run again*/
456 	if (test_bit(0, &dev->enter_suspend))
457 		wake_up_dev(dev, reason, err);
458 	else
459 		s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
460 }
461 
462 /* Error handling for interrupt */
s5p_mfc_handle_error(struct s5p_mfc_dev * dev,struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)463 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
464 		struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
465 {
466 	mfc_err("Interrupt Error: %08x\n", err);
467 
468 	if (ctx != NULL) {
469 		/* Error recovery is dependent on the state of context */
470 		switch (ctx->state) {
471 		case MFCINST_RES_CHANGE_INIT:
472 		case MFCINST_RES_CHANGE_FLUSH:
473 		case MFCINST_RES_CHANGE_END:
474 		case MFCINST_FINISHING:
475 		case MFCINST_FINISHED:
476 		case MFCINST_RUNNING:
477 			/* It is highly probable that an error occurred
478 			 * while decoding a frame */
479 			clear_work_bit(ctx);
480 			ctx->state = MFCINST_ERROR;
481 			/* Mark all dst buffers as having an error */
482 			s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
483 			/* Mark all src buffers as having an error */
484 			s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
485 			wake_up_ctx(ctx, reason, err);
486 			break;
487 		default:
488 			clear_work_bit(ctx);
489 			ctx->state = MFCINST_ERROR;
490 			wake_up_ctx(ctx, reason, err);
491 			break;
492 		}
493 	}
494 	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
495 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
496 	s5p_mfc_clock_off();
497 	wake_up_dev(dev, reason, err);
498 }
499 
500 /* Header parsing interrupt handling */
s5p_mfc_handle_seq_done(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)501 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
502 				 unsigned int reason, unsigned int err)
503 {
504 	struct s5p_mfc_dev *dev;
505 
506 	if (ctx == NULL)
507 		return;
508 	dev = ctx->dev;
509 	if (ctx->c_ops->post_seq_start) {
510 		if (ctx->c_ops->post_seq_start(ctx))
511 			mfc_err("post_seq_start() failed\n");
512 	} else {
513 		ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
514 				dev);
515 		ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
516 				dev);
517 
518 		s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
519 
520 		ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
521 				dev);
522 		ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
523 				dev);
524 		if (ctx->img_width == 0 || ctx->img_height == 0)
525 			ctx->state = MFCINST_ERROR;
526 		else
527 			ctx->state = MFCINST_HEAD_PARSED;
528 
529 		if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
530 			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
531 				!list_empty(&ctx->src_queue)) {
532 			struct s5p_mfc_buf *src_buf;
533 			src_buf = list_entry(ctx->src_queue.next,
534 					struct s5p_mfc_buf, list);
535 			if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
536 						dev) <
537 					src_buf->b->vb2_buf.planes[0].bytesused)
538 				ctx->head_processed = 0;
539 			else
540 				ctx->head_processed = 1;
541 		} else {
542 			ctx->head_processed = 1;
543 		}
544 	}
545 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
546 	clear_work_bit(ctx);
547 	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
548 	s5p_mfc_clock_off();
549 	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
550 	wake_up_ctx(ctx, reason, err);
551 }
552 
553 /* Header parsing interrupt handling */
s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)554 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
555 				 unsigned int reason, unsigned int err)
556 {
557 	struct s5p_mfc_buf *src_buf;
558 	struct s5p_mfc_dev *dev;
559 
560 	if (ctx == NULL)
561 		return;
562 	dev = ctx->dev;
563 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
564 	ctx->int_type = reason;
565 	ctx->int_err = err;
566 	ctx->int_cond = 1;
567 	clear_work_bit(ctx);
568 	if (err == 0) {
569 		ctx->state = MFCINST_RUNNING;
570 		if (!ctx->dpb_flush_flag && ctx->head_processed) {
571 			if (!list_empty(&ctx->src_queue)) {
572 				src_buf = list_entry(ctx->src_queue.next,
573 					     struct s5p_mfc_buf, list);
574 				list_del(&src_buf->list);
575 				ctx->src_queue_cnt--;
576 				vb2_buffer_done(&src_buf->b->vb2_buf,
577 						VB2_BUF_STATE_DONE);
578 			}
579 		} else {
580 			ctx->dpb_flush_flag = 0;
581 		}
582 		WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
583 
584 		s5p_mfc_clock_off();
585 
586 		wake_up(&ctx->queue);
587 		s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
588 	} else {
589 		WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
590 
591 		s5p_mfc_clock_off();
592 
593 		wake_up(&ctx->queue);
594 	}
595 }
596 
s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx * ctx)597 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
598 {
599 	struct s5p_mfc_dev *dev = ctx->dev;
600 	struct s5p_mfc_buf *mb_entry;
601 
602 	mfc_debug(2, "Stream completed\n");
603 
604 	ctx->state = MFCINST_FINISHED;
605 
606 	if (!list_empty(&ctx->dst_queue)) {
607 		mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
608 									list);
609 		list_del(&mb_entry->list);
610 		ctx->dst_queue_cnt--;
611 		vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
612 		vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
613 	}
614 
615 	clear_work_bit(ctx);
616 
617 	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
618 
619 	s5p_mfc_clock_off();
620 	wake_up(&ctx->queue);
621 	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
622 }
623 
624 /* Interrupt processing */
s5p_mfc_irq(int irq,void * priv)625 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
626 {
627 	struct s5p_mfc_dev *dev = priv;
628 	struct s5p_mfc_ctx *ctx;
629 	unsigned int reason;
630 	unsigned int err;
631 
632 	mfc_debug_enter();
633 	/* Reset the timeout watchdog */
634 	atomic_set(&dev->watchdog_cnt, 0);
635 	spin_lock(&dev->irqlock);
636 	ctx = dev->ctx[dev->curr_ctx];
637 	/* Get the reason of interrupt and the error code */
638 	reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
639 	err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
640 	mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
641 	switch (reason) {
642 	case S5P_MFC_R2H_CMD_ERR_RET:
643 		/* An error has occurred */
644 		if (ctx->state == MFCINST_RUNNING &&
645 			s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
646 				dev->warn_start)
647 			s5p_mfc_handle_frame(ctx, reason, err);
648 		else
649 			s5p_mfc_handle_error(dev, ctx, reason, err);
650 		clear_bit(0, &dev->enter_suspend);
651 		break;
652 
653 	case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
654 	case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
655 	case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
656 		if (ctx->c_ops->post_frame_start) {
657 			if (ctx->c_ops->post_frame_start(ctx))
658 				mfc_err("post_frame_start() failed\n");
659 
660 			if (ctx->state == MFCINST_FINISHING &&
661 						list_empty(&ctx->ref_queue)) {
662 				s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
663 				s5p_mfc_handle_stream_complete(ctx);
664 				break;
665 			}
666 			s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
667 			WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
668 			s5p_mfc_clock_off();
669 			wake_up_ctx(ctx, reason, err);
670 			s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
671 		} else {
672 			s5p_mfc_handle_frame(ctx, reason, err);
673 		}
674 		break;
675 
676 	case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
677 		s5p_mfc_handle_seq_done(ctx, reason, err);
678 		break;
679 
680 	case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
681 		ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
682 		ctx->state = MFCINST_GOT_INST;
683 		goto irq_cleanup_hw;
684 
685 	case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
686 		ctx->inst_no = MFC_NO_INSTANCE_SET;
687 		ctx->state = MFCINST_FREE;
688 		goto irq_cleanup_hw;
689 
690 	case S5P_MFC_R2H_CMD_SYS_INIT_RET:
691 	case S5P_MFC_R2H_CMD_FW_STATUS_RET:
692 	case S5P_MFC_R2H_CMD_SLEEP_RET:
693 	case S5P_MFC_R2H_CMD_WAKEUP_RET:
694 		if (ctx)
695 			clear_work_bit(ctx);
696 		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
697 		clear_bit(0, &dev->hw_lock);
698 		clear_bit(0, &dev->enter_suspend);
699 		wake_up_dev(dev, reason, err);
700 		break;
701 
702 	case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
703 		s5p_mfc_handle_init_buffers(ctx, reason, err);
704 		break;
705 
706 	case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
707 		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
708 		ctx->int_type = reason;
709 		ctx->int_err = err;
710 		s5p_mfc_handle_stream_complete(ctx);
711 		break;
712 
713 	case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
714 		ctx->state = MFCINST_RUNNING;
715 		goto irq_cleanup_hw;
716 
717 	default:
718 		mfc_debug(2, "Unknown int reason\n");
719 		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
720 	}
721 	spin_unlock(&dev->irqlock);
722 	mfc_debug_leave();
723 	return IRQ_HANDLED;
724 irq_cleanup_hw:
725 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
726 	ctx->int_type = reason;
727 	ctx->int_err = err;
728 	ctx->int_cond = 1;
729 	if (test_and_clear_bit(0, &dev->hw_lock) == 0)
730 		mfc_err("Failed to unlock hw\n");
731 
732 	s5p_mfc_clock_off();
733 	clear_work_bit(ctx);
734 	wake_up(&ctx->queue);
735 
736 	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
737 	spin_unlock(&dev->irqlock);
738 	mfc_debug(2, "Exit via irq_cleanup_hw\n");
739 	return IRQ_HANDLED;
740 }
741 
742 /* Open an MFC node */
s5p_mfc_open(struct file * file)743 static int s5p_mfc_open(struct file *file)
744 {
745 	struct video_device *vdev = video_devdata(file);
746 	struct s5p_mfc_dev *dev = video_drvdata(file);
747 	struct s5p_mfc_ctx *ctx = NULL;
748 	struct vb2_queue *q;
749 	int ret = 0;
750 
751 	mfc_debug_enter();
752 	if (mutex_lock_interruptible(&dev->mfc_mutex))
753 		return -ERESTARTSYS;
754 	dev->num_inst++;	/* It is guarded by mfc_mutex in vfd */
755 	/* Allocate memory for context */
756 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
757 	if (!ctx) {
758 		ret = -ENOMEM;
759 		goto err_alloc;
760 	}
761 	v4l2_fh_init(&ctx->fh, vdev);
762 	file->private_data = &ctx->fh;
763 	v4l2_fh_add(&ctx->fh);
764 	ctx->dev = dev;
765 	INIT_LIST_HEAD(&ctx->src_queue);
766 	INIT_LIST_HEAD(&ctx->dst_queue);
767 	ctx->src_queue_cnt = 0;
768 	ctx->dst_queue_cnt = 0;
769 	/* Get context number */
770 	ctx->num = 0;
771 	while (dev->ctx[ctx->num]) {
772 		ctx->num++;
773 		if (ctx->num >= MFC_NUM_CONTEXTS) {
774 			mfc_debug(2, "Too many open contexts\n");
775 			ret = -EBUSY;
776 			goto err_no_ctx;
777 		}
778 	}
779 	/* Mark context as idle */
780 	clear_work_bit_irqsave(ctx);
781 	dev->ctx[ctx->num] = ctx;
782 	if (vdev == dev->vfd_dec) {
783 		ctx->type = MFCINST_DECODER;
784 		ctx->c_ops = get_dec_codec_ops();
785 		s5p_mfc_dec_init(ctx);
786 		/* Setup ctrl handler */
787 		ret = s5p_mfc_dec_ctrls_setup(ctx);
788 		if (ret) {
789 			mfc_err("Failed to setup mfc controls\n");
790 			goto err_ctrls_setup;
791 		}
792 	} else if (vdev == dev->vfd_enc) {
793 		ctx->type = MFCINST_ENCODER;
794 		ctx->c_ops = get_enc_codec_ops();
795 		/* only for encoder */
796 		INIT_LIST_HEAD(&ctx->ref_queue);
797 		ctx->ref_queue_cnt = 0;
798 		s5p_mfc_enc_init(ctx);
799 		/* Setup ctrl handler */
800 		ret = s5p_mfc_enc_ctrls_setup(ctx);
801 		if (ret) {
802 			mfc_err("Failed to setup mfc controls\n");
803 			goto err_ctrls_setup;
804 		}
805 	} else {
806 		ret = -ENOENT;
807 		goto err_bad_node;
808 	}
809 	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
810 	ctx->inst_no = MFC_NO_INSTANCE_SET;
811 	/* Load firmware if this is the first instance */
812 	if (dev->num_inst == 1) {
813 		dev->watchdog_timer.expires = jiffies +
814 					msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
815 		add_timer(&dev->watchdog_timer);
816 		ret = s5p_mfc_power_on();
817 		if (ret < 0) {
818 			mfc_err("power on failed\n");
819 			goto err_pwr_enable;
820 		}
821 		s5p_mfc_clock_on();
822 		ret = s5p_mfc_load_firmware(dev);
823 		if (ret) {
824 			s5p_mfc_clock_off();
825 			goto err_load_fw;
826 		}
827 		/* Init the FW */
828 		ret = s5p_mfc_init_hw(dev);
829 		s5p_mfc_clock_off();
830 		if (ret)
831 			goto err_init_hw;
832 	}
833 	/* Init videobuf2 queue for CAPTURE */
834 	q = &ctx->vq_dst;
835 	q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
836 	q->drv_priv = &ctx->fh;
837 	q->lock = &dev->mfc_mutex;
838 	if (vdev == dev->vfd_dec) {
839 		q->io_modes = VB2_MMAP;
840 		q->ops = get_dec_queue_ops();
841 	} else if (vdev == dev->vfd_enc) {
842 		q->io_modes = VB2_MMAP | VB2_USERPTR;
843 		q->ops = get_enc_queue_ops();
844 	} else {
845 		ret = -ENOENT;
846 		goto err_queue_init;
847 	}
848 	q->mem_ops = &vb2_dma_contig_memops;
849 	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
850 	ret = vb2_queue_init(q);
851 	if (ret) {
852 		mfc_err("Failed to initialize videobuf2 queue(capture)\n");
853 		goto err_queue_init;
854 	}
855 	/* Init videobuf2 queue for OUTPUT */
856 	q = &ctx->vq_src;
857 	q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
858 	q->io_modes = VB2_MMAP;
859 	q->drv_priv = &ctx->fh;
860 	q->lock = &dev->mfc_mutex;
861 	if (vdev == dev->vfd_dec) {
862 		q->io_modes = VB2_MMAP;
863 		q->ops = get_dec_queue_ops();
864 	} else if (vdev == dev->vfd_enc) {
865 		q->io_modes = VB2_MMAP | VB2_USERPTR;
866 		q->ops = get_enc_queue_ops();
867 	} else {
868 		ret = -ENOENT;
869 		goto err_queue_init;
870 	}
871 	/* One way to indicate end-of-stream for MFC is to set the
872 	 * bytesused == 0. However by default videobuf2 handles bytesused
873 	 * equal to 0 as a special case and changes its value to the size
874 	 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
875 	 * will keep the value of bytesused intact.
876 	 */
877 	q->allow_zero_bytesused = 1;
878 	q->mem_ops = &vb2_dma_contig_memops;
879 	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
880 	ret = vb2_queue_init(q);
881 	if (ret) {
882 		mfc_err("Failed to initialize videobuf2 queue(output)\n");
883 		goto err_queue_init;
884 	}
885 	init_waitqueue_head(&ctx->queue);
886 	mutex_unlock(&dev->mfc_mutex);
887 	mfc_debug_leave();
888 	return ret;
889 	/* Deinit when failure occurred */
890 err_queue_init:
891 	if (dev->num_inst == 1)
892 		s5p_mfc_deinit_hw(dev);
893 err_init_hw:
894 err_load_fw:
895 err_pwr_enable:
896 	if (dev->num_inst == 1) {
897 		if (s5p_mfc_power_off() < 0)
898 			mfc_err("power off failed\n");
899 		del_timer_sync(&dev->watchdog_timer);
900 	}
901 err_ctrls_setup:
902 	s5p_mfc_dec_ctrls_delete(ctx);
903 err_bad_node:
904 	dev->ctx[ctx->num] = NULL;
905 err_no_ctx:
906 	v4l2_fh_del(&ctx->fh);
907 	v4l2_fh_exit(&ctx->fh);
908 	kfree(ctx);
909 err_alloc:
910 	dev->num_inst--;
911 	mutex_unlock(&dev->mfc_mutex);
912 	mfc_debug_leave();
913 	return ret;
914 }
915 
916 /* Release MFC context */
s5p_mfc_release(struct file * file)917 static int s5p_mfc_release(struct file *file)
918 {
919 	struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
920 	struct s5p_mfc_dev *dev = ctx->dev;
921 
922 	/* if dev is null, do cleanup that doesn't need dev */
923 	mfc_debug_enter();
924 	if (dev)
925 		mutex_lock(&dev->mfc_mutex);
926 	vb2_queue_release(&ctx->vq_src);
927 	vb2_queue_release(&ctx->vq_dst);
928 	if (dev) {
929 		s5p_mfc_clock_on();
930 
931 		/* Mark context as idle */
932 		clear_work_bit_irqsave(ctx);
933 		/*
934 		 * If instance was initialised and not yet freed,
935 		 * return instance and free resources
936 		*/
937 		if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
938 			mfc_debug(2, "Has to free instance\n");
939 			s5p_mfc_close_mfc_inst(dev, ctx);
940 		}
941 		/* hardware locking scheme */
942 		if (dev->curr_ctx == ctx->num)
943 			clear_bit(0, &dev->hw_lock);
944 		dev->num_inst--;
945 		if (dev->num_inst == 0) {
946 			mfc_debug(2, "Last instance\n");
947 			s5p_mfc_deinit_hw(dev);
948 			del_timer_sync(&dev->watchdog_timer);
949 			if (s5p_mfc_power_off() < 0)
950 				mfc_err("Power off failed\n");
951 		}
952 		mfc_debug(2, "Shutting down clock\n");
953 		s5p_mfc_clock_off();
954 	}
955 	if (dev)
956 		dev->ctx[ctx->num] = NULL;
957 	s5p_mfc_dec_ctrls_delete(ctx);
958 	v4l2_fh_del(&ctx->fh);
959 	/* vdev is gone if dev is null */
960 	if (dev)
961 		v4l2_fh_exit(&ctx->fh);
962 	kfree(ctx);
963 	mfc_debug_leave();
964 	if (dev)
965 		mutex_unlock(&dev->mfc_mutex);
966 
967 	return 0;
968 }
969 
970 /* Poll */
s5p_mfc_poll(struct file * file,struct poll_table_struct * wait)971 static unsigned int s5p_mfc_poll(struct file *file,
972 				 struct poll_table_struct *wait)
973 {
974 	struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
975 	struct s5p_mfc_dev *dev = ctx->dev;
976 	struct vb2_queue *src_q, *dst_q;
977 	struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
978 	unsigned int rc = 0;
979 	unsigned long flags;
980 
981 	mutex_lock(&dev->mfc_mutex);
982 	src_q = &ctx->vq_src;
983 	dst_q = &ctx->vq_dst;
984 	/*
985 	 * There has to be at least one buffer queued on each queued_list, which
986 	 * means either in driver already or waiting for driver to claim it
987 	 * and start processing.
988 	 */
989 	if ((!src_q->streaming || list_empty(&src_q->queued_list))
990 		&& (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
991 		rc = POLLERR;
992 		goto end;
993 	}
994 	mutex_unlock(&dev->mfc_mutex);
995 	poll_wait(file, &ctx->fh.wait, wait);
996 	poll_wait(file, &src_q->done_wq, wait);
997 	poll_wait(file, &dst_q->done_wq, wait);
998 	mutex_lock(&dev->mfc_mutex);
999 	if (v4l2_event_pending(&ctx->fh))
1000 		rc |= POLLPRI;
1001 	spin_lock_irqsave(&src_q->done_lock, flags);
1002 	if (!list_empty(&src_q->done_list))
1003 		src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
1004 								done_entry);
1005 	if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
1006 				|| src_vb->state == VB2_BUF_STATE_ERROR))
1007 		rc |= POLLOUT | POLLWRNORM;
1008 	spin_unlock_irqrestore(&src_q->done_lock, flags);
1009 	spin_lock_irqsave(&dst_q->done_lock, flags);
1010 	if (!list_empty(&dst_q->done_list))
1011 		dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1012 								done_entry);
1013 	if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1014 				|| dst_vb->state == VB2_BUF_STATE_ERROR))
1015 		rc |= POLLIN | POLLRDNORM;
1016 	spin_unlock_irqrestore(&dst_q->done_lock, flags);
1017 end:
1018 	mutex_unlock(&dev->mfc_mutex);
1019 	return rc;
1020 }
1021 
1022 /* Mmap */
s5p_mfc_mmap(struct file * file,struct vm_area_struct * vma)1023 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1024 {
1025 	struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1026 	struct s5p_mfc_dev *dev = ctx->dev;
1027 	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1028 	int ret;
1029 
1030 	if (mutex_lock_interruptible(&dev->mfc_mutex))
1031 		return -ERESTARTSYS;
1032 	if (offset < DST_QUEUE_OFF_BASE) {
1033 		mfc_debug(2, "mmaping source\n");
1034 		ret = vb2_mmap(&ctx->vq_src, vma);
1035 	} else {		/* capture */
1036 		mfc_debug(2, "mmaping destination\n");
1037 		vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1038 		ret = vb2_mmap(&ctx->vq_dst, vma);
1039 	}
1040 	mutex_unlock(&dev->mfc_mutex);
1041 	return ret;
1042 }
1043 
1044 /* v4l2 ops */
1045 static const struct v4l2_file_operations s5p_mfc_fops = {
1046 	.owner = THIS_MODULE,
1047 	.open = s5p_mfc_open,
1048 	.release = s5p_mfc_release,
1049 	.poll = s5p_mfc_poll,
1050 	.unlocked_ioctl = video_ioctl2,
1051 	.mmap = s5p_mfc_mmap,
1052 };
1053 
1054 /* DMA memory related helper functions */
s5p_mfc_memdev_release(struct device * dev)1055 static void s5p_mfc_memdev_release(struct device *dev)
1056 {
1057 	of_reserved_mem_device_release(dev);
1058 }
1059 
s5p_mfc_alloc_memdev(struct device * dev,const char * name,unsigned int idx)1060 static struct device *s5p_mfc_alloc_memdev(struct device *dev,
1061 					   const char *name, unsigned int idx)
1062 {
1063 	struct device *child;
1064 	int ret;
1065 
1066 	child = devm_kzalloc(dev, sizeof(struct device), GFP_KERNEL);
1067 	if (!child)
1068 		return NULL;
1069 
1070 	device_initialize(child);
1071 	dev_set_name(child, "%s:%s", dev_name(dev), name);
1072 	child->parent = dev;
1073 	child->bus = dev->bus;
1074 	child->coherent_dma_mask = dev->coherent_dma_mask;
1075 	child->dma_mask = dev->dma_mask;
1076 	child->release = s5p_mfc_memdev_release;
1077 
1078 	if (device_add(child) == 0) {
1079 		ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
1080 							 idx);
1081 		if (ret == 0)
1082 			return child;
1083 		device_del(child);
1084 	}
1085 
1086 	put_device(child);
1087 	return NULL;
1088 }
1089 
s5p_mfc_configure_dma_memory(struct s5p_mfc_dev * mfc_dev)1090 static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1091 {
1092 	struct device *dev = &mfc_dev->plat_dev->dev;
1093 
1094 	/*
1095 	 * When IOMMU is available, we cannot use the default configuration,
1096 	 * because of MFC firmware requirements: address space limited to
1097 	 * 256M and non-zero default start address.
1098 	 * This is still simplified, not optimal configuration, but for now
1099 	 * IOMMU core doesn't allow to configure device's IOMMUs channel
1100 	 * separately.
1101 	 */
1102 	if (exynos_is_iommu_available(dev)) {
1103 		int ret = exynos_configure_iommu(dev, S5P_MFC_IOMMU_DMA_BASE,
1104 						 S5P_MFC_IOMMU_DMA_SIZE);
1105 		if (ret == 0)
1106 			mfc_dev->mem_dev_l = mfc_dev->mem_dev_r = dev;
1107 		return ret;
1108 	}
1109 
1110 	/*
1111 	 * Create and initialize virtual devices for accessing
1112 	 * reserved memory regions.
1113 	 */
1114 	mfc_dev->mem_dev_l = s5p_mfc_alloc_memdev(dev, "left",
1115 						  MFC_BANK1_ALLOC_CTX);
1116 	if (!mfc_dev->mem_dev_l)
1117 		return -ENODEV;
1118 	mfc_dev->mem_dev_r = s5p_mfc_alloc_memdev(dev, "right",
1119 						  MFC_BANK2_ALLOC_CTX);
1120 	if (!mfc_dev->mem_dev_r) {
1121 		device_unregister(mfc_dev->mem_dev_l);
1122 		return -ENODEV;
1123 	}
1124 
1125 	return 0;
1126 }
1127 
s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev * mfc_dev)1128 static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1129 {
1130 	struct device *dev = &mfc_dev->plat_dev->dev;
1131 
1132 	if (exynos_is_iommu_available(dev)) {
1133 		exynos_unconfigure_iommu(dev);
1134 		return;
1135 	}
1136 
1137 	device_unregister(mfc_dev->mem_dev_l);
1138 	device_unregister(mfc_dev->mem_dev_r);
1139 }
1140 
1141 static void *mfc_get_drv_data(struct platform_device *pdev);
1142 
1143 /* MFC probe function */
s5p_mfc_probe(struct platform_device * pdev)1144 static int s5p_mfc_probe(struct platform_device *pdev)
1145 {
1146 	struct s5p_mfc_dev *dev;
1147 	struct video_device *vfd;
1148 	struct resource *res;
1149 	int ret;
1150 
1151 	pr_debug("%s++\n", __func__);
1152 	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1153 	if (!dev) {
1154 		dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1155 		return -ENOMEM;
1156 	}
1157 
1158 	spin_lock_init(&dev->irqlock);
1159 	spin_lock_init(&dev->condlock);
1160 	dev->plat_dev = pdev;
1161 	if (!dev->plat_dev) {
1162 		dev_err(&pdev->dev, "No platform data specified\n");
1163 		return -ENODEV;
1164 	}
1165 
1166 	dev->variant = mfc_get_drv_data(pdev);
1167 
1168 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1169 	dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1170 	if (IS_ERR(dev->regs_base))
1171 		return PTR_ERR(dev->regs_base);
1172 
1173 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1174 	if (res == NULL) {
1175 		dev_err(&pdev->dev, "failed to get irq resource\n");
1176 		return -ENOENT;
1177 	}
1178 	dev->irq = res->start;
1179 	ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1180 					0, pdev->name, dev);
1181 	if (ret) {
1182 		dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1183 		return ret;
1184 	}
1185 
1186 	ret = s5p_mfc_configure_dma_memory(dev);
1187 	if (ret < 0) {
1188 		dev_err(&pdev->dev, "failed to configure DMA memory\n");
1189 		return ret;
1190 	}
1191 
1192 	ret = s5p_mfc_init_pm(dev);
1193 	if (ret < 0) {
1194 		dev_err(&pdev->dev, "failed to get mfc clock source\n");
1195 		goto err_dma;
1196 	}
1197 
1198 	vb2_dma_contig_set_max_seg_size(dev->mem_dev_l, DMA_BIT_MASK(32));
1199 	vb2_dma_contig_set_max_seg_size(dev->mem_dev_r, DMA_BIT_MASK(32));
1200 
1201 	mutex_init(&dev->mfc_mutex);
1202 
1203 	ret = s5p_mfc_alloc_firmware(dev);
1204 	if (ret)
1205 		goto err_res;
1206 
1207 	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1208 	if (ret)
1209 		goto err_v4l2_dev_reg;
1210 	init_waitqueue_head(&dev->queue);
1211 
1212 	/* decoder */
1213 	vfd = video_device_alloc();
1214 	if (!vfd) {
1215 		v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1216 		ret = -ENOMEM;
1217 		goto err_dec_alloc;
1218 	}
1219 	vfd->fops	= &s5p_mfc_fops;
1220 	vfd->ioctl_ops	= get_dec_v4l2_ioctl_ops();
1221 	vfd->release	= video_device_release;
1222 	vfd->lock	= &dev->mfc_mutex;
1223 	vfd->v4l2_dev	= &dev->v4l2_dev;
1224 	vfd->vfl_dir	= VFL_DIR_M2M;
1225 	snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1226 	dev->vfd_dec	= vfd;
1227 	video_set_drvdata(vfd, dev);
1228 
1229 	/* encoder */
1230 	vfd = video_device_alloc();
1231 	if (!vfd) {
1232 		v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1233 		ret = -ENOMEM;
1234 		goto err_enc_alloc;
1235 	}
1236 	vfd->fops	= &s5p_mfc_fops;
1237 	vfd->ioctl_ops	= get_enc_v4l2_ioctl_ops();
1238 	vfd->release	= video_device_release;
1239 	vfd->lock	= &dev->mfc_mutex;
1240 	vfd->v4l2_dev	= &dev->v4l2_dev;
1241 	vfd->vfl_dir	= VFL_DIR_M2M;
1242 	snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1243 	dev->vfd_enc	= vfd;
1244 	video_set_drvdata(vfd, dev);
1245 	platform_set_drvdata(pdev, dev);
1246 
1247 	dev->hw_lock = 0;
1248 	INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1249 	atomic_set(&dev->watchdog_cnt, 0);
1250 	init_timer(&dev->watchdog_timer);
1251 	dev->watchdog_timer.data = (unsigned long)dev;
1252 	dev->watchdog_timer.function = s5p_mfc_watchdog;
1253 
1254 	/* Initialize HW ops and commands based on MFC version */
1255 	s5p_mfc_init_hw_ops(dev);
1256 	s5p_mfc_init_hw_cmds(dev);
1257 	s5p_mfc_init_regs(dev);
1258 
1259 	/* Register decoder and encoder */
1260 	ret = video_register_device(dev->vfd_dec, VFL_TYPE_GRABBER, 0);
1261 	if (ret) {
1262 		v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1263 		goto err_dec_reg;
1264 	}
1265 	v4l2_info(&dev->v4l2_dev,
1266 		  "decoder registered as /dev/video%d\n", dev->vfd_dec->num);
1267 
1268 	ret = video_register_device(dev->vfd_enc, VFL_TYPE_GRABBER, 0);
1269 	if (ret) {
1270 		v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1271 		goto err_enc_reg;
1272 	}
1273 	v4l2_info(&dev->v4l2_dev,
1274 		  "encoder registered as /dev/video%d\n", dev->vfd_enc->num);
1275 
1276 	pr_debug("%s--\n", __func__);
1277 	return 0;
1278 
1279 /* Deinit MFC if probe had failed */
1280 err_enc_reg:
1281 	video_unregister_device(dev->vfd_dec);
1282 err_dec_reg:
1283 	video_device_release(dev->vfd_enc);
1284 err_enc_alloc:
1285 	video_device_release(dev->vfd_dec);
1286 err_dec_alloc:
1287 	v4l2_device_unregister(&dev->v4l2_dev);
1288 err_v4l2_dev_reg:
1289 	s5p_mfc_release_firmware(dev);
1290 err_res:
1291 	s5p_mfc_final_pm(dev);
1292 err_dma:
1293 	s5p_mfc_unconfigure_dma_memory(dev);
1294 
1295 	pr_debug("%s-- with error\n", __func__);
1296 	return ret;
1297 
1298 }
1299 
1300 /* Remove the driver */
s5p_mfc_remove(struct platform_device * pdev)1301 static int s5p_mfc_remove(struct platform_device *pdev)
1302 {
1303 	struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1304 	struct s5p_mfc_ctx *ctx;
1305 	int i;
1306 
1307 	v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1308 
1309 	/*
1310 	 * Clear ctx dev pointer to avoid races between s5p_mfc_remove()
1311 	 * and s5p_mfc_release() and s5p_mfc_release() accessing ctx->dev
1312 	 * after s5p_mfc_remove() is run during unbind.
1313 	*/
1314 	mutex_lock(&dev->mfc_mutex);
1315 	for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
1316 		ctx = dev->ctx[i];
1317 		if (!ctx)
1318 			continue;
1319 		/* clear ctx->dev */
1320 		ctx->dev = NULL;
1321 	}
1322 	mutex_unlock(&dev->mfc_mutex);
1323 
1324 	del_timer_sync(&dev->watchdog_timer);
1325 	flush_work(&dev->watchdog_work);
1326 
1327 	video_unregister_device(dev->vfd_enc);
1328 	video_unregister_device(dev->vfd_dec);
1329 	video_device_release(dev->vfd_enc);
1330 	video_device_release(dev->vfd_dec);
1331 	v4l2_device_unregister(&dev->v4l2_dev);
1332 	s5p_mfc_release_firmware(dev);
1333 	s5p_mfc_unconfigure_dma_memory(dev);
1334 	vb2_dma_contig_clear_max_seg_size(dev->mem_dev_l);
1335 	vb2_dma_contig_clear_max_seg_size(dev->mem_dev_r);
1336 
1337 	s5p_mfc_final_pm(dev);
1338 	return 0;
1339 }
1340 
1341 #ifdef CONFIG_PM_SLEEP
1342 
s5p_mfc_suspend(struct device * dev)1343 static int s5p_mfc_suspend(struct device *dev)
1344 {
1345 	struct platform_device *pdev = to_platform_device(dev);
1346 	struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1347 	int ret;
1348 
1349 	if (m_dev->num_inst == 0)
1350 		return 0;
1351 
1352 	if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1353 		mfc_err("Error: going to suspend for a second time\n");
1354 		return -EIO;
1355 	}
1356 
1357 	/* Check if we're processing then wait if it necessary. */
1358 	while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1359 		/* Try and lock the HW */
1360 		/* Wait on the interrupt waitqueue */
1361 		ret = wait_event_interruptible_timeout(m_dev->queue,
1362 			m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1363 		if (ret == 0) {
1364 			mfc_err("Waiting for hardware to finish timed out\n");
1365 			clear_bit(0, &m_dev->enter_suspend);
1366 			return -EIO;
1367 		}
1368 	}
1369 
1370 	ret = s5p_mfc_sleep(m_dev);
1371 	if (ret) {
1372 		clear_bit(0, &m_dev->enter_suspend);
1373 		clear_bit(0, &m_dev->hw_lock);
1374 	}
1375 	return ret;
1376 }
1377 
s5p_mfc_resume(struct device * dev)1378 static int s5p_mfc_resume(struct device *dev)
1379 {
1380 	struct platform_device *pdev = to_platform_device(dev);
1381 	struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1382 
1383 	if (m_dev->num_inst == 0)
1384 		return 0;
1385 	return s5p_mfc_wakeup(m_dev);
1386 }
1387 #endif
1388 
1389 #ifdef CONFIG_PM
s5p_mfc_runtime_suspend(struct device * dev)1390 static int s5p_mfc_runtime_suspend(struct device *dev)
1391 {
1392 	struct platform_device *pdev = to_platform_device(dev);
1393 	struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1394 
1395 	atomic_set(&m_dev->pm.power, 0);
1396 	return 0;
1397 }
1398 
s5p_mfc_runtime_resume(struct device * dev)1399 static int s5p_mfc_runtime_resume(struct device *dev)
1400 {
1401 	struct platform_device *pdev = to_platform_device(dev);
1402 	struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1403 
1404 	atomic_set(&m_dev->pm.power, 1);
1405 	return 0;
1406 }
1407 #endif
1408 
1409 /* Power management */
1410 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1411 	SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1412 	SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1413 			   NULL)
1414 };
1415 
1416 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1417 	.h264_ctx	= MFC_H264_CTX_BUF_SIZE,
1418 	.non_h264_ctx	= MFC_CTX_BUF_SIZE,
1419 	.dsc		= DESC_BUF_SIZE,
1420 	.shm		= SHARED_BUF_SIZE,
1421 };
1422 
1423 static struct s5p_mfc_buf_size buf_size_v5 = {
1424 	.fw	= MAX_FW_SIZE,
1425 	.cpb	= MAX_CPB_SIZE,
1426 	.priv	= &mfc_buf_size_v5,
1427 };
1428 
1429 static struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1430 	.base = MFC_BASE_ALIGN_ORDER,
1431 };
1432 
1433 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1434 	.version	= MFC_VERSION,
1435 	.version_bit	= MFC_V5_BIT,
1436 	.port_num	= MFC_NUM_PORTS,
1437 	.buf_size	= &buf_size_v5,
1438 	.buf_align	= &mfc_buf_align_v5,
1439 	.fw_name[0]	= "s5p-mfc.fw",
1440 };
1441 
1442 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1443 	.dev_ctx	= MFC_CTX_BUF_SIZE_V6,
1444 	.h264_dec_ctx	= MFC_H264_DEC_CTX_BUF_SIZE_V6,
1445 	.other_dec_ctx	= MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1446 	.h264_enc_ctx	= MFC_H264_ENC_CTX_BUF_SIZE_V6,
1447 	.other_enc_ctx	= MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1448 };
1449 
1450 static struct s5p_mfc_buf_size buf_size_v6 = {
1451 	.fw	= MAX_FW_SIZE_V6,
1452 	.cpb	= MAX_CPB_SIZE_V6,
1453 	.priv	= &mfc_buf_size_v6,
1454 };
1455 
1456 static struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1457 	.base = 0,
1458 };
1459 
1460 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1461 	.version	= MFC_VERSION_V6,
1462 	.version_bit	= MFC_V6_BIT,
1463 	.port_num	= MFC_NUM_PORTS_V6,
1464 	.buf_size	= &buf_size_v6,
1465 	.buf_align	= &mfc_buf_align_v6,
1466 	.fw_name[0]     = "s5p-mfc-v6.fw",
1467 	/*
1468 	 * v6-v2 firmware contains bug fixes and interface change
1469 	 * for init buffer command
1470 	 */
1471 	.fw_name[1]     = "s5p-mfc-v6-v2.fw",
1472 };
1473 
1474 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1475 	.dev_ctx	= MFC_CTX_BUF_SIZE_V7,
1476 	.h264_dec_ctx	= MFC_H264_DEC_CTX_BUF_SIZE_V7,
1477 	.other_dec_ctx	= MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1478 	.h264_enc_ctx	= MFC_H264_ENC_CTX_BUF_SIZE_V7,
1479 	.other_enc_ctx	= MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1480 };
1481 
1482 static struct s5p_mfc_buf_size buf_size_v7 = {
1483 	.fw	= MAX_FW_SIZE_V7,
1484 	.cpb	= MAX_CPB_SIZE_V7,
1485 	.priv	= &mfc_buf_size_v7,
1486 };
1487 
1488 static struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1489 	.base = 0,
1490 };
1491 
1492 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1493 	.version	= MFC_VERSION_V7,
1494 	.version_bit	= MFC_V7_BIT,
1495 	.port_num	= MFC_NUM_PORTS_V7,
1496 	.buf_size	= &buf_size_v7,
1497 	.buf_align	= &mfc_buf_align_v7,
1498 	.fw_name[0]     = "s5p-mfc-v7.fw",
1499 };
1500 
1501 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1502 	.dev_ctx	= MFC_CTX_BUF_SIZE_V8,
1503 	.h264_dec_ctx	= MFC_H264_DEC_CTX_BUF_SIZE_V8,
1504 	.other_dec_ctx	= MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1505 	.h264_enc_ctx	= MFC_H264_ENC_CTX_BUF_SIZE_V8,
1506 	.other_enc_ctx	= MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1507 };
1508 
1509 static struct s5p_mfc_buf_size buf_size_v8 = {
1510 	.fw	= MAX_FW_SIZE_V8,
1511 	.cpb	= MAX_CPB_SIZE_V8,
1512 	.priv	= &mfc_buf_size_v8,
1513 };
1514 
1515 static struct s5p_mfc_buf_align mfc_buf_align_v8 = {
1516 	.base = 0,
1517 };
1518 
1519 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1520 	.version	= MFC_VERSION_V8,
1521 	.version_bit	= MFC_V8_BIT,
1522 	.port_num	= MFC_NUM_PORTS_V8,
1523 	.buf_size	= &buf_size_v8,
1524 	.buf_align	= &mfc_buf_align_v8,
1525 	.fw_name[0]     = "s5p-mfc-v8.fw",
1526 };
1527 
1528 static const struct of_device_id exynos_mfc_match[] = {
1529 	{
1530 		.compatible = "samsung,mfc-v5",
1531 		.data = &mfc_drvdata_v5,
1532 	}, {
1533 		.compatible = "samsung,mfc-v6",
1534 		.data = &mfc_drvdata_v6,
1535 	}, {
1536 		.compatible = "samsung,mfc-v7",
1537 		.data = &mfc_drvdata_v7,
1538 	}, {
1539 		.compatible = "samsung,mfc-v8",
1540 		.data = &mfc_drvdata_v8,
1541 	},
1542 	{},
1543 };
1544 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1545 
mfc_get_drv_data(struct platform_device * pdev)1546 static void *mfc_get_drv_data(struct platform_device *pdev)
1547 {
1548 	struct s5p_mfc_variant *driver_data = NULL;
1549 	const struct of_device_id *match;
1550 
1551 	match = of_match_node(exynos_mfc_match, pdev->dev.of_node);
1552 	if (match)
1553 		driver_data = (struct s5p_mfc_variant *)match->data;
1554 
1555 	return driver_data;
1556 }
1557 
1558 static struct platform_driver s5p_mfc_driver = {
1559 	.probe		= s5p_mfc_probe,
1560 	.remove		= s5p_mfc_remove,
1561 	.driver	= {
1562 		.name	= S5P_MFC_NAME,
1563 		.pm	= &s5p_mfc_pm_ops,
1564 		.of_match_table = exynos_mfc_match,
1565 	},
1566 };
1567 
1568 module_platform_driver(s5p_mfc_driver);
1569 
1570 MODULE_LICENSE("GPL");
1571 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1572 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1573 
1574