1 /*
2 *
3 * Common boot and setup code.
4 *
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13 #define DEBUG
14
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/reboot.h>
21 #include <linux/delay.h>
22 #include <linux/initrd.h>
23 #include <linux/seq_file.h>
24 #include <linux/ioport.h>
25 #include <linux/console.h>
26 #include <linux/utsname.h>
27 #include <linux/tty.h>
28 #include <linux/root_dev.h>
29 #include <linux/notifier.h>
30 #include <linux/cpu.h>
31 #include <linux/unistd.h>
32 #include <linux/serial.h>
33 #include <linux/serial_8250.h>
34 #include <linux/bootmem.h>
35 #include <linux/pci.h>
36 #include <linux/lockdep.h>
37 #include <linux/memblock.h>
38 #include <linux/memory.h>
39 #include <linux/nmi.h>
40 #include <linux/debugfs.h>
41
42 #include <asm/io.h>
43 #include <asm/kdump.h>
44 #include <asm/prom.h>
45 #include <asm/processor.h>
46 #include <asm/pgtable.h>
47 #include <asm/smp.h>
48 #include <asm/elf.h>
49 #include <asm/machdep.h>
50 #include <asm/paca.h>
51 #include <asm/time.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
54 #include <asm/btext.h>
55 #include <asm/nvram.h>
56 #include <asm/setup.h>
57 #include <asm/rtas.h>
58 #include <asm/iommu.h>
59 #include <asm/serial.h>
60 #include <asm/cache.h>
61 #include <asm/page.h>
62 #include <asm/mmu.h>
63 #include <asm/firmware.h>
64 #include <asm/xmon.h>
65 #include <asm/udbg.h>
66 #include <asm/kexec.h>
67 #include <asm/code-patching.h>
68 #include <asm/livepatch.h>
69 #include <asm/opal.h>
70 #include <asm/cputhreads.h>
71
72 #ifdef DEBUG
73 #define DBG(fmt...) udbg_printf(fmt)
74 #else
75 #define DBG(fmt...)
76 #endif
77
78 int spinning_secondaries;
79 u64 ppc64_pft_size;
80
81 /* Pick defaults since we might want to patch instructions
82 * before we've read this from the device tree.
83 */
84 struct ppc64_caches ppc64_caches = {
85 .dline_size = 0x40,
86 .log_dline_size = 6,
87 .iline_size = 0x40,
88 .log_iline_size = 6
89 };
90 EXPORT_SYMBOL_GPL(ppc64_caches);
91
92 /*
93 * These are used in binfmt_elf.c to put aux entries on the stack
94 * for each elf executable being started.
95 */
96 int dcache_bsize;
97 int icache_bsize;
98 int ucache_bsize;
99
100 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
setup_tlb_core_data(void)101 void __init setup_tlb_core_data(void)
102 {
103 int cpu;
104
105 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
106
107 for_each_possible_cpu(cpu) {
108 int first = cpu_first_thread_sibling(cpu);
109
110 /*
111 * If we boot via kdump on a non-primary thread,
112 * make sure we point at the thread that actually
113 * set up this TLB.
114 */
115 if (cpu_first_thread_sibling(boot_cpuid) == first)
116 first = boot_cpuid;
117
118 paca[cpu].tcd_ptr = &paca[first].tcd;
119
120 /*
121 * If we have threads, we need either tlbsrx.
122 * or e6500 tablewalk mode, or else TLB handlers
123 * will be racy and could produce duplicate entries.
124 */
125 if (smt_enabled_at_boot >= 2 &&
126 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
127 book3e_htw_mode != PPC_HTW_E6500) {
128 /* Should we panic instead? */
129 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
130 __func__);
131 }
132 }
133 }
134 #endif
135
136 #ifdef CONFIG_SMP
137
138 static char *smt_enabled_cmdline;
139
140 /* Look for ibm,smt-enabled OF option */
check_smt_enabled(void)141 void __init check_smt_enabled(void)
142 {
143 struct device_node *dn;
144 const char *smt_option;
145
146 /* Default to enabling all threads */
147 smt_enabled_at_boot = threads_per_core;
148
149 /* Allow the command line to overrule the OF option */
150 if (smt_enabled_cmdline) {
151 if (!strcmp(smt_enabled_cmdline, "on"))
152 smt_enabled_at_boot = threads_per_core;
153 else if (!strcmp(smt_enabled_cmdline, "off"))
154 smt_enabled_at_boot = 0;
155 else {
156 int smt;
157 int rc;
158
159 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
160 if (!rc)
161 smt_enabled_at_boot =
162 min(threads_per_core, smt);
163 }
164 } else {
165 dn = of_find_node_by_path("/options");
166 if (dn) {
167 smt_option = of_get_property(dn, "ibm,smt-enabled",
168 NULL);
169
170 if (smt_option) {
171 if (!strcmp(smt_option, "on"))
172 smt_enabled_at_boot = threads_per_core;
173 else if (!strcmp(smt_option, "off"))
174 smt_enabled_at_boot = 0;
175 }
176
177 of_node_put(dn);
178 }
179 }
180 }
181
182 /* Look for smt-enabled= cmdline option */
early_smt_enabled(char * p)183 static int __init early_smt_enabled(char *p)
184 {
185 smt_enabled_cmdline = p;
186 return 0;
187 }
188 early_param("smt-enabled", early_smt_enabled);
189
190 #endif /* CONFIG_SMP */
191
192 /** Fix up paca fields required for the boot cpu */
fixup_boot_paca(void)193 static void __init fixup_boot_paca(void)
194 {
195 /* The boot cpu is started */
196 get_paca()->cpu_start = 1;
197 /* Allow percpu accesses to work until we setup percpu data */
198 get_paca()->data_offset = 0;
199 }
200
configure_exceptions(void)201 static void __init configure_exceptions(void)
202 {
203 /*
204 * Setup the trampolines from the lowmem exception vectors
205 * to the kdump kernel when not using a relocatable kernel.
206 */
207 setup_kdump_trampoline();
208
209 /* Under a PAPR hypervisor, we need hypercalls */
210 if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
211 /* Enable AIL if possible */
212 pseries_enable_reloc_on_exc();
213
214 /*
215 * Tell the hypervisor that we want our exceptions to
216 * be taken in little endian mode.
217 *
218 * We don't call this for big endian as our calling convention
219 * makes us always enter in BE, and the call may fail under
220 * some circumstances with kdump.
221 */
222 #ifdef __LITTLE_ENDIAN__
223 pseries_little_endian_exceptions();
224 #endif
225 } else {
226 /* Set endian mode using OPAL */
227 if (firmware_has_feature(FW_FEATURE_OPAL))
228 opal_configure_cores();
229
230 /* AIL on native is done in cpu_ready_for_interrupts() */
231 }
232 }
233
cpu_ready_for_interrupts(void)234 static void cpu_ready_for_interrupts(void)
235 {
236 /*
237 * Enable AIL if supported, and we are in hypervisor mode. This
238 * is called once for every processor.
239 *
240 * If we are not in hypervisor mode the job is done once for
241 * the whole partition in configure_exceptions().
242 */
243 if (early_cpu_has_feature(CPU_FTR_HVMODE) &&
244 early_cpu_has_feature(CPU_FTR_ARCH_207S)) {
245 unsigned long lpcr = mfspr(SPRN_LPCR);
246 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
247 }
248
249 /*
250 * Fixup HFSCR:TM based on CPU features. The bit is set by our
251 * early asm init because at that point we haven't updated our
252 * CPU features from firmware and device-tree. Here we have,
253 * so let's do it.
254 */
255 if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP))
256 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
257
258 /* Set IR and DR in PACA MSR */
259 get_paca()->kernel_msr = MSR_KERNEL;
260 }
261
262 /*
263 * Early initialization entry point. This is called by head.S
264 * with MMU translation disabled. We rely on the "feature" of
265 * the CPU that ignores the top 2 bits of the address in real
266 * mode so we can access kernel globals normally provided we
267 * only toy with things in the RMO region. From here, we do
268 * some early parsing of the device-tree to setup out MEMBLOCK
269 * data structures, and allocate & initialize the hash table
270 * and segment tables so we can start running with translation
271 * enabled.
272 *
273 * It is this function which will call the probe() callback of
274 * the various platform types and copy the matching one to the
275 * global ppc_md structure. Your platform can eventually do
276 * some very early initializations from the probe() routine, but
277 * this is not recommended, be very careful as, for example, the
278 * device-tree is not accessible via normal means at this point.
279 */
280
early_setup(unsigned long dt_ptr)281 void __init early_setup(unsigned long dt_ptr)
282 {
283 static __initdata struct paca_struct boot_paca;
284
285 /* -------- printk is _NOT_ safe to use here ! ------- */
286
287 /* Identify CPU type */
288 identify_cpu(0, mfspr(SPRN_PVR));
289
290 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
291 initialise_paca(&boot_paca, 0);
292 setup_paca(&boot_paca);
293 fixup_boot_paca();
294
295 /* -------- printk is now safe to use ------- */
296
297 /* Enable early debugging if any specified (see udbg.h) */
298 udbg_early_init();
299
300 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
301
302 /*
303 * Do early initialization using the flattened device
304 * tree, such as retrieving the physical memory map or
305 * calculating/retrieving the hash table size.
306 */
307 early_init_devtree(__va(dt_ptr));
308
309 /* Now we know the logical id of our boot cpu, setup the paca. */
310 setup_paca(&paca[boot_cpuid]);
311 fixup_boot_paca();
312
313 /*
314 * Configure exception handlers. This include setting up trampolines
315 * if needed, setting exception endian mode, etc...
316 */
317 configure_exceptions();
318
319 /* Apply all the dynamic patching */
320 apply_feature_fixups();
321 setup_feature_keys();
322
323 /* Initialize the hash table or TLB handling */
324 early_init_mmu();
325
326 /*
327 * At this point, we can let interrupts switch to virtual mode
328 * (the MMU has been setup), so adjust the MSR in the PACA to
329 * have IR and DR set and enable AIL if it exists
330 */
331 cpu_ready_for_interrupts();
332
333 DBG(" <- early_setup()\n");
334
335 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
336 /*
337 * This needs to be done *last* (after the above DBG() even)
338 *
339 * Right after we return from this function, we turn on the MMU
340 * which means the real-mode access trick that btext does will
341 * no longer work, it needs to switch to using a real MMU
342 * mapping. This call will ensure that it does
343 */
344 btext_map();
345 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
346 }
347
348 #ifdef CONFIG_SMP
early_setup_secondary(void)349 void early_setup_secondary(void)
350 {
351 /* Mark interrupts disabled in PACA */
352 get_paca()->soft_enabled = 0;
353
354 /* Initialize the hash table or TLB handling */
355 early_init_mmu_secondary();
356
357 /*
358 * At this point, we can let interrupts switch to virtual mode
359 * (the MMU has been setup), so adjust the MSR in the PACA to
360 * have IR and DR set.
361 */
362 cpu_ready_for_interrupts();
363 }
364
365 #endif /* CONFIG_SMP */
366
367 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
use_spinloop(void)368 static bool use_spinloop(void)
369 {
370 if (!IS_ENABLED(CONFIG_PPC_BOOK3E))
371 return true;
372
373 /*
374 * When book3e boots from kexec, the ePAPR spin table does
375 * not get used.
376 */
377 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
378 }
379
smp_release_cpus(void)380 void smp_release_cpus(void)
381 {
382 unsigned long *ptr;
383 int i;
384
385 if (!use_spinloop())
386 return;
387
388 DBG(" -> smp_release_cpus()\n");
389
390 /* All secondary cpus are spinning on a common spinloop, release them
391 * all now so they can start to spin on their individual paca
392 * spinloops. For non SMP kernels, the secondary cpus never get out
393 * of the common spinloop.
394 */
395
396 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
397 - PHYSICAL_START);
398 *ptr = ppc_function_entry(generic_secondary_smp_init);
399
400 /* And wait a bit for them to catch up */
401 for (i = 0; i < 100000; i++) {
402 mb();
403 HMT_low();
404 if (spinning_secondaries == 0)
405 break;
406 udelay(1);
407 }
408 DBG("spinning_secondaries = %d\n", spinning_secondaries);
409
410 DBG(" <- smp_release_cpus()\n");
411 }
412 #endif /* CONFIG_SMP || CONFIG_KEXEC */
413
414 /*
415 * Initialize some remaining members of the ppc64_caches and systemcfg
416 * structures
417 * (at least until we get rid of them completely). This is mostly some
418 * cache informations about the CPU that will be used by cache flush
419 * routines and/or provided to userland
420 */
initialize_cache_info(void)421 void __init initialize_cache_info(void)
422 {
423 struct device_node *np;
424 unsigned long num_cpus = 0;
425
426 DBG(" -> initialize_cache_info()\n");
427
428 for_each_node_by_type(np, "cpu") {
429 num_cpus += 1;
430
431 /*
432 * We're assuming *all* of the CPUs have the same
433 * d-cache and i-cache sizes... -Peter
434 */
435 if (num_cpus == 1) {
436 const __be32 *sizep, *lsizep;
437 u32 size, lsize;
438
439 size = 0;
440 lsize = cur_cpu_spec->dcache_bsize;
441 sizep = of_get_property(np, "d-cache-size", NULL);
442 if (sizep != NULL)
443 size = be32_to_cpu(*sizep);
444 lsizep = of_get_property(np, "d-cache-block-size",
445 NULL);
446 /* fallback if block size missing */
447 if (lsizep == NULL)
448 lsizep = of_get_property(np,
449 "d-cache-line-size",
450 NULL);
451 if (lsizep != NULL)
452 lsize = be32_to_cpu(*lsizep);
453 if (sizep == NULL || lsizep == NULL)
454 DBG("Argh, can't find dcache properties ! "
455 "sizep: %p, lsizep: %p\n", sizep, lsizep);
456
457 ppc64_caches.dsize = size;
458 ppc64_caches.dline_size = lsize;
459 ppc64_caches.log_dline_size = __ilog2(lsize);
460 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize;
461
462 size = 0;
463 lsize = cur_cpu_spec->icache_bsize;
464 sizep = of_get_property(np, "i-cache-size", NULL);
465 if (sizep != NULL)
466 size = be32_to_cpu(*sizep);
467 lsizep = of_get_property(np, "i-cache-block-size",
468 NULL);
469 if (lsizep == NULL)
470 lsizep = of_get_property(np,
471 "i-cache-line-size",
472 NULL);
473 if (lsizep != NULL)
474 lsize = be32_to_cpu(*lsizep);
475 if (sizep == NULL || lsizep == NULL)
476 DBG("Argh, can't find icache properties ! "
477 "sizep: %p, lsizep: %p\n", sizep, lsizep);
478
479 ppc64_caches.isize = size;
480 ppc64_caches.iline_size = lsize;
481 ppc64_caches.log_iline_size = __ilog2(lsize);
482 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize;
483 }
484 }
485
486 /* For use by binfmt_elf */
487 dcache_bsize = ppc64_caches.dline_size;
488 icache_bsize = ppc64_caches.iline_size;
489
490 DBG(" <- initialize_cache_info()\n");
491 }
492
493 /* This returns the limit below which memory accesses to the linear
494 * mapping are guarnateed not to cause a TLB or SLB miss. This is
495 * used to allocate interrupt or emergency stacks for which our
496 * exception entry path doesn't deal with being interrupted.
497 */
safe_stack_limit(void)498 static __init u64 safe_stack_limit(void)
499 {
500 #ifdef CONFIG_PPC_BOOK3E
501 /* Freescale BookE bolts the entire linear mapping */
502 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
503 return linear_map_top;
504 /* Other BookE, we assume the first GB is bolted */
505 return 1ul << 30;
506 #else
507 /* BookS, the first segment is bolted */
508 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
509 return 1UL << SID_SHIFT_1T;
510 return 1UL << SID_SHIFT;
511 #endif
512 }
513
irqstack_early_init(void)514 void __init irqstack_early_init(void)
515 {
516 u64 limit = safe_stack_limit();
517 unsigned int i;
518
519 /*
520 * Interrupt stacks must be in the first segment since we
521 * cannot afford to take SLB misses on them.
522 */
523 for_each_possible_cpu(i) {
524 softirq_ctx[i] = (struct thread_info *)
525 __va(memblock_alloc_base(THREAD_SIZE,
526 THREAD_SIZE, limit));
527 hardirq_ctx[i] = (struct thread_info *)
528 __va(memblock_alloc_base(THREAD_SIZE,
529 THREAD_SIZE, limit));
530 }
531 }
532
533 #ifdef CONFIG_PPC_BOOK3E
exc_lvl_early_init(void)534 void __init exc_lvl_early_init(void)
535 {
536 unsigned int i;
537 unsigned long sp;
538
539 for_each_possible_cpu(i) {
540 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
541 critirq_ctx[i] = (struct thread_info *)__va(sp);
542 paca[i].crit_kstack = __va(sp + THREAD_SIZE);
543
544 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
545 dbgirq_ctx[i] = (struct thread_info *)__va(sp);
546 paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
547
548 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
549 mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
550 paca[i].mc_kstack = __va(sp + THREAD_SIZE);
551 }
552
553 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
554 patch_exception(0x040, exc_debug_debug_book3e);
555 }
556 #endif
557
558 /*
559 * Stack space used when we detect a bad kernel stack pointer, and
560 * early in SMP boots before relocation is enabled. Exclusive emergency
561 * stack for machine checks.
562 */
emergency_stack_init(void)563 void __init emergency_stack_init(void)
564 {
565 u64 limit;
566 unsigned int i;
567
568 /*
569 * Emergency stacks must be under 256MB, we cannot afford to take
570 * SLB misses on them. The ABI also requires them to be 128-byte
571 * aligned.
572 *
573 * Since we use these as temporary stacks during secondary CPU
574 * bringup, we need to get at them in real mode. This means they
575 * must also be within the RMO region.
576 */
577 limit = min(safe_stack_limit(), ppc64_rma_size);
578
579 for_each_possible_cpu(i) {
580 struct thread_info *ti;
581 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
582 klp_init_thread_info(ti);
583 paca[i].emergency_sp = (void *)ti + THREAD_SIZE;
584
585 #ifdef CONFIG_PPC_BOOK3S_64
586 /* emergency stack for machine check exception handling. */
587 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
588 klp_init_thread_info(ti);
589 paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE;
590 #endif
591 }
592 }
593
594 #ifdef CONFIG_SMP
595 #define PCPU_DYN_SIZE ()
596
pcpu_fc_alloc(unsigned int cpu,size_t size,size_t align)597 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
598 {
599 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
600 __pa(MAX_DMA_ADDRESS));
601 }
602
pcpu_fc_free(void * ptr,size_t size)603 static void __init pcpu_fc_free(void *ptr, size_t size)
604 {
605 free_bootmem(__pa(ptr), size);
606 }
607
pcpu_cpu_distance(unsigned int from,unsigned int to)608 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
609 {
610 if (cpu_to_node(from) == cpu_to_node(to))
611 return LOCAL_DISTANCE;
612 else
613 return REMOTE_DISTANCE;
614 }
615
616 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
617 EXPORT_SYMBOL(__per_cpu_offset);
618
setup_per_cpu_areas(void)619 void __init setup_per_cpu_areas(void)
620 {
621 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
622 size_t atom_size;
623 unsigned long delta;
624 unsigned int cpu;
625 int rc;
626
627 /*
628 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
629 * to group units. For larger mappings, use 1M atom which
630 * should be large enough to contain a number of units.
631 */
632 if (mmu_linear_psize == MMU_PAGE_4K)
633 atom_size = PAGE_SIZE;
634 else
635 atom_size = 1 << 20;
636
637 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
638 pcpu_fc_alloc, pcpu_fc_free);
639 if (rc < 0)
640 panic("cannot initialize percpu area (err=%d)", rc);
641
642 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
643 for_each_possible_cpu(cpu) {
644 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
645 paca[cpu].data_offset = __per_cpu_offset[cpu];
646 }
647 }
648 #endif
649
650 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
memory_block_size_bytes(void)651 unsigned long memory_block_size_bytes(void)
652 {
653 if (ppc_md.memory_block_size)
654 return ppc_md.memory_block_size();
655
656 return MIN_MEMORY_BLOCK_SIZE;
657 }
658 #endif
659
660 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
661 struct ppc_pci_io ppc_pci_io;
662 EXPORT_SYMBOL(ppc_pci_io);
663 #endif
664
665 #ifdef CONFIG_HARDLOCKUP_DETECTOR
hw_nmi_get_sample_period(int watchdog_thresh)666 u64 hw_nmi_get_sample_period(int watchdog_thresh)
667 {
668 return ppc_proc_freq * watchdog_thresh;
669 }
670
671 /*
672 * The hardlockup detector breaks PMU event based branches and is likely
673 * to get false positives in KVM guests, so disable it by default.
674 */
disable_hardlockup_detector(void)675 static int __init disable_hardlockup_detector(void)
676 {
677 hardlockup_detector_disable();
678
679 return 0;
680 }
681 early_initcall(disable_hardlockup_detector);
682
683 #ifdef CONFIG_PPC_BOOK3S_64
684 static enum l1d_flush_type enabled_flush_types;
685 static void *l1d_flush_fallback_area;
686 static bool no_rfi_flush;
687 bool rfi_flush;
688
handle_no_rfi_flush(char * p)689 static int __init handle_no_rfi_flush(char *p)
690 {
691 pr_info("rfi-flush: disabled on command line.");
692 no_rfi_flush = true;
693 return 0;
694 }
695 early_param("no_rfi_flush", handle_no_rfi_flush);
696
697 /*
698 * The RFI flush is not KPTI, but because users will see doco that says to use
699 * nopti we hijack that option here to also disable the RFI flush.
700 */
handle_no_pti(char * p)701 static int __init handle_no_pti(char *p)
702 {
703 pr_info("rfi-flush: disabling due to 'nopti' on command line.\n");
704 handle_no_rfi_flush(NULL);
705 return 0;
706 }
707 early_param("nopti", handle_no_pti);
708
do_nothing(void * unused)709 static void do_nothing(void *unused)
710 {
711 /*
712 * We don't need to do the flush explicitly, just enter+exit kernel is
713 * sufficient, the RFI exit handlers will do the right thing.
714 */
715 }
716
rfi_flush_enable(bool enable)717 void rfi_flush_enable(bool enable)
718 {
719 if (rfi_flush == enable)
720 return;
721
722 if (enable) {
723 do_rfi_flush_fixups(enabled_flush_types);
724 on_each_cpu(do_nothing, NULL, 1);
725 } else
726 do_rfi_flush_fixups(L1D_FLUSH_NONE);
727
728 rfi_flush = enable;
729 }
730
init_fallback_flush(void)731 static void init_fallback_flush(void)
732 {
733 u64 l1d_size, limit;
734 int cpu;
735
736 l1d_size = ppc64_caches.dsize;
737 limit = min(safe_stack_limit(), ppc64_rma_size);
738
739 /*
740 * Align to L1d size, and size it at 2x L1d size, to catch possible
741 * hardware prefetch runoff. We don't have a recipe for load patterns to
742 * reliably avoid the prefetcher.
743 */
744 l1d_flush_fallback_area = __va(memblock_alloc_base(l1d_size * 2, l1d_size, limit));
745 memset(l1d_flush_fallback_area, 0, l1d_size * 2);
746
747 for_each_possible_cpu(cpu) {
748 paca[cpu].rfi_flush_fallback_area = l1d_flush_fallback_area;
749 paca[cpu].l1d_flush_size = l1d_size;
750 }
751 }
752
setup_rfi_flush(enum l1d_flush_type types,bool enable)753 void __init setup_rfi_flush(enum l1d_flush_type types, bool enable)
754 {
755 if (types & L1D_FLUSH_FALLBACK) {
756 pr_info("rfi-flush: Using fallback displacement flush\n");
757 init_fallback_flush();
758 }
759
760 if (types & L1D_FLUSH_ORI)
761 pr_info("rfi-flush: Using ori type flush\n");
762
763 if (types & L1D_FLUSH_MTTRIG)
764 pr_info("rfi-flush: Using mttrig type flush\n");
765
766 enabled_flush_types = types;
767
768 if (!no_rfi_flush)
769 rfi_flush_enable(enable);
770 }
771
772 #ifdef CONFIG_DEBUG_FS
rfi_flush_set(void * data,u64 val)773 static int rfi_flush_set(void *data, u64 val)
774 {
775 if (val == 1)
776 rfi_flush_enable(true);
777 else if (val == 0)
778 rfi_flush_enable(false);
779 else
780 return -EINVAL;
781
782 return 0;
783 }
784
rfi_flush_get(void * data,u64 * val)785 static int rfi_flush_get(void *data, u64 *val)
786 {
787 *val = rfi_flush ? 1 : 0;
788 return 0;
789 }
790
791 DEFINE_SIMPLE_ATTRIBUTE(fops_rfi_flush, rfi_flush_get, rfi_flush_set, "%llu\n");
792
rfi_flush_debugfs_init(void)793 static __init int rfi_flush_debugfs_init(void)
794 {
795 debugfs_create_file("rfi_flush", 0600, powerpc_debugfs_root, NULL, &fops_rfi_flush);
796 return 0;
797 }
798 device_initcall(rfi_flush_debugfs_init);
799 #endif
800
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)801 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
802 {
803 if (rfi_flush)
804 return sprintf(buf, "Mitigation: RFI Flush\n");
805
806 return sprintf(buf, "Vulnerable\n");
807 }
808 #endif /* CONFIG_PPC_BOOK3S_64 */
809 #endif
810