1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
38
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_ttm.h"
55 #include "amdgpu_gds.h"
56 #include "amd_powerplay.h"
57 #include "amdgpu_acp.h"
58
59 #include "gpu_scheduler.h"
60 #include "amdgpu_virt.h"
61
62 /*
63 * Modules parameters.
64 */
65 extern int amdgpu_modeset;
66 extern int amdgpu_vram_limit;
67 extern int amdgpu_gart_size;
68 extern int amdgpu_moverate;
69 extern int amdgpu_benchmarking;
70 extern int amdgpu_testing;
71 extern int amdgpu_audio;
72 extern int amdgpu_disp_priority;
73 extern int amdgpu_hw_i2c;
74 extern int amdgpu_pcie_gen2;
75 extern int amdgpu_msi;
76 extern int amdgpu_lockup_timeout;
77 extern int amdgpu_dpm;
78 extern int amdgpu_smc_load_fw;
79 extern int amdgpu_aspm;
80 extern int amdgpu_runtime_pm;
81 extern unsigned amdgpu_ip_block_mask;
82 extern int amdgpu_bapm;
83 extern int amdgpu_deep_color;
84 extern int amdgpu_vm_size;
85 extern int amdgpu_vm_block_size;
86 extern int amdgpu_vm_fault_stop;
87 extern int amdgpu_vm_debug;
88 extern int amdgpu_sched_jobs;
89 extern int amdgpu_sched_hw_submission;
90 extern int amdgpu_powerplay;
91 extern int amdgpu_powercontainment;
92 extern unsigned amdgpu_pcie_gen_cap;
93 extern unsigned amdgpu_pcie_lane_cap;
94 extern unsigned amdgpu_cg_mask;
95 extern unsigned amdgpu_pg_mask;
96 extern char *amdgpu_disable_cu;
97 extern int amdgpu_sclk_deep_sleep_en;
98 extern char *amdgpu_virtual_display;
99 extern unsigned amdgpu_pp_feature_mask;
100
101 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
102 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
103 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
104 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
105 #define AMDGPU_IB_POOL_SIZE 16
106 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
107 #define AMDGPUFB_CONN_LIMIT 4
108 #define AMDGPU_BIOS_NUM_SCRATCH 8
109
110 /* max number of rings */
111 #define AMDGPU_MAX_RINGS 16
112 #define AMDGPU_MAX_GFX_RINGS 1
113 #define AMDGPU_MAX_COMPUTE_RINGS 8
114 #define AMDGPU_MAX_VCE_RINGS 3
115
116 /* max number of IP instances */
117 #define AMDGPU_MAX_SDMA_INSTANCES 2
118
119 /* hardcode that limit for now */
120 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
121
122 /* hard reset data */
123 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
124
125 /* reset flags */
126 #define AMDGPU_RESET_GFX (1 << 0)
127 #define AMDGPU_RESET_COMPUTE (1 << 1)
128 #define AMDGPU_RESET_DMA (1 << 2)
129 #define AMDGPU_RESET_CP (1 << 3)
130 #define AMDGPU_RESET_GRBM (1 << 4)
131 #define AMDGPU_RESET_DMA1 (1 << 5)
132 #define AMDGPU_RESET_RLC (1 << 6)
133 #define AMDGPU_RESET_SEM (1 << 7)
134 #define AMDGPU_RESET_IH (1 << 8)
135 #define AMDGPU_RESET_VMC (1 << 9)
136 #define AMDGPU_RESET_MC (1 << 10)
137 #define AMDGPU_RESET_DISPLAY (1 << 11)
138 #define AMDGPU_RESET_UVD (1 << 12)
139 #define AMDGPU_RESET_VCE (1 << 13)
140 #define AMDGPU_RESET_VCE1 (1 << 14)
141
142 /* GFX current status */
143 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
144 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
145 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
146 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
147 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
148
149 /* max cursor sizes (in pixels) */
150 #define CIK_CURSOR_WIDTH 128
151 #define CIK_CURSOR_HEIGHT 128
152
153 struct amdgpu_device;
154 struct amdgpu_ib;
155 struct amdgpu_vm;
156 struct amdgpu_ring;
157 struct amdgpu_cs_parser;
158 struct amdgpu_job;
159 struct amdgpu_irq_src;
160 struct amdgpu_fpriv;
161
162 enum amdgpu_cp_irq {
163 AMDGPU_CP_IRQ_GFX_EOP = 0,
164 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
165 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
166 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
167 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
168 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
169 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
170 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
171 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
172
173 AMDGPU_CP_IRQ_LAST
174 };
175
176 enum amdgpu_sdma_irq {
177 AMDGPU_SDMA_IRQ_TRAP0 = 0,
178 AMDGPU_SDMA_IRQ_TRAP1,
179
180 AMDGPU_SDMA_IRQ_LAST
181 };
182
183 enum amdgpu_thermal_irq {
184 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
185 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
186
187 AMDGPU_THERMAL_IRQ_LAST
188 };
189
190 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
191 enum amd_ip_block_type block_type,
192 enum amd_clockgating_state state);
193 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
194 enum amd_ip_block_type block_type,
195 enum amd_powergating_state state);
196 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
197 enum amd_ip_block_type block_type);
198 bool amdgpu_is_idle(struct amdgpu_device *adev,
199 enum amd_ip_block_type block_type);
200
201 struct amdgpu_ip_block_version {
202 enum amd_ip_block_type type;
203 u32 major;
204 u32 minor;
205 u32 rev;
206 const struct amd_ip_funcs *funcs;
207 };
208
209 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
210 enum amd_ip_block_type type,
211 u32 major, u32 minor);
212
213 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
214 struct amdgpu_device *adev,
215 enum amd_ip_block_type type);
216
217 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
218 struct amdgpu_buffer_funcs {
219 /* maximum bytes in a single operation */
220 uint32_t copy_max_bytes;
221
222 /* number of dw to reserve per operation */
223 unsigned copy_num_dw;
224
225 /* used for buffer migration */
226 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
227 /* src addr in bytes */
228 uint64_t src_offset,
229 /* dst addr in bytes */
230 uint64_t dst_offset,
231 /* number of byte to transfer */
232 uint32_t byte_count);
233
234 /* maximum bytes in a single operation */
235 uint32_t fill_max_bytes;
236
237 /* number of dw to reserve per operation */
238 unsigned fill_num_dw;
239
240 /* used for buffer clearing */
241 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
242 /* value to write to memory */
243 uint32_t src_data,
244 /* dst addr in bytes */
245 uint64_t dst_offset,
246 /* number of byte to fill */
247 uint32_t byte_count);
248 };
249
250 /* provided by hw blocks that can write ptes, e.g., sdma */
251 struct amdgpu_vm_pte_funcs {
252 /* copy pte entries from GART */
253 void (*copy_pte)(struct amdgpu_ib *ib,
254 uint64_t pe, uint64_t src,
255 unsigned count);
256 /* write pte one entry at a time with addr mapping */
257 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
258 uint64_t value, unsigned count,
259 uint32_t incr);
260 /* for linear pte/pde updates without addr mapping */
261 void (*set_pte_pde)(struct amdgpu_ib *ib,
262 uint64_t pe,
263 uint64_t addr, unsigned count,
264 uint32_t incr, uint32_t flags);
265 };
266
267 /* provided by the gmc block */
268 struct amdgpu_gart_funcs {
269 /* flush the vm tlb via mmio */
270 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
271 uint32_t vmid);
272 /* write pte/pde updates using the cpu */
273 int (*set_pte_pde)(struct amdgpu_device *adev,
274 void *cpu_pt_addr, /* cpu addr of page table */
275 uint32_t gpu_page_idx, /* pte/pde to update */
276 uint64_t addr, /* addr to write into pte/pde */
277 uint32_t flags); /* access flags */
278 };
279
280 /* provided by the ih block */
281 struct amdgpu_ih_funcs {
282 /* ring read/write ptr handling, called from interrupt context */
283 u32 (*get_wptr)(struct amdgpu_device *adev);
284 void (*decode_iv)(struct amdgpu_device *adev,
285 struct amdgpu_iv_entry *entry);
286 void (*set_rptr)(struct amdgpu_device *adev);
287 };
288
289 /* provided by hw blocks that expose a ring buffer for commands */
290 struct amdgpu_ring_funcs {
291 /* ring read/write ptr handling */
292 u32 (*get_rptr)(struct amdgpu_ring *ring);
293 u32 (*get_wptr)(struct amdgpu_ring *ring);
294 void (*set_wptr)(struct amdgpu_ring *ring);
295 /* validating and patching of IBs */
296 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
297 /* command emit functions */
298 void (*emit_ib)(struct amdgpu_ring *ring,
299 struct amdgpu_ib *ib,
300 unsigned vm_id, bool ctx_switch);
301 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
302 uint64_t seq, unsigned flags);
303 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
304 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
305 uint64_t pd_addr);
306 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
307 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
308 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
309 uint32_t gds_base, uint32_t gds_size,
310 uint32_t gws_base, uint32_t gws_size,
311 uint32_t oa_base, uint32_t oa_size);
312 /* testing functions */
313 int (*test_ring)(struct amdgpu_ring *ring);
314 int (*test_ib)(struct amdgpu_ring *ring, long timeout);
315 /* insert NOP packets */
316 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
317 /* pad the indirect buffer to the necessary number of dw */
318 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
319 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
320 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
321 /* note usage for clock and power gating */
322 void (*begin_use)(struct amdgpu_ring *ring);
323 void (*end_use)(struct amdgpu_ring *ring);
324 void (*emit_switch_buffer) (struct amdgpu_ring *ring);
325 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
326 unsigned (*get_emit_ib_size) (struct amdgpu_ring *ring);
327 unsigned (*get_dma_frame_size) (struct amdgpu_ring *ring);
328 };
329
330 /*
331 * BIOS.
332 */
333 bool amdgpu_get_bios(struct amdgpu_device *adev);
334 bool amdgpu_read_bios(struct amdgpu_device *adev);
335
336 /*
337 * Dummy page
338 */
339 struct amdgpu_dummy_page {
340 struct page *page;
341 dma_addr_t addr;
342 };
343 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
344 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
345
346
347 /*
348 * Clocks
349 */
350
351 #define AMDGPU_MAX_PPLL 3
352
353 struct amdgpu_clock {
354 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
355 struct amdgpu_pll spll;
356 struct amdgpu_pll mpll;
357 /* 10 Khz units */
358 uint32_t default_mclk;
359 uint32_t default_sclk;
360 uint32_t default_dispclk;
361 uint32_t current_dispclk;
362 uint32_t dp_extclk;
363 uint32_t max_pixel_clock;
364 };
365
366 /*
367 * Fences.
368 */
369 struct amdgpu_fence_driver {
370 uint64_t gpu_addr;
371 volatile uint32_t *cpu_addr;
372 /* sync_seq is protected by ring emission lock */
373 uint32_t sync_seq;
374 atomic_t last_seq;
375 bool initialized;
376 struct amdgpu_irq_src *irq_src;
377 unsigned irq_type;
378 struct timer_list fallback_timer;
379 unsigned num_fences_mask;
380 spinlock_t lock;
381 struct fence **fences;
382 };
383
384 /* some special values for the owner field */
385 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
386 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
387
388 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
389 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
390
391 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
392 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
393 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
394
395 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
396 unsigned num_hw_submission);
397 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
398 struct amdgpu_irq_src *irq_src,
399 unsigned irq_type);
400 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
401 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
402 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
403 void amdgpu_fence_process(struct amdgpu_ring *ring);
404 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
405 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
406
407 /*
408 * BO.
409 */
410 struct amdgpu_bo_list_entry {
411 struct amdgpu_bo *robj;
412 struct ttm_validate_buffer tv;
413 struct amdgpu_bo_va *bo_va;
414 uint32_t priority;
415 struct page **user_pages;
416 int user_invalidated;
417 };
418
419 struct amdgpu_bo_va_mapping {
420 struct list_head list;
421 struct interval_tree_node it;
422 uint64_t offset;
423 uint32_t flags;
424 };
425
426 /* bo virtual addresses in a specific vm */
427 struct amdgpu_bo_va {
428 /* protected by bo being reserved */
429 struct list_head bo_list;
430 struct fence *last_pt_update;
431 unsigned ref_count;
432
433 /* protected by vm mutex and spinlock */
434 struct list_head vm_status;
435
436 /* mappings for this bo_va */
437 struct list_head invalids;
438 struct list_head valids;
439
440 /* constant after initialization */
441 struct amdgpu_vm *vm;
442 struct amdgpu_bo *bo;
443 };
444
445 #define AMDGPU_GEM_DOMAIN_MAX 0x3
446
447 struct amdgpu_bo {
448 /* Protected by tbo.reserved */
449 u32 prefered_domains;
450 u32 allowed_domains;
451 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
452 struct ttm_placement placement;
453 struct ttm_buffer_object tbo;
454 struct ttm_bo_kmap_obj kmap;
455 u64 flags;
456 unsigned pin_count;
457 void *kptr;
458 u64 tiling_flags;
459 u64 metadata_flags;
460 void *metadata;
461 u32 metadata_size;
462 unsigned prime_shared_count;
463 /* list of all virtual address to which this bo
464 * is associated to
465 */
466 struct list_head va;
467 /* Constant after initialization */
468 struct amdgpu_device *adev;
469 struct drm_gem_object gem_base;
470 struct amdgpu_bo *parent;
471 struct amdgpu_bo *shadow;
472
473 struct ttm_bo_kmap_obj dma_buf_vmap;
474 struct amdgpu_mn *mn;
475 struct list_head mn_list;
476 struct list_head shadow_list;
477 };
478 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
479
480 void amdgpu_gem_object_free(struct drm_gem_object *obj);
481 int amdgpu_gem_object_open(struct drm_gem_object *obj,
482 struct drm_file *file_priv);
483 void amdgpu_gem_object_close(struct drm_gem_object *obj,
484 struct drm_file *file_priv);
485 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
486 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
487 struct drm_gem_object *
488 amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
489 struct dma_buf_attachment *attach,
490 struct sg_table *sg);
491 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
492 struct drm_gem_object *gobj,
493 int flags);
494 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
495 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
496 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
497 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
498 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
499 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
500
501 /* sub-allocation manager, it has to be protected by another lock.
502 * By conception this is an helper for other part of the driver
503 * like the indirect buffer or semaphore, which both have their
504 * locking.
505 *
506 * Principe is simple, we keep a list of sub allocation in offset
507 * order (first entry has offset == 0, last entry has the highest
508 * offset).
509 *
510 * When allocating new object we first check if there is room at
511 * the end total_size - (last_object_offset + last_object_size) >=
512 * alloc_size. If so we allocate new object there.
513 *
514 * When there is not enough room at the end, we start waiting for
515 * each sub object until we reach object_offset+object_size >=
516 * alloc_size, this object then become the sub object we return.
517 *
518 * Alignment can't be bigger than page size.
519 *
520 * Hole are not considered for allocation to keep things simple.
521 * Assumption is that there won't be hole (all object on same
522 * alignment).
523 */
524
525 #define AMDGPU_SA_NUM_FENCE_LISTS 32
526
527 struct amdgpu_sa_manager {
528 wait_queue_head_t wq;
529 struct amdgpu_bo *bo;
530 struct list_head *hole;
531 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
532 struct list_head olist;
533 unsigned size;
534 uint64_t gpu_addr;
535 void *cpu_ptr;
536 uint32_t domain;
537 uint32_t align;
538 };
539
540 /* sub-allocation buffer */
541 struct amdgpu_sa_bo {
542 struct list_head olist;
543 struct list_head flist;
544 struct amdgpu_sa_manager *manager;
545 unsigned soffset;
546 unsigned eoffset;
547 struct fence *fence;
548 };
549
550 /*
551 * GEM objects.
552 */
553 void amdgpu_gem_force_release(struct amdgpu_device *adev);
554 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
555 int alignment, u32 initial_domain,
556 u64 flags, bool kernel,
557 struct drm_gem_object **obj);
558
559 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
560 struct drm_device *dev,
561 struct drm_mode_create_dumb *args);
562 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
563 struct drm_device *dev,
564 uint32_t handle, uint64_t *offset_p);
565 /*
566 * Synchronization
567 */
568 struct amdgpu_sync {
569 DECLARE_HASHTABLE(fences, 4);
570 struct fence *last_vm_update;
571 };
572
573 void amdgpu_sync_create(struct amdgpu_sync *sync);
574 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
575 struct fence *f);
576 int amdgpu_sync_resv(struct amdgpu_device *adev,
577 struct amdgpu_sync *sync,
578 struct reservation_object *resv,
579 void *owner);
580 struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
581 struct amdgpu_ring *ring);
582 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
583 void amdgpu_sync_free(struct amdgpu_sync *sync);
584 int amdgpu_sync_init(void);
585 void amdgpu_sync_fini(void);
586 int amdgpu_fence_slab_init(void);
587 void amdgpu_fence_slab_fini(void);
588
589 /*
590 * GART structures, functions & helpers
591 */
592 struct amdgpu_mc;
593
594 #define AMDGPU_GPU_PAGE_SIZE 4096
595 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
596 #define AMDGPU_GPU_PAGE_SHIFT 12
597 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
598
599 struct amdgpu_gart {
600 dma_addr_t table_addr;
601 struct amdgpu_bo *robj;
602 void *ptr;
603 unsigned num_gpu_pages;
604 unsigned num_cpu_pages;
605 unsigned table_size;
606 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
607 struct page **pages;
608 #endif
609 bool ready;
610 const struct amdgpu_gart_funcs *gart_funcs;
611 };
612
613 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
614 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
615 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
616 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
617 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
618 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
619 int amdgpu_gart_init(struct amdgpu_device *adev);
620 void amdgpu_gart_fini(struct amdgpu_device *adev);
621 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
622 int pages);
623 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
624 int pages, struct page **pagelist,
625 dma_addr_t *dma_addr, uint32_t flags);
626 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
627
628 /*
629 * GPU MC structures, functions & helpers
630 */
631 struct amdgpu_mc {
632 resource_size_t aper_size;
633 resource_size_t aper_base;
634 resource_size_t agp_base;
635 /* for some chips with <= 32MB we need to lie
636 * about vram size near mc fb location */
637 u64 mc_vram_size;
638 u64 visible_vram_size;
639 u64 gtt_size;
640 u64 gtt_start;
641 u64 gtt_end;
642 u64 vram_start;
643 u64 vram_end;
644 unsigned vram_width;
645 u64 real_vram_size;
646 int vram_mtrr;
647 u64 gtt_base_align;
648 u64 mc_mask;
649 const struct firmware *fw; /* MC firmware */
650 uint32_t fw_version;
651 struct amdgpu_irq_src vm_fault;
652 uint32_t vram_type;
653 uint32_t srbm_soft_reset;
654 struct amdgpu_mode_mc_save save;
655 };
656
657 /*
658 * GPU doorbell structures, functions & helpers
659 */
660 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
661 {
662 AMDGPU_DOORBELL_KIQ = 0x000,
663 AMDGPU_DOORBELL_HIQ = 0x001,
664 AMDGPU_DOORBELL_DIQ = 0x002,
665 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
666 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
667 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
668 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
669 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
670 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
671 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
672 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
673 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
674 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
675 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
676 AMDGPU_DOORBELL_IH = 0x1E8,
677 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
678 AMDGPU_DOORBELL_INVALID = 0xFFFF
679 } AMDGPU_DOORBELL_ASSIGNMENT;
680
681 struct amdgpu_doorbell {
682 /* doorbell mmio */
683 resource_size_t base;
684 resource_size_t size;
685 u32 __iomem *ptr;
686 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
687 };
688
689 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
690 phys_addr_t *aperture_base,
691 size_t *aperture_size,
692 size_t *start_offset);
693
694 /*
695 * IRQS.
696 */
697
698 struct amdgpu_flip_work {
699 struct delayed_work flip_work;
700 struct work_struct unpin_work;
701 struct amdgpu_device *adev;
702 int crtc_id;
703 u32 target_vblank;
704 uint64_t base;
705 struct drm_pending_vblank_event *event;
706 struct amdgpu_bo *old_abo;
707 struct fence *excl;
708 unsigned shared_count;
709 struct fence **shared;
710 struct fence_cb cb;
711 bool async;
712 };
713
714
715 /*
716 * CP & rings.
717 */
718
719 struct amdgpu_ib {
720 struct amdgpu_sa_bo *sa_bo;
721 uint32_t length_dw;
722 uint64_t gpu_addr;
723 uint32_t *ptr;
724 uint32_t flags;
725 };
726
727 enum amdgpu_ring_type {
728 AMDGPU_RING_TYPE_GFX,
729 AMDGPU_RING_TYPE_COMPUTE,
730 AMDGPU_RING_TYPE_SDMA,
731 AMDGPU_RING_TYPE_UVD,
732 AMDGPU_RING_TYPE_VCE
733 };
734
735 extern const struct amd_sched_backend_ops amdgpu_sched_ops;
736
737 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
738 struct amdgpu_job **job, struct amdgpu_vm *vm);
739 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
740 struct amdgpu_job **job);
741
742 void amdgpu_job_free_resources(struct amdgpu_job *job);
743 void amdgpu_job_free(struct amdgpu_job *job);
744 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
745 struct amd_sched_entity *entity, void *owner,
746 struct fence **f);
747
748 struct amdgpu_ring {
749 struct amdgpu_device *adev;
750 const struct amdgpu_ring_funcs *funcs;
751 struct amdgpu_fence_driver fence_drv;
752 struct amd_gpu_scheduler sched;
753
754 struct amdgpu_bo *ring_obj;
755 volatile uint32_t *ring;
756 unsigned rptr_offs;
757 unsigned wptr;
758 unsigned wptr_old;
759 unsigned ring_size;
760 unsigned max_dw;
761 int count_dw;
762 uint64_t gpu_addr;
763 uint32_t align_mask;
764 uint32_t ptr_mask;
765 bool ready;
766 u32 nop;
767 u32 idx;
768 u32 me;
769 u32 pipe;
770 u32 queue;
771 struct amdgpu_bo *mqd_obj;
772 u32 doorbell_index;
773 bool use_doorbell;
774 unsigned wptr_offs;
775 unsigned fence_offs;
776 uint64_t current_ctx;
777 enum amdgpu_ring_type type;
778 char name[16];
779 unsigned cond_exe_offs;
780 u64 cond_exe_gpu_addr;
781 volatile u32 *cond_exe_cpu_addr;
782 #if defined(CONFIG_DEBUG_FS)
783 struct dentry *ent;
784 #endif
785 };
786
787 /*
788 * VM
789 */
790
791 /* maximum number of VMIDs */
792 #define AMDGPU_NUM_VM 16
793
794 /* Maximum number of PTEs the hardware can write with one command */
795 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
796
797 /* number of entries in page table */
798 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
799
800 /* PTBs (Page Table Blocks) need to be aligned to 32K */
801 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
802
803 /* LOG2 number of continuous pages for the fragment field */
804 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
805
806 #define AMDGPU_PTE_VALID (1 << 0)
807 #define AMDGPU_PTE_SYSTEM (1 << 1)
808 #define AMDGPU_PTE_SNOOPED (1 << 2)
809
810 /* VI only */
811 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
812
813 #define AMDGPU_PTE_READABLE (1 << 5)
814 #define AMDGPU_PTE_WRITEABLE (1 << 6)
815
816 #define AMDGPU_PTE_FRAG(x) ((x & 0x1f) << 7)
817
818 /* How to programm VM fault handling */
819 #define AMDGPU_VM_FAULT_STOP_NEVER 0
820 #define AMDGPU_VM_FAULT_STOP_FIRST 1
821 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
822
823 struct amdgpu_vm_pt {
824 struct amdgpu_bo_list_entry entry;
825 uint64_t addr;
826 uint64_t shadow_addr;
827 };
828
829 struct amdgpu_vm {
830 /* tree of virtual addresses mapped */
831 struct rb_root va;
832
833 /* protecting invalidated */
834 spinlock_t status_lock;
835
836 /* BOs moved, but not yet updated in the PT */
837 struct list_head invalidated;
838
839 /* BOs cleared in the PT because of a move */
840 struct list_head cleared;
841
842 /* BO mappings freed, but not yet updated in the PT */
843 struct list_head freed;
844
845 /* contains the page directory */
846 struct amdgpu_bo *page_directory;
847 unsigned max_pde_used;
848 struct fence *page_directory_fence;
849 uint64_t last_eviction_counter;
850
851 /* array of page tables, one for each page directory entry */
852 struct amdgpu_vm_pt *page_tables;
853
854 /* for id and flush management per ring */
855 struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS];
856
857 /* protecting freed */
858 spinlock_t freed_lock;
859
860 /* Scheduler entity for page table updates */
861 struct amd_sched_entity entity;
862
863 /* client id */
864 u64 client_id;
865 };
866
867 struct amdgpu_vm_id {
868 struct list_head list;
869 struct fence *first;
870 struct amdgpu_sync active;
871 struct fence *last_flush;
872 atomic64_t owner;
873
874 uint64_t pd_gpu_addr;
875 /* last flushed PD/PT update */
876 struct fence *flushed_updates;
877
878 uint32_t current_gpu_reset_count;
879
880 uint32_t gds_base;
881 uint32_t gds_size;
882 uint32_t gws_base;
883 uint32_t gws_size;
884 uint32_t oa_base;
885 uint32_t oa_size;
886 };
887
888 struct amdgpu_vm_manager {
889 /* Handling of VMIDs */
890 struct mutex lock;
891 unsigned num_ids;
892 struct list_head ids_lru;
893 struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
894
895 /* Handling of VM fences */
896 u64 fence_context;
897 unsigned seqno[AMDGPU_MAX_RINGS];
898
899 uint32_t max_pfn;
900 /* vram base address for page table entry */
901 u64 vram_base_offset;
902 /* is vm enabled? */
903 bool enabled;
904 /* vm pte handling */
905 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
906 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
907 unsigned vm_pte_num_rings;
908 atomic_t vm_pte_next_ring;
909 /* client id counter */
910 atomic64_t client_counter;
911 };
912
913 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
914 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
915 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
916 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
917 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
918 struct list_head *validated,
919 struct amdgpu_bo_list_entry *entry);
920 void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
921 struct list_head *duplicates);
922 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
923 struct amdgpu_vm *vm);
924 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
925 struct amdgpu_sync *sync, struct fence *fence,
926 struct amdgpu_job *job);
927 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);
928 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
929 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
930 struct amdgpu_vm *vm);
931 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
932 struct amdgpu_vm *vm);
933 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
934 struct amdgpu_sync *sync);
935 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
936 struct amdgpu_bo_va *bo_va,
937 bool clear);
938 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
939 struct amdgpu_bo *bo);
940 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
941 struct amdgpu_bo *bo);
942 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
943 struct amdgpu_vm *vm,
944 struct amdgpu_bo *bo);
945 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
946 struct amdgpu_bo_va *bo_va,
947 uint64_t addr, uint64_t offset,
948 uint64_t size, uint32_t flags);
949 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
950 struct amdgpu_bo_va *bo_va,
951 uint64_t addr);
952 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
953 struct amdgpu_bo_va *bo_va);
954
955 /*
956 * context related structures
957 */
958
959 struct amdgpu_ctx_ring {
960 uint64_t sequence;
961 struct fence **fences;
962 struct amd_sched_entity entity;
963 };
964
965 struct amdgpu_ctx {
966 struct kref refcount;
967 struct amdgpu_device *adev;
968 unsigned reset_counter;
969 spinlock_t ring_lock;
970 struct fence **fences;
971 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
972 bool preamble_presented;
973 };
974
975 struct amdgpu_ctx_mgr {
976 struct amdgpu_device *adev;
977 struct mutex lock;
978 /* protected by lock */
979 struct idr ctx_handles;
980 };
981
982 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
983 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
984
985 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
986 struct fence *fence);
987 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
988 struct amdgpu_ring *ring, uint64_t seq);
989
990 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
991 struct drm_file *filp);
992
993 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
994 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
995
996 /*
997 * file private structure
998 */
999
1000 struct amdgpu_fpriv {
1001 struct amdgpu_vm vm;
1002 struct mutex bo_list_lock;
1003 struct idr bo_list_handles;
1004 struct amdgpu_ctx_mgr ctx_mgr;
1005 };
1006
1007 /*
1008 * residency list
1009 */
1010
1011 struct amdgpu_bo_list {
1012 struct mutex lock;
1013 struct amdgpu_bo *gds_obj;
1014 struct amdgpu_bo *gws_obj;
1015 struct amdgpu_bo *oa_obj;
1016 unsigned first_userptr;
1017 unsigned num_entries;
1018 struct amdgpu_bo_list_entry *array;
1019 };
1020
1021 struct amdgpu_bo_list *
1022 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1023 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1024 struct list_head *validated);
1025 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1026 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1027
1028 /*
1029 * GFX stuff
1030 */
1031 #include "clearstate_defs.h"
1032
1033 struct amdgpu_rlc_funcs {
1034 void (*enter_safe_mode)(struct amdgpu_device *adev);
1035 void (*exit_safe_mode)(struct amdgpu_device *adev);
1036 };
1037
1038 struct amdgpu_rlc {
1039 /* for power gating */
1040 struct amdgpu_bo *save_restore_obj;
1041 uint64_t save_restore_gpu_addr;
1042 volatile uint32_t *sr_ptr;
1043 const u32 *reg_list;
1044 u32 reg_list_size;
1045 /* for clear state */
1046 struct amdgpu_bo *clear_state_obj;
1047 uint64_t clear_state_gpu_addr;
1048 volatile uint32_t *cs_ptr;
1049 const struct cs_section_def *cs_data;
1050 u32 clear_state_size;
1051 /* for cp tables */
1052 struct amdgpu_bo *cp_table_obj;
1053 uint64_t cp_table_gpu_addr;
1054 volatile uint32_t *cp_table_ptr;
1055 u32 cp_table_size;
1056
1057 /* safe mode for updating CG/PG state */
1058 bool in_safe_mode;
1059 const struct amdgpu_rlc_funcs *funcs;
1060
1061 /* for firmware data */
1062 u32 save_and_restore_offset;
1063 u32 clear_state_descriptor_offset;
1064 u32 avail_scratch_ram_locations;
1065 u32 reg_restore_list_size;
1066 u32 reg_list_format_start;
1067 u32 reg_list_format_separate_start;
1068 u32 starting_offsets_start;
1069 u32 reg_list_format_size_bytes;
1070 u32 reg_list_size_bytes;
1071
1072 u32 *register_list_format;
1073 u32 *register_restore;
1074 };
1075
1076 struct amdgpu_mec {
1077 struct amdgpu_bo *hpd_eop_obj;
1078 u64 hpd_eop_gpu_addr;
1079 u32 num_pipe;
1080 u32 num_mec;
1081 u32 num_queue;
1082 };
1083
1084 /*
1085 * GPU scratch registers structures, functions & helpers
1086 */
1087 struct amdgpu_scratch {
1088 unsigned num_reg;
1089 uint32_t reg_base;
1090 bool free[32];
1091 uint32_t reg[32];
1092 };
1093
1094 /*
1095 * GFX configurations
1096 */
1097 struct amdgpu_gca_config {
1098 unsigned max_shader_engines;
1099 unsigned max_tile_pipes;
1100 unsigned max_cu_per_sh;
1101 unsigned max_sh_per_se;
1102 unsigned max_backends_per_se;
1103 unsigned max_texture_channel_caches;
1104 unsigned max_gprs;
1105 unsigned max_gs_threads;
1106 unsigned max_hw_contexts;
1107 unsigned sc_prim_fifo_size_frontend;
1108 unsigned sc_prim_fifo_size_backend;
1109 unsigned sc_hiz_tile_fifo_size;
1110 unsigned sc_earlyz_tile_fifo_size;
1111
1112 unsigned num_tile_pipes;
1113 unsigned backend_enable_mask;
1114 unsigned mem_max_burst_length_bytes;
1115 unsigned mem_row_size_in_kb;
1116 unsigned shader_engine_tile_size;
1117 unsigned num_gpus;
1118 unsigned multi_gpu_tile_size;
1119 unsigned mc_arb_ramcfg;
1120 unsigned gb_addr_config;
1121 unsigned num_rbs;
1122
1123 uint32_t tile_mode_array[32];
1124 uint32_t macrotile_mode_array[16];
1125 };
1126
1127 struct amdgpu_cu_info {
1128 uint32_t number; /* total active CU number */
1129 uint32_t ao_cu_mask;
1130 uint32_t bitmap[4][4];
1131 };
1132
1133 struct amdgpu_gfx_funcs {
1134 /* get the gpu clock counter */
1135 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1136 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
1137 };
1138
1139 struct amdgpu_gfx {
1140 struct mutex gpu_clock_mutex;
1141 struct amdgpu_gca_config config;
1142 struct amdgpu_rlc rlc;
1143 struct amdgpu_mec mec;
1144 struct amdgpu_scratch scratch;
1145 const struct firmware *me_fw; /* ME firmware */
1146 uint32_t me_fw_version;
1147 const struct firmware *pfp_fw; /* PFP firmware */
1148 uint32_t pfp_fw_version;
1149 const struct firmware *ce_fw; /* CE firmware */
1150 uint32_t ce_fw_version;
1151 const struct firmware *rlc_fw; /* RLC firmware */
1152 uint32_t rlc_fw_version;
1153 const struct firmware *mec_fw; /* MEC firmware */
1154 uint32_t mec_fw_version;
1155 const struct firmware *mec2_fw; /* MEC2 firmware */
1156 uint32_t mec2_fw_version;
1157 uint32_t me_feature_version;
1158 uint32_t ce_feature_version;
1159 uint32_t pfp_feature_version;
1160 uint32_t rlc_feature_version;
1161 uint32_t mec_feature_version;
1162 uint32_t mec2_feature_version;
1163 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1164 unsigned num_gfx_rings;
1165 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1166 unsigned num_compute_rings;
1167 struct amdgpu_irq_src eop_irq;
1168 struct amdgpu_irq_src priv_reg_irq;
1169 struct amdgpu_irq_src priv_inst_irq;
1170 /* gfx status */
1171 uint32_t gfx_current_status;
1172 /* ce ram size*/
1173 unsigned ce_ram_size;
1174 struct amdgpu_cu_info cu_info;
1175 const struct amdgpu_gfx_funcs *funcs;
1176
1177 /* reset mask */
1178 uint32_t grbm_soft_reset;
1179 uint32_t srbm_soft_reset;
1180 };
1181
1182 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1183 unsigned size, struct amdgpu_ib *ib);
1184 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
1185 struct fence *f);
1186 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
1187 struct amdgpu_ib *ib, struct fence *last_vm_update,
1188 struct amdgpu_job *job, struct fence **f);
1189 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1190 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1191 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1192 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1193 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
1194 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
1195 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1196 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1197 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1198 unsigned ring_size, u32 nop, u32 align_mask,
1199 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1200 enum amdgpu_ring_type ring_type);
1201 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1202
1203 /*
1204 * CS.
1205 */
1206 struct amdgpu_cs_chunk {
1207 uint32_t chunk_id;
1208 uint32_t length_dw;
1209 void *kdata;
1210 };
1211
1212 struct amdgpu_cs_parser {
1213 struct amdgpu_device *adev;
1214 struct drm_file *filp;
1215 struct amdgpu_ctx *ctx;
1216
1217 /* chunks */
1218 unsigned nchunks;
1219 struct amdgpu_cs_chunk *chunks;
1220
1221 /* scheduler job object */
1222 struct amdgpu_job *job;
1223
1224 /* buffer objects */
1225 struct ww_acquire_ctx ticket;
1226 struct amdgpu_bo_list *bo_list;
1227 struct amdgpu_bo_list_entry vm_pd;
1228 struct list_head validated;
1229 struct fence *fence;
1230 uint64_t bytes_moved_threshold;
1231 uint64_t bytes_moved;
1232 struct amdgpu_bo_list_entry *evictable;
1233
1234 /* user fence */
1235 struct amdgpu_bo_list_entry uf_entry;
1236 };
1237
1238 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1239 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1240 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1241
1242 struct amdgpu_job {
1243 struct amd_sched_job base;
1244 struct amdgpu_device *adev;
1245 struct amdgpu_vm *vm;
1246 struct amdgpu_ring *ring;
1247 struct amdgpu_sync sync;
1248 struct amdgpu_ib *ibs;
1249 struct fence *fence; /* the hw fence */
1250 uint32_t preamble_status;
1251 uint32_t num_ibs;
1252 void *owner;
1253 uint64_t fence_ctx; /* the fence_context this job uses */
1254 bool vm_needs_flush;
1255 unsigned vm_id;
1256 uint64_t vm_pd_addr;
1257 uint32_t gds_base, gds_size;
1258 uint32_t gws_base, gws_size;
1259 uint32_t oa_base, oa_size;
1260
1261 /* user fence handling */
1262 uint64_t uf_addr;
1263 uint64_t uf_sequence;
1264
1265 };
1266 #define to_amdgpu_job(sched_job) \
1267 container_of((sched_job), struct amdgpu_job, base)
1268
amdgpu_get_ib_value(struct amdgpu_cs_parser * p,uint32_t ib_idx,int idx)1269 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1270 uint32_t ib_idx, int idx)
1271 {
1272 return p->job->ibs[ib_idx].ptr[idx];
1273 }
1274
amdgpu_set_ib_value(struct amdgpu_cs_parser * p,uint32_t ib_idx,int idx,uint32_t value)1275 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1276 uint32_t ib_idx, int idx,
1277 uint32_t value)
1278 {
1279 p->job->ibs[ib_idx].ptr[idx] = value;
1280 }
1281
1282 /*
1283 * Writeback
1284 */
1285 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1286
1287 struct amdgpu_wb {
1288 struct amdgpu_bo *wb_obj;
1289 volatile uint32_t *wb;
1290 uint64_t gpu_addr;
1291 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1292 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1293 };
1294
1295 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1296 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1297
1298
1299
1300 enum amdgpu_int_thermal_type {
1301 THERMAL_TYPE_NONE,
1302 THERMAL_TYPE_EXTERNAL,
1303 THERMAL_TYPE_EXTERNAL_GPIO,
1304 THERMAL_TYPE_RV6XX,
1305 THERMAL_TYPE_RV770,
1306 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1307 THERMAL_TYPE_EVERGREEN,
1308 THERMAL_TYPE_SUMO,
1309 THERMAL_TYPE_NI,
1310 THERMAL_TYPE_SI,
1311 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1312 THERMAL_TYPE_CI,
1313 THERMAL_TYPE_KV,
1314 };
1315
1316 enum amdgpu_dpm_auto_throttle_src {
1317 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1318 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1319 };
1320
1321 enum amdgpu_dpm_event_src {
1322 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1323 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1324 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1325 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1326 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1327 };
1328
1329 #define AMDGPU_MAX_VCE_LEVELS 6
1330
1331 enum amdgpu_vce_level {
1332 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1333 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1334 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1335 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1336 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1337 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1338 };
1339
1340 struct amdgpu_ps {
1341 u32 caps; /* vbios flags */
1342 u32 class; /* vbios flags */
1343 u32 class2; /* vbios flags */
1344 /* UVD clocks */
1345 u32 vclk;
1346 u32 dclk;
1347 /* VCE clocks */
1348 u32 evclk;
1349 u32 ecclk;
1350 bool vce_active;
1351 enum amdgpu_vce_level vce_level;
1352 /* asic priv */
1353 void *ps_priv;
1354 };
1355
1356 struct amdgpu_dpm_thermal {
1357 /* thermal interrupt work */
1358 struct work_struct work;
1359 /* low temperature threshold */
1360 int min_temp;
1361 /* high temperature threshold */
1362 int max_temp;
1363 /* was last interrupt low to high or high to low */
1364 bool high_to_low;
1365 /* interrupt source */
1366 struct amdgpu_irq_src irq;
1367 };
1368
1369 enum amdgpu_clk_action
1370 {
1371 AMDGPU_SCLK_UP = 1,
1372 AMDGPU_SCLK_DOWN
1373 };
1374
1375 struct amdgpu_blacklist_clocks
1376 {
1377 u32 sclk;
1378 u32 mclk;
1379 enum amdgpu_clk_action action;
1380 };
1381
1382 struct amdgpu_clock_and_voltage_limits {
1383 u32 sclk;
1384 u32 mclk;
1385 u16 vddc;
1386 u16 vddci;
1387 };
1388
1389 struct amdgpu_clock_array {
1390 u32 count;
1391 u32 *values;
1392 };
1393
1394 struct amdgpu_clock_voltage_dependency_entry {
1395 u32 clk;
1396 u16 v;
1397 };
1398
1399 struct amdgpu_clock_voltage_dependency_table {
1400 u32 count;
1401 struct amdgpu_clock_voltage_dependency_entry *entries;
1402 };
1403
1404 union amdgpu_cac_leakage_entry {
1405 struct {
1406 u16 vddc;
1407 u32 leakage;
1408 };
1409 struct {
1410 u16 vddc1;
1411 u16 vddc2;
1412 u16 vddc3;
1413 };
1414 };
1415
1416 struct amdgpu_cac_leakage_table {
1417 u32 count;
1418 union amdgpu_cac_leakage_entry *entries;
1419 };
1420
1421 struct amdgpu_phase_shedding_limits_entry {
1422 u16 voltage;
1423 u32 sclk;
1424 u32 mclk;
1425 };
1426
1427 struct amdgpu_phase_shedding_limits_table {
1428 u32 count;
1429 struct amdgpu_phase_shedding_limits_entry *entries;
1430 };
1431
1432 struct amdgpu_uvd_clock_voltage_dependency_entry {
1433 u32 vclk;
1434 u32 dclk;
1435 u16 v;
1436 };
1437
1438 struct amdgpu_uvd_clock_voltage_dependency_table {
1439 u8 count;
1440 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1441 };
1442
1443 struct amdgpu_vce_clock_voltage_dependency_entry {
1444 u32 ecclk;
1445 u32 evclk;
1446 u16 v;
1447 };
1448
1449 struct amdgpu_vce_clock_voltage_dependency_table {
1450 u8 count;
1451 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1452 };
1453
1454 struct amdgpu_ppm_table {
1455 u8 ppm_design;
1456 u16 cpu_core_number;
1457 u32 platform_tdp;
1458 u32 small_ac_platform_tdp;
1459 u32 platform_tdc;
1460 u32 small_ac_platform_tdc;
1461 u32 apu_tdp;
1462 u32 dgpu_tdp;
1463 u32 dgpu_ulv_power;
1464 u32 tj_max;
1465 };
1466
1467 struct amdgpu_cac_tdp_table {
1468 u16 tdp;
1469 u16 configurable_tdp;
1470 u16 tdc;
1471 u16 battery_power_limit;
1472 u16 small_power_limit;
1473 u16 low_cac_leakage;
1474 u16 high_cac_leakage;
1475 u16 maximum_power_delivery_limit;
1476 };
1477
1478 struct amdgpu_dpm_dynamic_state {
1479 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1480 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1481 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1482 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1483 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1484 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1485 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1486 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1487 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1488 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1489 struct amdgpu_clock_array valid_sclk_values;
1490 struct amdgpu_clock_array valid_mclk_values;
1491 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1492 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1493 u32 mclk_sclk_ratio;
1494 u32 sclk_mclk_delta;
1495 u16 vddc_vddci_delta;
1496 u16 min_vddc_for_pcie_gen2;
1497 struct amdgpu_cac_leakage_table cac_leakage_table;
1498 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1499 struct amdgpu_ppm_table *ppm_table;
1500 struct amdgpu_cac_tdp_table *cac_tdp_table;
1501 };
1502
1503 struct amdgpu_dpm_fan {
1504 u16 t_min;
1505 u16 t_med;
1506 u16 t_high;
1507 u16 pwm_min;
1508 u16 pwm_med;
1509 u16 pwm_high;
1510 u8 t_hyst;
1511 u32 cycle_delay;
1512 u16 t_max;
1513 u8 control_mode;
1514 u16 default_max_fan_pwm;
1515 u16 default_fan_output_sensitivity;
1516 u16 fan_output_sensitivity;
1517 bool ucode_fan_control;
1518 };
1519
1520 enum amdgpu_pcie_gen {
1521 AMDGPU_PCIE_GEN1 = 0,
1522 AMDGPU_PCIE_GEN2 = 1,
1523 AMDGPU_PCIE_GEN3 = 2,
1524 AMDGPU_PCIE_GEN_INVALID = 0xffff
1525 };
1526
1527 enum amdgpu_dpm_forced_level {
1528 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1529 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1530 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1531 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
1532 };
1533
1534 struct amdgpu_vce_state {
1535 /* vce clocks */
1536 u32 evclk;
1537 u32 ecclk;
1538 /* gpu clocks */
1539 u32 sclk;
1540 u32 mclk;
1541 u8 clk_idx;
1542 u8 pstate;
1543 };
1544
1545 struct amdgpu_dpm_funcs {
1546 int (*get_temperature)(struct amdgpu_device *adev);
1547 int (*pre_set_power_state)(struct amdgpu_device *adev);
1548 int (*set_power_state)(struct amdgpu_device *adev);
1549 void (*post_set_power_state)(struct amdgpu_device *adev);
1550 void (*display_configuration_changed)(struct amdgpu_device *adev);
1551 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1552 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1553 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1554 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1555 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1556 bool (*vblank_too_short)(struct amdgpu_device *adev);
1557 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1558 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1559 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1560 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1561 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1562 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1563 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1564 int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);
1565 int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);
1566 int (*get_sclk_od)(struct amdgpu_device *adev);
1567 int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value);
1568 int (*get_mclk_od)(struct amdgpu_device *adev);
1569 int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value);
1570 };
1571
1572 struct amdgpu_dpm {
1573 struct amdgpu_ps *ps;
1574 /* number of valid power states */
1575 int num_ps;
1576 /* current power state that is active */
1577 struct amdgpu_ps *current_ps;
1578 /* requested power state */
1579 struct amdgpu_ps *requested_ps;
1580 /* boot up power state */
1581 struct amdgpu_ps *boot_ps;
1582 /* default uvd power state */
1583 struct amdgpu_ps *uvd_ps;
1584 /* vce requirements */
1585 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1586 enum amdgpu_vce_level vce_level;
1587 enum amd_pm_state_type state;
1588 enum amd_pm_state_type user_state;
1589 u32 platform_caps;
1590 u32 voltage_response_time;
1591 u32 backbias_response_time;
1592 void *priv;
1593 u32 new_active_crtcs;
1594 int new_active_crtc_count;
1595 u32 current_active_crtcs;
1596 int current_active_crtc_count;
1597 struct amdgpu_dpm_dynamic_state dyn_state;
1598 struct amdgpu_dpm_fan fan;
1599 u32 tdp_limit;
1600 u32 near_tdp_limit;
1601 u32 near_tdp_limit_adjusted;
1602 u32 sq_ramping_threshold;
1603 u32 cac_leakage;
1604 u16 tdp_od_limit;
1605 u32 tdp_adjustment;
1606 u16 load_line_slope;
1607 bool power_control;
1608 bool ac_power;
1609 /* special states active */
1610 bool thermal_active;
1611 bool uvd_active;
1612 bool vce_active;
1613 /* thermal handling */
1614 struct amdgpu_dpm_thermal thermal;
1615 /* forced levels */
1616 enum amdgpu_dpm_forced_level forced_level;
1617 };
1618
1619 struct amdgpu_pm {
1620 struct mutex mutex;
1621 u32 current_sclk;
1622 u32 current_mclk;
1623 u32 default_sclk;
1624 u32 default_mclk;
1625 struct amdgpu_i2c_chan *i2c_bus;
1626 /* internal thermal controller on rv6xx+ */
1627 enum amdgpu_int_thermal_type int_thermal_type;
1628 struct device *int_hwmon_dev;
1629 /* fan control parameters */
1630 bool no_fan;
1631 u8 fan_pulses_per_revolution;
1632 u8 fan_min_rpm;
1633 u8 fan_max_rpm;
1634 /* dpm */
1635 bool dpm_enabled;
1636 bool sysfs_initialized;
1637 struct amdgpu_dpm dpm;
1638 const struct firmware *fw; /* SMC firmware */
1639 uint32_t fw_version;
1640 const struct amdgpu_dpm_funcs *funcs;
1641 uint32_t pcie_gen_mask;
1642 uint32_t pcie_mlw_mask;
1643 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
1644 };
1645
1646 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1647
1648 /*
1649 * UVD
1650 */
1651 #define AMDGPU_DEFAULT_UVD_HANDLES 10
1652 #define AMDGPU_MAX_UVD_HANDLES 40
1653 #define AMDGPU_UVD_STACK_SIZE (200*1024)
1654 #define AMDGPU_UVD_HEAP_SIZE (256*1024)
1655 #define AMDGPU_UVD_SESSION_SIZE (50*1024)
1656 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1657
1658 struct amdgpu_uvd {
1659 struct amdgpu_bo *vcpu_bo;
1660 void *cpu_addr;
1661 uint64_t gpu_addr;
1662 unsigned fw_version;
1663 void *saved_bo;
1664 unsigned max_handles;
1665 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1666 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1667 struct delayed_work idle_work;
1668 const struct firmware *fw; /* UVD firmware */
1669 struct amdgpu_ring ring;
1670 struct amdgpu_irq_src irq;
1671 bool address_64_bit;
1672 bool use_ctx_buf;
1673 struct amd_sched_entity entity;
1674 uint32_t srbm_soft_reset;
1675 };
1676
1677 /*
1678 * VCE
1679 */
1680 #define AMDGPU_MAX_VCE_HANDLES 16
1681 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1682
1683 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1684 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1685
1686 struct amdgpu_vce {
1687 struct amdgpu_bo *vcpu_bo;
1688 uint64_t gpu_addr;
1689 unsigned fw_version;
1690 unsigned fb_version;
1691 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1692 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1693 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1694 struct delayed_work idle_work;
1695 struct mutex idle_mutex;
1696 const struct firmware *fw; /* VCE firmware */
1697 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1698 struct amdgpu_irq_src irq;
1699 unsigned harvest_config;
1700 struct amd_sched_entity entity;
1701 uint32_t srbm_soft_reset;
1702 unsigned num_rings;
1703 };
1704
1705 /*
1706 * SDMA
1707 */
1708 struct amdgpu_sdma_instance {
1709 /* SDMA firmware */
1710 const struct firmware *fw;
1711 uint32_t fw_version;
1712 uint32_t feature_version;
1713
1714 struct amdgpu_ring ring;
1715 bool burst_nop;
1716 };
1717
1718 struct amdgpu_sdma {
1719 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1720 #ifdef CONFIG_DRM_AMDGPU_SI
1721 //SI DMA has a difference trap irq number for the second engine
1722 struct amdgpu_irq_src trap_irq_1;
1723 #endif
1724 struct amdgpu_irq_src trap_irq;
1725 struct amdgpu_irq_src illegal_inst_irq;
1726 int num_instances;
1727 uint32_t srbm_soft_reset;
1728 };
1729
1730 /*
1731 * Firmware
1732 */
1733 struct amdgpu_firmware {
1734 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1735 bool smu_load;
1736 struct amdgpu_bo *fw_buf;
1737 unsigned int fw_size;
1738 };
1739
1740 /*
1741 * Benchmarking
1742 */
1743 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1744
1745
1746 /*
1747 * Testing
1748 */
1749 void amdgpu_test_moves(struct amdgpu_device *adev);
1750 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1751 struct amdgpu_ring *cpA,
1752 struct amdgpu_ring *cpB);
1753 void amdgpu_test_syncing(struct amdgpu_device *adev);
1754
1755 /*
1756 * MMU Notifier
1757 */
1758 #if defined(CONFIG_MMU_NOTIFIER)
1759 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1760 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1761 #else
amdgpu_mn_register(struct amdgpu_bo * bo,unsigned long addr)1762 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1763 {
1764 return -ENODEV;
1765 }
amdgpu_mn_unregister(struct amdgpu_bo * bo)1766 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1767 #endif
1768
1769 /*
1770 * Debugfs
1771 */
1772 struct amdgpu_debugfs {
1773 const struct drm_info_list *files;
1774 unsigned num_files;
1775 };
1776
1777 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1778 const struct drm_info_list *files,
1779 unsigned nfiles);
1780 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1781
1782 #if defined(CONFIG_DEBUG_FS)
1783 int amdgpu_debugfs_init(struct drm_minor *minor);
1784 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1785 #endif
1786
1787 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1788
1789 /*
1790 * amdgpu smumgr functions
1791 */
1792 struct amdgpu_smumgr_funcs {
1793 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1794 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1795 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1796 };
1797
1798 /*
1799 * amdgpu smumgr
1800 */
1801 struct amdgpu_smumgr {
1802 struct amdgpu_bo *toc_buf;
1803 struct amdgpu_bo *smu_buf;
1804 /* asic priv smu data */
1805 void *priv;
1806 spinlock_t smu_lock;
1807 /* smumgr functions */
1808 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1809 /* ucode loading complete flag */
1810 uint32_t fw_flags;
1811 };
1812
1813 /*
1814 * ASIC specific register table accessible by UMD
1815 */
1816 struct amdgpu_allowed_register_entry {
1817 uint32_t reg_offset;
1818 bool untouched;
1819 bool grbm_indexed;
1820 };
1821
1822 /*
1823 * ASIC specific functions.
1824 */
1825 struct amdgpu_asic_funcs {
1826 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1827 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1828 u8 *bios, u32 length_bytes);
1829 void (*detect_hw_virtualization) (struct amdgpu_device *adev);
1830 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1831 u32 sh_num, u32 reg_offset, u32 *value);
1832 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1833 int (*reset)(struct amdgpu_device *adev);
1834 /* get the reference clock */
1835 u32 (*get_xclk)(struct amdgpu_device *adev);
1836 /* MM block clocks */
1837 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1838 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1839 /* static power management */
1840 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1841 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
1842 };
1843
1844 /*
1845 * IOCTL.
1846 */
1847 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1848 struct drm_file *filp);
1849 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1850 struct drm_file *filp);
1851
1852 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1853 struct drm_file *filp);
1854 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1855 struct drm_file *filp);
1856 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1857 struct drm_file *filp);
1858 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1859 struct drm_file *filp);
1860 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1861 struct drm_file *filp);
1862 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1863 struct drm_file *filp);
1864 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1865 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1866
1867 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1868 struct drm_file *filp);
1869
1870 /* VRAM scratch page for HDP bug, default vram page */
1871 struct amdgpu_vram_scratch {
1872 struct amdgpu_bo *robj;
1873 volatile uint32_t *ptr;
1874 u64 gpu_addr;
1875 };
1876
1877 /*
1878 * ACPI
1879 */
1880 struct amdgpu_atif_notification_cfg {
1881 bool enabled;
1882 int command_code;
1883 };
1884
1885 struct amdgpu_atif_notifications {
1886 bool display_switch;
1887 bool expansion_mode_change;
1888 bool thermal_state;
1889 bool forced_power_state;
1890 bool system_power_state;
1891 bool display_conf_change;
1892 bool px_gfx_switch;
1893 bool brightness_change;
1894 bool dgpu_display_event;
1895 };
1896
1897 struct amdgpu_atif_functions {
1898 bool system_params;
1899 bool sbios_requests;
1900 bool select_active_disp;
1901 bool lid_state;
1902 bool get_tv_standard;
1903 bool set_tv_standard;
1904 bool get_panel_expansion_mode;
1905 bool set_panel_expansion_mode;
1906 bool temperature_change;
1907 bool graphics_device_types;
1908 };
1909
1910 struct amdgpu_atif {
1911 struct amdgpu_atif_notifications notifications;
1912 struct amdgpu_atif_functions functions;
1913 struct amdgpu_atif_notification_cfg notification_cfg;
1914 struct amdgpu_encoder *encoder_for_bl;
1915 };
1916
1917 struct amdgpu_atcs_functions {
1918 bool get_ext_state;
1919 bool pcie_perf_req;
1920 bool pcie_dev_rdy;
1921 bool pcie_bus_width;
1922 };
1923
1924 struct amdgpu_atcs {
1925 struct amdgpu_atcs_functions functions;
1926 };
1927
1928 /*
1929 * CGS
1930 */
1931 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1932 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
1933
1934 /*
1935 * Core structure, functions and helpers.
1936 */
1937 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1938 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1939
1940 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1941 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1942
1943 struct amdgpu_ip_block_status {
1944 bool valid;
1945 bool sw;
1946 bool hw;
1947 bool late_initialized;
1948 bool hang;
1949 };
1950
1951 struct amdgpu_device {
1952 struct device *dev;
1953 struct drm_device *ddev;
1954 struct pci_dev *pdev;
1955
1956 #ifdef CONFIG_DRM_AMD_ACP
1957 struct amdgpu_acp acp;
1958 #endif
1959
1960 /* ASIC */
1961 enum amd_asic_type asic_type;
1962 uint32_t family;
1963 uint32_t rev_id;
1964 uint32_t external_rev_id;
1965 unsigned long flags;
1966 int usec_timeout;
1967 const struct amdgpu_asic_funcs *asic_funcs;
1968 bool shutdown;
1969 bool need_dma32;
1970 bool accel_working;
1971 struct work_struct reset_work;
1972 struct notifier_block acpi_nb;
1973 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1974 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1975 unsigned debugfs_count;
1976 #if defined(CONFIG_DEBUG_FS)
1977 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1978 #endif
1979 struct amdgpu_atif atif;
1980 struct amdgpu_atcs atcs;
1981 struct mutex srbm_mutex;
1982 /* GRBM index mutex. Protects concurrent access to GRBM index */
1983 struct mutex grbm_idx_mutex;
1984 struct dev_pm_domain vga_pm_domain;
1985 bool have_disp_power_ref;
1986
1987 /* BIOS */
1988 uint8_t *bios;
1989 bool is_atom_bios;
1990 struct amdgpu_bo *stollen_vga_memory;
1991 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1992
1993 /* Register/doorbell mmio */
1994 resource_size_t rmmio_base;
1995 resource_size_t rmmio_size;
1996 void __iomem *rmmio;
1997 /* protects concurrent MM_INDEX/DATA based register access */
1998 spinlock_t mmio_idx_lock;
1999 /* protects concurrent SMC based register access */
2000 spinlock_t smc_idx_lock;
2001 amdgpu_rreg_t smc_rreg;
2002 amdgpu_wreg_t smc_wreg;
2003 /* protects concurrent PCIE register access */
2004 spinlock_t pcie_idx_lock;
2005 amdgpu_rreg_t pcie_rreg;
2006 amdgpu_wreg_t pcie_wreg;
2007 amdgpu_rreg_t pciep_rreg;
2008 amdgpu_wreg_t pciep_wreg;
2009 /* protects concurrent UVD register access */
2010 spinlock_t uvd_ctx_idx_lock;
2011 amdgpu_rreg_t uvd_ctx_rreg;
2012 amdgpu_wreg_t uvd_ctx_wreg;
2013 /* protects concurrent DIDT register access */
2014 spinlock_t didt_idx_lock;
2015 amdgpu_rreg_t didt_rreg;
2016 amdgpu_wreg_t didt_wreg;
2017 /* protects concurrent gc_cac register access */
2018 spinlock_t gc_cac_idx_lock;
2019 amdgpu_rreg_t gc_cac_rreg;
2020 amdgpu_wreg_t gc_cac_wreg;
2021 /* protects concurrent ENDPOINT (audio) register access */
2022 spinlock_t audio_endpt_idx_lock;
2023 amdgpu_block_rreg_t audio_endpt_rreg;
2024 amdgpu_block_wreg_t audio_endpt_wreg;
2025 void __iomem *rio_mem;
2026 resource_size_t rio_mem_size;
2027 struct amdgpu_doorbell doorbell;
2028
2029 /* clock/pll info */
2030 struct amdgpu_clock clock;
2031
2032 /* MC */
2033 struct amdgpu_mc mc;
2034 struct amdgpu_gart gart;
2035 struct amdgpu_dummy_page dummy_page;
2036 struct amdgpu_vm_manager vm_manager;
2037
2038 /* memory management */
2039 struct amdgpu_mman mman;
2040 struct amdgpu_vram_scratch vram_scratch;
2041 struct amdgpu_wb wb;
2042 atomic64_t vram_usage;
2043 atomic64_t vram_vis_usage;
2044 atomic64_t gtt_usage;
2045 atomic64_t num_bytes_moved;
2046 atomic64_t num_evictions;
2047 atomic_t gpu_reset_counter;
2048
2049 /* data for buffer migration throttling */
2050 struct {
2051 spinlock_t lock;
2052 s64 last_update_us;
2053 s64 accum_us; /* accumulated microseconds */
2054 u32 log2_max_MBps;
2055 } mm_stats;
2056
2057 /* display */
2058 bool enable_virtual_display;
2059 struct amdgpu_mode_info mode_info;
2060 struct work_struct hotplug_work;
2061 struct amdgpu_irq_src crtc_irq;
2062 struct amdgpu_irq_src pageflip_irq;
2063 struct amdgpu_irq_src hpd_irq;
2064
2065 /* rings */
2066 u64 fence_context;
2067 unsigned num_rings;
2068 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2069 bool ib_pool_ready;
2070 struct amdgpu_sa_manager ring_tmp_bo;
2071
2072 /* interrupts */
2073 struct amdgpu_irq irq;
2074
2075 /* powerplay */
2076 struct amd_powerplay powerplay;
2077 bool pp_enabled;
2078 bool pp_force_state_enabled;
2079
2080 /* dpm */
2081 struct amdgpu_pm pm;
2082 u32 cg_flags;
2083 u32 pg_flags;
2084
2085 /* amdgpu smumgr */
2086 struct amdgpu_smumgr smu;
2087
2088 /* gfx */
2089 struct amdgpu_gfx gfx;
2090
2091 /* sdma */
2092 struct amdgpu_sdma sdma;
2093
2094 /* uvd */
2095 struct amdgpu_uvd uvd;
2096
2097 /* vce */
2098 struct amdgpu_vce vce;
2099
2100 /* firmwares */
2101 struct amdgpu_firmware firmware;
2102
2103 /* GDS */
2104 struct amdgpu_gds gds;
2105
2106 const struct amdgpu_ip_block_version *ip_blocks;
2107 int num_ip_blocks;
2108 struct amdgpu_ip_block_status *ip_block_status;
2109 struct mutex mn_lock;
2110 DECLARE_HASHTABLE(mn_hash, 7);
2111
2112 /* tracking pinned memory */
2113 u64 vram_pin_size;
2114 u64 invisible_pin_size;
2115 u64 gart_pin_size;
2116
2117 /* amdkfd interface */
2118 struct kfd_dev *kfd;
2119
2120 struct amdgpu_virtualization virtualization;
2121
2122 /* link all shadow bo */
2123 struct list_head shadow_list;
2124 struct mutex shadow_list_lock;
2125 /* link all gtt */
2126 spinlock_t gtt_list_lock;
2127 struct list_head gtt_list;
2128
2129 };
2130
2131 bool amdgpu_device_is_px(struct drm_device *dev);
2132 int amdgpu_device_init(struct amdgpu_device *adev,
2133 struct drm_device *ddev,
2134 struct pci_dev *pdev,
2135 uint32_t flags);
2136 void amdgpu_device_fini(struct amdgpu_device *adev);
2137 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2138
2139 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2140 bool always_indirect);
2141 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2142 bool always_indirect);
2143 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2144 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2145
2146 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2147 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2148
2149 /*
2150 * Registers read & write functions.
2151 */
2152 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2153 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2154 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2155 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2156 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2157 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2158 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2159 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2160 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2161 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
2162 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
2163 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2164 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2165 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2166 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2167 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2168 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2169 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
2170 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
2171 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2172 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2173 #define WREG32_P(reg, val, mask) \
2174 do { \
2175 uint32_t tmp_ = RREG32(reg); \
2176 tmp_ &= (mask); \
2177 tmp_ |= ((val) & ~(mask)); \
2178 WREG32(reg, tmp_); \
2179 } while (0)
2180 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2181 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2182 #define WREG32_PLL_P(reg, val, mask) \
2183 do { \
2184 uint32_t tmp_ = RREG32_PLL(reg); \
2185 tmp_ &= (mask); \
2186 tmp_ |= ((val) & ~(mask)); \
2187 WREG32_PLL(reg, tmp_); \
2188 } while (0)
2189 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2190 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2191 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2192
2193 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2194 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2195
2196 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2197 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2198
2199 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2200 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2201 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2202
2203 #define REG_GET_FIELD(value, reg, field) \
2204 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2205
2206 #define WREG32_FIELD(reg, field, val) \
2207 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
2208
2209 /*
2210 * BIOS helpers.
2211 */
2212 #define RBIOS8(i) (adev->bios[i])
2213 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2214 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2215
2216 /*
2217 * RING helpers.
2218 */
amdgpu_ring_write(struct amdgpu_ring * ring,uint32_t v)2219 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2220 {
2221 if (ring->count_dw <= 0)
2222 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2223 ring->ring[ring->wptr++] = v;
2224 ring->wptr &= ring->ptr_mask;
2225 ring->count_dw--;
2226 }
2227
2228 static inline struct amdgpu_sdma_instance *
amdgpu_get_sdma_instance(struct amdgpu_ring * ring)2229 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2230 {
2231 struct amdgpu_device *adev = ring->adev;
2232 int i;
2233
2234 for (i = 0; i < adev->sdma.num_instances; i++)
2235 if (&adev->sdma.instance[i].ring == ring)
2236 break;
2237
2238 if (i < AMDGPU_MAX_SDMA_INSTANCES)
2239 return &adev->sdma.instance[i];
2240 else
2241 return NULL;
2242 }
2243
2244 /*
2245 * ASICs macro.
2246 */
2247 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2248 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2249 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2250 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2251 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2252 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
2253 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
2254 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2255 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2256 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
2257 #define amdgpu_asic_detect_hw_virtualization(adev) (adev)->asic_funcs->detect_hw_virtualization((adev))
2258 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2259 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2260 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2261 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2262 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
2263 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2264 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2265 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2266 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
2267 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2268 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2269 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2270 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
2271 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
2272 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2273 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2274 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2275 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2276 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
2277 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
2278 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
2279 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
2280 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
2281 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
2282 #define amdgpu_ring_get_emit_ib_size(r) (r)->funcs->get_emit_ib_size((r))
2283 #define amdgpu_ring_get_dma_frame_size(r) (r)->funcs->get_dma_frame_size((r))
2284 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2285 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2286 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2287 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2288 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2289 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2290 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2291 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2292 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2293 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2294 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2295 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2296 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2297 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
2298 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2299 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2300 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2301 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2302 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2303 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2304 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2305 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2306 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2307 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2308 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2309 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2310 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2311 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2312 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
2313 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
2314
2315 #define amdgpu_dpm_read_sensor(adev, idx, value) \
2316 ((adev)->pp_enabled ? \
2317 (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value)) : \
2318 -EINVAL)
2319
2320 #define amdgpu_dpm_get_temperature(adev) \
2321 ((adev)->pp_enabled ? \
2322 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
2323 (adev)->pm.funcs->get_temperature((adev)))
2324
2325 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
2326 ((adev)->pp_enabled ? \
2327 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
2328 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
2329
2330 #define amdgpu_dpm_get_fan_control_mode(adev) \
2331 ((adev)->pp_enabled ? \
2332 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
2333 (adev)->pm.funcs->get_fan_control_mode((adev)))
2334
2335 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
2336 ((adev)->pp_enabled ? \
2337 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2338 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
2339
2340 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
2341 ((adev)->pp_enabled ? \
2342 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2343 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
2344
2345 #define amdgpu_dpm_get_sclk(adev, l) \
2346 ((adev)->pp_enabled ? \
2347 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
2348 (adev)->pm.funcs->get_sclk((adev), (l)))
2349
2350 #define amdgpu_dpm_get_mclk(adev, l) \
2351 ((adev)->pp_enabled ? \
2352 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
2353 (adev)->pm.funcs->get_mclk((adev), (l)))
2354
2355
2356 #define amdgpu_dpm_force_performance_level(adev, l) \
2357 ((adev)->pp_enabled ? \
2358 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
2359 (adev)->pm.funcs->force_performance_level((adev), (l)))
2360
2361 #define amdgpu_dpm_powergate_uvd(adev, g) \
2362 ((adev)->pp_enabled ? \
2363 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
2364 (adev)->pm.funcs->powergate_uvd((adev), (g)))
2365
2366 #define amdgpu_dpm_powergate_vce(adev, g) \
2367 ((adev)->pp_enabled ? \
2368 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
2369 (adev)->pm.funcs->powergate_vce((adev), (g)))
2370
2371 #define amdgpu_dpm_get_current_power_state(adev) \
2372 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
2373
2374 #define amdgpu_dpm_get_performance_level(adev) \
2375 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
2376
2377 #define amdgpu_dpm_get_pp_num_states(adev, data) \
2378 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2379
2380 #define amdgpu_dpm_get_pp_table(adev, table) \
2381 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2382
2383 #define amdgpu_dpm_set_pp_table(adev, buf, size) \
2384 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2385
2386 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2387 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2388
2389 #define amdgpu_dpm_force_clock_level(adev, type, level) \
2390 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2391
2392 #define amdgpu_dpm_get_sclk_od(adev) \
2393 (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
2394
2395 #define amdgpu_dpm_set_sclk_od(adev, value) \
2396 (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
2397
2398 #define amdgpu_dpm_get_mclk_od(adev) \
2399 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
2400
2401 #define amdgpu_dpm_set_mclk_od(adev, value) \
2402 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
2403
2404 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
2405 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
2406
2407 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2408
2409 /* Common functions */
2410 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2411 bool amdgpu_need_backup(struct amdgpu_device *adev);
2412 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2413 bool amdgpu_card_posted(struct amdgpu_device *adev);
2414 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2415
2416 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2417 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2418 u32 ip_instance, u32 ring,
2419 struct amdgpu_ring **out_ring);
2420 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
2421 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2422 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
2423 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2424 uint32_t flags);
2425 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2426 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
2427 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2428 unsigned long end);
2429 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
2430 int *last_invalidated);
2431 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2432 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2433 struct ttm_mem_reg *mem);
2434 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2435 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2436 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2437 u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev);
2438 int amdgpu_ttm_global_init(struct amdgpu_device *adev);
2439 int amdgpu_ttm_init(struct amdgpu_device *adev);
2440 void amdgpu_ttm_fini(struct amdgpu_device *adev);
2441 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2442 const u32 *registers,
2443 const u32 array_size);
2444
2445 bool amdgpu_device_is_px(struct drm_device *dev);
2446 /* atpx handler */
2447 #if defined(CONFIG_VGA_SWITCHEROO)
2448 void amdgpu_register_atpx_handler(void);
2449 void amdgpu_unregister_atpx_handler(void);
2450 bool amdgpu_has_atpx_dgpu_power_cntl(void);
2451 bool amdgpu_is_atpx_hybrid(void);
2452 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
2453 #else
amdgpu_register_atpx_handler(void)2454 static inline void amdgpu_register_atpx_handler(void) {}
amdgpu_unregister_atpx_handler(void)2455 static inline void amdgpu_unregister_atpx_handler(void) {}
amdgpu_has_atpx_dgpu_power_cntl(void)2456 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
amdgpu_is_atpx_hybrid(void)2457 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
amdgpu_atpx_dgpu_req_power_for_displays(void)2458 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
2459 #endif
2460
2461 /*
2462 * KMS
2463 */
2464 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2465 extern const int amdgpu_max_kms_ioctl;
2466
2467 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2468 int amdgpu_driver_unload_kms(struct drm_device *dev);
2469 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2470 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2471 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2472 struct drm_file *file_priv);
2473 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2474 struct drm_file *file_priv);
2475 int amdgpu_suspend(struct amdgpu_device *adev);
2476 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
2477 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
2478 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2479 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2480 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2481 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
2482 int *max_error,
2483 struct timeval *vblank_time,
2484 unsigned flags);
2485 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2486 unsigned long arg);
2487
2488 /*
2489 * functions used by amdgpu_encoder.c
2490 */
2491 struct amdgpu_afmt_acr {
2492 u32 clock;
2493
2494 int n_32khz;
2495 int cts_32khz;
2496
2497 int n_44_1khz;
2498 int cts_44_1khz;
2499
2500 int n_48khz;
2501 int cts_48khz;
2502
2503 };
2504
2505 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2506
2507 /* amdgpu_acpi.c */
2508 #if defined(CONFIG_ACPI)
2509 int amdgpu_acpi_init(struct amdgpu_device *adev);
2510 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2511 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2512 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2513 u8 perf_req, bool advertise);
2514 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2515 #else
amdgpu_acpi_init(struct amdgpu_device * adev)2516 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
amdgpu_acpi_fini(struct amdgpu_device * adev)2517 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2518 #endif
2519
2520 struct amdgpu_bo_va_mapping *
2521 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2522 uint64_t addr, struct amdgpu_bo **bo);
2523 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
2524
2525 #include "amdgpu_object.h"
2526 #endif
2527