1 /*
2 * skl-sst-ipc.c - Intel skl IPC Support
3 *
4 * Copyright (C) 2014-15, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as version 2, as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 */
15 #include <linux/device.h>
16
17 #include "../common/sst-dsp.h"
18 #include "../common/sst-dsp-priv.h"
19 #include "skl.h"
20 #include "skl-sst-dsp.h"
21 #include "skl-sst-ipc.h"
22 #include "sound/hdaudio_ext.h"
23
24
25 #define IPC_IXC_STATUS_BITS 24
26
27 /* Global Message - Generic */
28 #define IPC_GLB_TYPE_SHIFT 24
29 #define IPC_GLB_TYPE_MASK (0xf << IPC_GLB_TYPE_SHIFT)
30 #define IPC_GLB_TYPE(x) ((x) << IPC_GLB_TYPE_SHIFT)
31
32 /* Global Message - Reply */
33 #define IPC_GLB_REPLY_STATUS_SHIFT 24
34 #define IPC_GLB_REPLY_STATUS_MASK ((0x1 << IPC_GLB_REPLY_STATUS_SHIFT) - 1)
35 #define IPC_GLB_REPLY_STATUS(x) ((x) << IPC_GLB_REPLY_STATUS_SHIFT)
36
37 #define IPC_TIMEOUT_MSECS 3000
38
39 #define IPC_EMPTY_LIST_SIZE 8
40
41 #define IPC_MSG_TARGET_SHIFT 30
42 #define IPC_MSG_TARGET_MASK 0x1
43 #define IPC_MSG_TARGET(x) (((x) & IPC_MSG_TARGET_MASK) \
44 << IPC_MSG_TARGET_SHIFT)
45
46 #define IPC_MSG_DIR_SHIFT 29
47 #define IPC_MSG_DIR_MASK 0x1
48 #define IPC_MSG_DIR(x) (((x) & IPC_MSG_DIR_MASK) \
49 << IPC_MSG_DIR_SHIFT)
50 /* Global Notification Message */
51 #define IPC_GLB_NOTIFY_TYPE_SHIFT 16
52 #define IPC_GLB_NOTIFY_TYPE_MASK 0xFF
53 #define IPC_GLB_NOTIFY_TYPE(x) (((x) >> IPC_GLB_NOTIFY_TYPE_SHIFT) \
54 & IPC_GLB_NOTIFY_TYPE_MASK)
55
56 #define IPC_GLB_NOTIFY_MSG_TYPE_SHIFT 24
57 #define IPC_GLB_NOTIFY_MSG_TYPE_MASK 0x1F
58 #define IPC_GLB_NOTIFY_MSG_TYPE(x) (((x) >> IPC_GLB_NOTIFY_MSG_TYPE_SHIFT) \
59 & IPC_GLB_NOTIFY_MSG_TYPE_MASK)
60
61 #define IPC_GLB_NOTIFY_RSP_SHIFT 29
62 #define IPC_GLB_NOTIFY_RSP_MASK 0x1
63 #define IPC_GLB_NOTIFY_RSP_TYPE(x) (((x) >> IPC_GLB_NOTIFY_RSP_SHIFT) \
64 & IPC_GLB_NOTIFY_RSP_MASK)
65
66 /* Pipeline operations */
67
68 /* Create pipeline message */
69 #define IPC_PPL_MEM_SIZE_SHIFT 0
70 #define IPC_PPL_MEM_SIZE_MASK 0x7FF
71 #define IPC_PPL_MEM_SIZE(x) (((x) & IPC_PPL_MEM_SIZE_MASK) \
72 << IPC_PPL_MEM_SIZE_SHIFT)
73
74 #define IPC_PPL_TYPE_SHIFT 11
75 #define IPC_PPL_TYPE_MASK 0x1F
76 #define IPC_PPL_TYPE(x) (((x) & IPC_PPL_TYPE_MASK) \
77 << IPC_PPL_TYPE_SHIFT)
78
79 #define IPC_INSTANCE_ID_SHIFT 16
80 #define IPC_INSTANCE_ID_MASK 0xFF
81 #define IPC_INSTANCE_ID(x) (((x) & IPC_INSTANCE_ID_MASK) \
82 << IPC_INSTANCE_ID_SHIFT)
83
84 /* Set pipeline state message */
85 #define IPC_PPL_STATE_SHIFT 0
86 #define IPC_PPL_STATE_MASK 0x1F
87 #define IPC_PPL_STATE(x) (((x) & IPC_PPL_STATE_MASK) \
88 << IPC_PPL_STATE_SHIFT)
89
90 /* Module operations primary register */
91 #define IPC_MOD_ID_SHIFT 0
92 #define IPC_MOD_ID_MASK 0xFFFF
93 #define IPC_MOD_ID(x) (((x) & IPC_MOD_ID_MASK) \
94 << IPC_MOD_ID_SHIFT)
95
96 #define IPC_MOD_INSTANCE_ID_SHIFT 16
97 #define IPC_MOD_INSTANCE_ID_MASK 0xFF
98 #define IPC_MOD_INSTANCE_ID(x) (((x) & IPC_MOD_INSTANCE_ID_MASK) \
99 << IPC_MOD_INSTANCE_ID_SHIFT)
100
101 /* Init instance message extension register */
102 #define IPC_PARAM_BLOCK_SIZE_SHIFT 0
103 #define IPC_PARAM_BLOCK_SIZE_MASK 0xFFFF
104 #define IPC_PARAM_BLOCK_SIZE(x) (((x) & IPC_PARAM_BLOCK_SIZE_MASK) \
105 << IPC_PARAM_BLOCK_SIZE_SHIFT)
106
107 #define IPC_PPL_INSTANCE_ID_SHIFT 16
108 #define IPC_PPL_INSTANCE_ID_MASK 0xFF
109 #define IPC_PPL_INSTANCE_ID(x) (((x) & IPC_PPL_INSTANCE_ID_MASK) \
110 << IPC_PPL_INSTANCE_ID_SHIFT)
111
112 #define IPC_CORE_ID_SHIFT 24
113 #define IPC_CORE_ID_MASK 0x1F
114 #define IPC_CORE_ID(x) (((x) & IPC_CORE_ID_MASK) \
115 << IPC_CORE_ID_SHIFT)
116
117 #define IPC_DOMAIN_SHIFT 28
118 #define IPC_DOMAIN_MASK 0x1
119 #define IPC_DOMAIN(x) (((x) & IPC_DOMAIN_MASK) \
120 << IPC_DOMAIN_SHIFT)
121
122 /* Bind/Unbind message extension register */
123 #define IPC_DST_MOD_ID_SHIFT 0
124 #define IPC_DST_MOD_ID(x) (((x) & IPC_MOD_ID_MASK) \
125 << IPC_DST_MOD_ID_SHIFT)
126
127 #define IPC_DST_MOD_INSTANCE_ID_SHIFT 16
128 #define IPC_DST_MOD_INSTANCE_ID(x) (((x) & IPC_MOD_INSTANCE_ID_MASK) \
129 << IPC_DST_MOD_INSTANCE_ID_SHIFT)
130
131 #define IPC_DST_QUEUE_SHIFT 24
132 #define IPC_DST_QUEUE_MASK 0x7
133 #define IPC_DST_QUEUE(x) (((x) & IPC_DST_QUEUE_MASK) \
134 << IPC_DST_QUEUE_SHIFT)
135
136 #define IPC_SRC_QUEUE_SHIFT 27
137 #define IPC_SRC_QUEUE_MASK 0x7
138 #define IPC_SRC_QUEUE(x) (((x) & IPC_SRC_QUEUE_MASK) \
139 << IPC_SRC_QUEUE_SHIFT)
140 /* Load Module count */
141 #define IPC_LOAD_MODULE_SHIFT 0
142 #define IPC_LOAD_MODULE_MASK 0xFF
143 #define IPC_LOAD_MODULE_CNT(x) (((x) & IPC_LOAD_MODULE_MASK) \
144 << IPC_LOAD_MODULE_SHIFT)
145
146 /* Save pipeline messgae extension register */
147 #define IPC_DMA_ID_SHIFT 0
148 #define IPC_DMA_ID_MASK 0x1F
149 #define IPC_DMA_ID(x) (((x) & IPC_DMA_ID_MASK) \
150 << IPC_DMA_ID_SHIFT)
151 /* Large Config message extension register */
152 #define IPC_DATA_OFFSET_SZ_SHIFT 0
153 #define IPC_DATA_OFFSET_SZ_MASK 0xFFFFF
154 #define IPC_DATA_OFFSET_SZ(x) (((x) & IPC_DATA_OFFSET_SZ_MASK) \
155 << IPC_DATA_OFFSET_SZ_SHIFT)
156 #define IPC_DATA_OFFSET_SZ_CLEAR ~(IPC_DATA_OFFSET_SZ_MASK \
157 << IPC_DATA_OFFSET_SZ_SHIFT)
158
159 #define IPC_LARGE_PARAM_ID_SHIFT 20
160 #define IPC_LARGE_PARAM_ID_MASK 0xFF
161 #define IPC_LARGE_PARAM_ID(x) (((x) & IPC_LARGE_PARAM_ID_MASK) \
162 << IPC_LARGE_PARAM_ID_SHIFT)
163
164 #define IPC_FINAL_BLOCK_SHIFT 28
165 #define IPC_FINAL_BLOCK_MASK 0x1
166 #define IPC_FINAL_BLOCK(x) (((x) & IPC_FINAL_BLOCK_MASK) \
167 << IPC_FINAL_BLOCK_SHIFT)
168
169 #define IPC_INITIAL_BLOCK_SHIFT 29
170 #define IPC_INITIAL_BLOCK_MASK 0x1
171 #define IPC_INITIAL_BLOCK(x) (((x) & IPC_INITIAL_BLOCK_MASK) \
172 << IPC_INITIAL_BLOCK_SHIFT)
173 #define IPC_INITIAL_BLOCK_CLEAR ~(IPC_INITIAL_BLOCK_MASK \
174 << IPC_INITIAL_BLOCK_SHIFT)
175
176 enum skl_ipc_msg_target {
177 IPC_FW_GEN_MSG = 0,
178 IPC_MOD_MSG = 1
179 };
180
181 enum skl_ipc_msg_direction {
182 IPC_MSG_REQUEST = 0,
183 IPC_MSG_REPLY = 1
184 };
185
186 /* Global Message Types */
187 enum skl_ipc_glb_type {
188 IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
189 IPC_GLB_LOAD_MULTIPLE_MODS = 15,
190 IPC_GLB_UNLOAD_MULTIPLE_MODS = 16,
191 IPC_GLB_CREATE_PPL = 17,
192 IPC_GLB_DELETE_PPL = 18,
193 IPC_GLB_SET_PPL_STATE = 19,
194 IPC_GLB_GET_PPL_STATE = 20,
195 IPC_GLB_GET_PPL_CONTEXT_SIZE = 21,
196 IPC_GLB_SAVE_PPL = 22,
197 IPC_GLB_RESTORE_PPL = 23,
198 IPC_GLB_LOAD_LIBRARY = 24,
199 IPC_GLB_NOTIFY = 26,
200 IPC_GLB_MAX_IPC_MSG_NUMBER = 31 /* Maximum message number */
201 };
202
203 enum skl_ipc_glb_reply {
204 IPC_GLB_REPLY_SUCCESS = 0,
205
206 IPC_GLB_REPLY_UNKNOWN_MSG_TYPE = 1,
207 IPC_GLB_REPLY_ERROR_INVALID_PARAM = 2,
208
209 IPC_GLB_REPLY_BUSY = 3,
210 IPC_GLB_REPLY_PENDING = 4,
211 IPC_GLB_REPLY_FAILURE = 5,
212 IPC_GLB_REPLY_INVALID_REQUEST = 6,
213
214 IPC_GLB_REPLY_OUT_OF_MEMORY = 7,
215 IPC_GLB_REPLY_OUT_OF_MIPS = 8,
216
217 IPC_GLB_REPLY_INVALID_RESOURCE_ID = 9,
218 IPC_GLB_REPLY_INVALID_RESOURCE_STATE = 10,
219
220 IPC_GLB_REPLY_MOD_MGMT_ERROR = 100,
221 IPC_GLB_REPLY_MOD_LOAD_CL_FAILED = 101,
222 IPC_GLB_REPLY_MOD_LOAD_INVALID_HASH = 102,
223
224 IPC_GLB_REPLY_MOD_UNLOAD_INST_EXIST = 103,
225 IPC_GLB_REPLY_MOD_NOT_INITIALIZED = 104,
226
227 IPC_GLB_REPLY_INVALID_CONFIG_PARAM_ID = 120,
228 IPC_GLB_REPLY_INVALID_CONFIG_DATA_LEN = 121,
229 IPC_GLB_REPLY_GATEWAY_NOT_INITIALIZED = 140,
230 IPC_GLB_REPLY_GATEWAY_NOT_EXIST = 141,
231
232 IPC_GLB_REPLY_PPL_NOT_INITIALIZED = 160,
233 IPC_GLB_REPLY_PPL_NOT_EXIST = 161,
234 IPC_GLB_REPLY_PPL_SAVE_FAILED = 162,
235 IPC_GLB_REPLY_PPL_RESTORE_FAILED = 163,
236
237 IPC_MAX_STATUS = ((1<<IPC_IXC_STATUS_BITS)-1)
238 };
239
240 enum skl_ipc_notification_type {
241 IPC_GLB_NOTIFY_GLITCH = 0,
242 IPC_GLB_NOTIFY_OVERRUN = 1,
243 IPC_GLB_NOTIFY_UNDERRUN = 2,
244 IPC_GLB_NOTIFY_END_STREAM = 3,
245 IPC_GLB_NOTIFY_PHRASE_DETECTED = 4,
246 IPC_GLB_NOTIFY_RESOURCE_EVENT = 5,
247 IPC_GLB_NOTIFY_LOG_BUFFER_STATUS = 6,
248 IPC_GLB_NOTIFY_TIMESTAMP_CAPTURED = 7,
249 IPC_GLB_NOTIFY_FW_READY = 8
250 };
251
252 /* Module Message Types */
253 enum skl_ipc_module_msg {
254 IPC_MOD_INIT_INSTANCE = 0,
255 IPC_MOD_CONFIG_GET = 1,
256 IPC_MOD_CONFIG_SET = 2,
257 IPC_MOD_LARGE_CONFIG_GET = 3,
258 IPC_MOD_LARGE_CONFIG_SET = 4,
259 IPC_MOD_BIND = 5,
260 IPC_MOD_UNBIND = 6,
261 IPC_MOD_SET_DX = 7
262 };
263
skl_ipc_tx_data_copy(struct ipc_message * msg,char * tx_data,size_t tx_size)264 static void skl_ipc_tx_data_copy(struct ipc_message *msg, char *tx_data,
265 size_t tx_size)
266 {
267 if (tx_size)
268 memcpy(msg->tx_data, tx_data, tx_size);
269 }
270
skl_ipc_is_dsp_busy(struct sst_dsp * dsp)271 static bool skl_ipc_is_dsp_busy(struct sst_dsp *dsp)
272 {
273 u32 hipci;
274
275 hipci = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCI);
276 return (hipci & SKL_ADSP_REG_HIPCI_BUSY);
277 }
278
279 /* Lock to be held by caller */
skl_ipc_tx_msg(struct sst_generic_ipc * ipc,struct ipc_message * msg)280 static void skl_ipc_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
281 {
282 struct skl_ipc_header *header = (struct skl_ipc_header *)(&msg->header);
283
284 if (msg->tx_size)
285 sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size);
286 sst_dsp_shim_write_unlocked(ipc->dsp, SKL_ADSP_REG_HIPCIE,
287 header->extension);
288 sst_dsp_shim_write_unlocked(ipc->dsp, SKL_ADSP_REG_HIPCI,
289 header->primary | SKL_ADSP_REG_HIPCI_BUSY);
290 }
291
skl_ipc_reply_get_msg(struct sst_generic_ipc * ipc,u64 ipc_header)292 static struct ipc_message *skl_ipc_reply_get_msg(struct sst_generic_ipc *ipc,
293 u64 ipc_header)
294 {
295 struct ipc_message *msg = NULL;
296 struct skl_ipc_header *header = (struct skl_ipc_header *)(&ipc_header);
297
298 if (list_empty(&ipc->rx_list)) {
299 dev_err(ipc->dev, "ipc: rx list is empty but received 0x%x\n",
300 header->primary);
301 goto out;
302 }
303
304 msg = list_first_entry(&ipc->rx_list, struct ipc_message, list);
305
306 out:
307 return msg;
308
309 }
310
skl_ipc_process_notification(struct sst_generic_ipc * ipc,struct skl_ipc_header header)311 static int skl_ipc_process_notification(struct sst_generic_ipc *ipc,
312 struct skl_ipc_header header)
313 {
314 struct skl_sst *skl = container_of(ipc, struct skl_sst, ipc);
315
316 if (IPC_GLB_NOTIFY_MSG_TYPE(header.primary)) {
317 switch (IPC_GLB_NOTIFY_TYPE(header.primary)) {
318
319 case IPC_GLB_NOTIFY_UNDERRUN:
320 dev_err(ipc->dev, "FW Underrun %x\n", header.primary);
321 break;
322
323 case IPC_GLB_NOTIFY_RESOURCE_EVENT:
324 dev_err(ipc->dev, "MCPS Budget Violation: %x\n",
325 header.primary);
326 break;
327
328 case IPC_GLB_NOTIFY_FW_READY:
329 skl->boot_complete = true;
330 wake_up(&skl->boot_wait);
331 break;
332
333 case IPC_GLB_NOTIFY_PHRASE_DETECTED:
334 dev_dbg(ipc->dev, "***** Phrase Detected **********\n");
335
336 /*
337 * Per HW recomendation, After phrase detection,
338 * clear the CGCTL.MISCBDCGE.
339 *
340 * This will be set back on stream closure
341 */
342 skl->enable_miscbdcge(ipc->dev, false);
343 skl->miscbdcg_disabled = true;
344 break;
345
346 default:
347 dev_err(ipc->dev, "ipc: Unhandled error msg=%x\n",
348 header.primary);
349 break;
350 }
351 }
352
353 return 0;
354 }
355
skl_ipc_process_reply(struct sst_generic_ipc * ipc,struct skl_ipc_header header)356 static void skl_ipc_process_reply(struct sst_generic_ipc *ipc,
357 struct skl_ipc_header header)
358 {
359 struct ipc_message *msg;
360 u32 reply = header.primary & IPC_GLB_REPLY_STATUS_MASK;
361 u64 *ipc_header = (u64 *)(&header);
362
363 msg = skl_ipc_reply_get_msg(ipc, *ipc_header);
364 if (msg == NULL) {
365 dev_dbg(ipc->dev, "ipc: rx list is empty\n");
366 return;
367 }
368
369 /* first process the header */
370 switch (reply) {
371 case IPC_GLB_REPLY_SUCCESS:
372 dev_dbg(ipc->dev, "ipc FW reply %x: success\n", header.primary);
373 /* copy the rx data from the mailbox */
374 sst_dsp_inbox_read(ipc->dsp, msg->rx_data, msg->rx_size);
375 break;
376
377 case IPC_GLB_REPLY_OUT_OF_MEMORY:
378 dev_err(ipc->dev, "ipc fw reply: %x: no memory\n", header.primary);
379 msg->errno = -ENOMEM;
380 break;
381
382 case IPC_GLB_REPLY_BUSY:
383 dev_err(ipc->dev, "ipc fw reply: %x: Busy\n", header.primary);
384 msg->errno = -EBUSY;
385 break;
386
387 default:
388 dev_err(ipc->dev, "Unknown ipc reply: 0x%x\n", reply);
389 msg->errno = -EINVAL;
390 break;
391 }
392
393 if (reply != IPC_GLB_REPLY_SUCCESS) {
394 dev_err(ipc->dev, "ipc FW reply: reply=%d\n", reply);
395 dev_err(ipc->dev, "FW Error Code: %u\n",
396 ipc->dsp->fw_ops.get_fw_errcode(ipc->dsp));
397 }
398
399 list_del(&msg->list);
400 sst_ipc_tx_msg_reply_complete(ipc, msg);
401 }
402
skl_dsp_irq_thread_handler(int irq,void * context)403 irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context)
404 {
405 struct sst_dsp *dsp = context;
406 struct skl_sst *skl = sst_dsp_get_thread_context(dsp);
407 struct sst_generic_ipc *ipc = &skl->ipc;
408 struct skl_ipc_header header = {0};
409 u32 hipcie, hipct, hipcte;
410 int ipc_irq = 0;
411
412 if (dsp->intr_status & SKL_ADSPIS_CL_DMA)
413 skl_cldma_process_intr(dsp);
414
415 /* Here we handle IPC interrupts only */
416 if (!(dsp->intr_status & SKL_ADSPIS_IPC))
417 return IRQ_NONE;
418
419 hipcie = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCIE);
420 hipct = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCT);
421
422 /* reply message from DSP */
423 if (hipcie & SKL_ADSP_REG_HIPCIE_DONE) {
424 sst_dsp_shim_update_bits(dsp, SKL_ADSP_REG_HIPCCTL,
425 SKL_ADSP_REG_HIPCCTL_DONE, 0);
426
427 /* clear DONE bit - tell DSP we have completed the operation */
428 sst_dsp_shim_update_bits_forced(dsp, SKL_ADSP_REG_HIPCIE,
429 SKL_ADSP_REG_HIPCIE_DONE, SKL_ADSP_REG_HIPCIE_DONE);
430
431 ipc_irq = 1;
432
433 /* unmask Done interrupt */
434 sst_dsp_shim_update_bits(dsp, SKL_ADSP_REG_HIPCCTL,
435 SKL_ADSP_REG_HIPCCTL_DONE, SKL_ADSP_REG_HIPCCTL_DONE);
436 }
437
438 /* New message from DSP */
439 if (hipct & SKL_ADSP_REG_HIPCT_BUSY) {
440 hipcte = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCTE);
441 header.primary = hipct;
442 header.extension = hipcte;
443 dev_dbg(dsp->dev, "IPC irq: Firmware respond primary:%x\n",
444 header.primary);
445 dev_dbg(dsp->dev, "IPC irq: Firmware respond extension:%x\n",
446 header.extension);
447
448 if (IPC_GLB_NOTIFY_RSP_TYPE(header.primary)) {
449 /* Handle Immediate reply from DSP Core */
450 skl_ipc_process_reply(ipc, header);
451 } else {
452 dev_dbg(dsp->dev, "IPC irq: Notification from firmware\n");
453 skl_ipc_process_notification(ipc, header);
454 }
455 /* clear busy interrupt */
456 sst_dsp_shim_update_bits_forced(dsp, SKL_ADSP_REG_HIPCT,
457 SKL_ADSP_REG_HIPCT_BUSY, SKL_ADSP_REG_HIPCT_BUSY);
458 ipc_irq = 1;
459 }
460
461 if (ipc_irq == 0)
462 return IRQ_NONE;
463
464 skl_ipc_int_enable(dsp);
465
466 /* continue to send any remaining messages... */
467 kthread_queue_work(&ipc->kworker, &ipc->kwork);
468
469 return IRQ_HANDLED;
470 }
471
skl_ipc_int_enable(struct sst_dsp * ctx)472 void skl_ipc_int_enable(struct sst_dsp *ctx)
473 {
474 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_ADSPIC,
475 SKL_ADSPIC_IPC, SKL_ADSPIC_IPC);
476 }
477
skl_ipc_int_disable(struct sst_dsp * ctx)478 void skl_ipc_int_disable(struct sst_dsp *ctx)
479 {
480 sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
481 SKL_ADSPIC_IPC, 0);
482 }
483
skl_ipc_op_int_enable(struct sst_dsp * ctx)484 void skl_ipc_op_int_enable(struct sst_dsp *ctx)
485 {
486 /* enable IPC DONE interrupt */
487 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCCTL,
488 SKL_ADSP_REG_HIPCCTL_DONE, SKL_ADSP_REG_HIPCCTL_DONE);
489
490 /* Enable IPC BUSY interrupt */
491 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCCTL,
492 SKL_ADSP_REG_HIPCCTL_BUSY, SKL_ADSP_REG_HIPCCTL_BUSY);
493 }
494
skl_ipc_op_int_disable(struct sst_dsp * ctx)495 void skl_ipc_op_int_disable(struct sst_dsp *ctx)
496 {
497 /* disable IPC DONE interrupt */
498 sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_HIPCCTL,
499 SKL_ADSP_REG_HIPCCTL_DONE, 0);
500
501 /* Disable IPC BUSY interrupt */
502 sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_HIPCCTL,
503 SKL_ADSP_REG_HIPCCTL_BUSY, 0);
504
505 }
506
skl_ipc_int_status(struct sst_dsp * ctx)507 bool skl_ipc_int_status(struct sst_dsp *ctx)
508 {
509 return sst_dsp_shim_read_unlocked(ctx,
510 SKL_ADSP_REG_ADSPIS) & SKL_ADSPIS_IPC;
511 }
512
skl_ipc_init(struct device * dev,struct skl_sst * skl)513 int skl_ipc_init(struct device *dev, struct skl_sst *skl)
514 {
515 struct sst_generic_ipc *ipc;
516 int err;
517
518 ipc = &skl->ipc;
519 ipc->dsp = skl->dsp;
520 ipc->dev = dev;
521
522 ipc->tx_data_max_size = SKL_ADSP_W1_SZ;
523 ipc->rx_data_max_size = SKL_ADSP_W0_UP_SZ;
524
525 err = sst_ipc_init(ipc);
526 if (err)
527 return err;
528
529 ipc->ops.tx_msg = skl_ipc_tx_msg;
530 ipc->ops.tx_data_copy = skl_ipc_tx_data_copy;
531 ipc->ops.is_dsp_busy = skl_ipc_is_dsp_busy;
532
533 return 0;
534 }
535
skl_ipc_free(struct sst_generic_ipc * ipc)536 void skl_ipc_free(struct sst_generic_ipc *ipc)
537 {
538 /* Disable IPC DONE interrupt */
539 sst_dsp_shim_update_bits(ipc->dsp, SKL_ADSP_REG_HIPCCTL,
540 SKL_ADSP_REG_HIPCCTL_DONE, 0);
541
542 /* Disable IPC BUSY interrupt */
543 sst_dsp_shim_update_bits(ipc->dsp, SKL_ADSP_REG_HIPCCTL,
544 SKL_ADSP_REG_HIPCCTL_BUSY, 0);
545
546 sst_ipc_fini(ipc);
547 }
548
skl_ipc_create_pipeline(struct sst_generic_ipc * ipc,u16 ppl_mem_size,u8 ppl_type,u8 instance_id)549 int skl_ipc_create_pipeline(struct sst_generic_ipc *ipc,
550 u16 ppl_mem_size, u8 ppl_type, u8 instance_id)
551 {
552 struct skl_ipc_header header = {0};
553 u64 *ipc_header = (u64 *)(&header);
554 int ret;
555
556 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
557 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
558 header.primary |= IPC_GLB_TYPE(IPC_GLB_CREATE_PPL);
559 header.primary |= IPC_INSTANCE_ID(instance_id);
560 header.primary |= IPC_PPL_TYPE(ppl_type);
561 header.primary |= IPC_PPL_MEM_SIZE(ppl_mem_size);
562
563 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
564 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
565 if (ret < 0) {
566 dev_err(ipc->dev, "ipc: create pipeline fail, err: %d\n", ret);
567 return ret;
568 }
569
570 return ret;
571 }
572 EXPORT_SYMBOL_GPL(skl_ipc_create_pipeline);
573
skl_ipc_delete_pipeline(struct sst_generic_ipc * ipc,u8 instance_id)574 int skl_ipc_delete_pipeline(struct sst_generic_ipc *ipc, u8 instance_id)
575 {
576 struct skl_ipc_header header = {0};
577 u64 *ipc_header = (u64 *)(&header);
578 int ret;
579
580 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
581 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
582 header.primary |= IPC_GLB_TYPE(IPC_GLB_DELETE_PPL);
583 header.primary |= IPC_INSTANCE_ID(instance_id);
584
585 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
586 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
587 if (ret < 0) {
588 dev_err(ipc->dev, "ipc: delete pipeline failed, err %d\n", ret);
589 return ret;
590 }
591
592 return 0;
593 }
594 EXPORT_SYMBOL_GPL(skl_ipc_delete_pipeline);
595
skl_ipc_set_pipeline_state(struct sst_generic_ipc * ipc,u8 instance_id,enum skl_ipc_pipeline_state state)596 int skl_ipc_set_pipeline_state(struct sst_generic_ipc *ipc,
597 u8 instance_id, enum skl_ipc_pipeline_state state)
598 {
599 struct skl_ipc_header header = {0};
600 u64 *ipc_header = (u64 *)(&header);
601 int ret;
602
603 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
604 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
605 header.primary |= IPC_GLB_TYPE(IPC_GLB_SET_PPL_STATE);
606 header.primary |= IPC_INSTANCE_ID(instance_id);
607 header.primary |= IPC_PPL_STATE(state);
608
609 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
610 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
611 if (ret < 0) {
612 dev_err(ipc->dev, "ipc: set pipeline state failed, err: %d\n", ret);
613 return ret;
614 }
615 return ret;
616 }
617 EXPORT_SYMBOL_GPL(skl_ipc_set_pipeline_state);
618
619 int
skl_ipc_save_pipeline(struct sst_generic_ipc * ipc,u8 instance_id,int dma_id)620 skl_ipc_save_pipeline(struct sst_generic_ipc *ipc, u8 instance_id, int dma_id)
621 {
622 struct skl_ipc_header header = {0};
623 u64 *ipc_header = (u64 *)(&header);
624 int ret;
625
626 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
627 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
628 header.primary |= IPC_GLB_TYPE(IPC_GLB_SAVE_PPL);
629 header.primary |= IPC_INSTANCE_ID(instance_id);
630
631 header.extension = IPC_DMA_ID(dma_id);
632 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
633 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
634 if (ret < 0) {
635 dev_err(ipc->dev, "ipc: save pipeline failed, err: %d\n", ret);
636 return ret;
637 }
638
639 return ret;
640 }
641 EXPORT_SYMBOL_GPL(skl_ipc_save_pipeline);
642
skl_ipc_restore_pipeline(struct sst_generic_ipc * ipc,u8 instance_id)643 int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id)
644 {
645 struct skl_ipc_header header = {0};
646 u64 *ipc_header = (u64 *)(&header);
647 int ret;
648
649 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
650 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
651 header.primary |= IPC_GLB_TYPE(IPC_GLB_RESTORE_PPL);
652 header.primary |= IPC_INSTANCE_ID(instance_id);
653
654 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
655 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
656 if (ret < 0) {
657 dev_err(ipc->dev, "ipc: restore pipeline failed, err: %d\n", ret);
658 return ret;
659 }
660
661 return ret;
662 }
663 EXPORT_SYMBOL_GPL(skl_ipc_restore_pipeline);
664
skl_ipc_set_dx(struct sst_generic_ipc * ipc,u8 instance_id,u16 module_id,struct skl_ipc_dxstate_info * dx)665 int skl_ipc_set_dx(struct sst_generic_ipc *ipc, u8 instance_id,
666 u16 module_id, struct skl_ipc_dxstate_info *dx)
667 {
668 struct skl_ipc_header header = {0};
669 u64 *ipc_header = (u64 *)(&header);
670 int ret;
671
672 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
673 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
674 header.primary |= IPC_GLB_TYPE(IPC_MOD_SET_DX);
675 header.primary |= IPC_MOD_INSTANCE_ID(instance_id);
676 header.primary |= IPC_MOD_ID(module_id);
677
678 dev_dbg(ipc->dev, "In %s primary =%x ext=%x\n", __func__,
679 header.primary, header.extension);
680 ret = sst_ipc_tx_message_wait(ipc, *ipc_header,
681 dx, sizeof(*dx), NULL, 0);
682 if (ret < 0) {
683 dev_err(ipc->dev, "ipc: set dx failed, err %d\n", ret);
684 return ret;
685 }
686
687 return ret;
688 }
689 EXPORT_SYMBOL_GPL(skl_ipc_set_dx);
690
skl_ipc_init_instance(struct sst_generic_ipc * ipc,struct skl_ipc_init_instance_msg * msg,void * param_data)691 int skl_ipc_init_instance(struct sst_generic_ipc *ipc,
692 struct skl_ipc_init_instance_msg *msg, void *param_data)
693 {
694 struct skl_ipc_header header = {0};
695 u64 *ipc_header = (u64 *)(&header);
696 int ret;
697 u32 *buffer = (u32 *)param_data;
698 /* param_block_size must be in dwords */
699 u16 param_block_size = msg->param_data_size / sizeof(u32);
700
701 print_hex_dump_debug("Param data:", DUMP_PREFIX_NONE,
702 16, 4, buffer, param_block_size, false);
703
704 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
705 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
706 header.primary |= IPC_GLB_TYPE(IPC_MOD_INIT_INSTANCE);
707 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
708 header.primary |= IPC_MOD_ID(msg->module_id);
709
710 header.extension = IPC_CORE_ID(msg->core_id);
711 header.extension |= IPC_PPL_INSTANCE_ID(msg->ppl_instance_id);
712 header.extension |= IPC_PARAM_BLOCK_SIZE(param_block_size);
713 header.extension |= IPC_DOMAIN(msg->domain);
714
715 dev_dbg(ipc->dev, "In %s primary =%x ext=%x\n", __func__,
716 header.primary, header.extension);
717 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, param_data,
718 msg->param_data_size, NULL, 0);
719
720 if (ret < 0) {
721 dev_err(ipc->dev, "ipc: init instance failed\n");
722 return ret;
723 }
724
725 return ret;
726 }
727 EXPORT_SYMBOL_GPL(skl_ipc_init_instance);
728
skl_ipc_bind_unbind(struct sst_generic_ipc * ipc,struct skl_ipc_bind_unbind_msg * msg)729 int skl_ipc_bind_unbind(struct sst_generic_ipc *ipc,
730 struct skl_ipc_bind_unbind_msg *msg)
731 {
732 struct skl_ipc_header header = {0};
733 u64 *ipc_header = (u64 *)(&header);
734 u8 bind_unbind = msg->bind ? IPC_MOD_BIND : IPC_MOD_UNBIND;
735 int ret;
736
737 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
738 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
739 header.primary |= IPC_GLB_TYPE(bind_unbind);
740 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
741 header.primary |= IPC_MOD_ID(msg->module_id);
742
743 header.extension = IPC_DST_MOD_ID(msg->dst_module_id);
744 header.extension |= IPC_DST_MOD_INSTANCE_ID(msg->dst_instance_id);
745 header.extension |= IPC_DST_QUEUE(msg->dst_queue);
746 header.extension |= IPC_SRC_QUEUE(msg->src_queue);
747
748 dev_dbg(ipc->dev, "In %s hdr=%x ext=%x\n", __func__, header.primary,
749 header.extension);
750 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
751 if (ret < 0) {
752 dev_err(ipc->dev, "ipc: bind/unbind failed\n");
753 return ret;
754 }
755
756 return ret;
757 }
758 EXPORT_SYMBOL_GPL(skl_ipc_bind_unbind);
759
760 /*
761 * In order to load a module we need to send IPC to initiate that. DMA will
762 * performed to load the module memory. The FW supports multiple module load
763 * at single shot, so we can send IPC with N modules represented by
764 * module_cnt
765 */
skl_ipc_load_modules(struct sst_generic_ipc * ipc,u8 module_cnt,void * data)766 int skl_ipc_load_modules(struct sst_generic_ipc *ipc,
767 u8 module_cnt, void *data)
768 {
769 struct skl_ipc_header header = {0};
770 u64 *ipc_header = (u64 *)(&header);
771 int ret;
772
773 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
774 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
775 header.primary |= IPC_GLB_TYPE(IPC_GLB_LOAD_MULTIPLE_MODS);
776 header.primary |= IPC_LOAD_MODULE_CNT(module_cnt);
777
778 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, data,
779 (sizeof(u16) * module_cnt), NULL, 0);
780 if (ret < 0)
781 dev_err(ipc->dev, "ipc: load modules failed :%d\n", ret);
782
783 return ret;
784 }
785 EXPORT_SYMBOL_GPL(skl_ipc_load_modules);
786
skl_ipc_unload_modules(struct sst_generic_ipc * ipc,u8 module_cnt,void * data)787 int skl_ipc_unload_modules(struct sst_generic_ipc *ipc, u8 module_cnt,
788 void *data)
789 {
790 struct skl_ipc_header header = {0};
791 u64 *ipc_header = (u64 *)(&header);
792 int ret;
793
794 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
795 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
796 header.primary |= IPC_GLB_TYPE(IPC_GLB_UNLOAD_MULTIPLE_MODS);
797 header.primary |= IPC_LOAD_MODULE_CNT(module_cnt);
798
799 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, data,
800 (sizeof(u16) * module_cnt), NULL, 0);
801 if (ret < 0)
802 dev_err(ipc->dev, "ipc: unload modules failed :%d\n", ret);
803
804 return ret;
805 }
806 EXPORT_SYMBOL_GPL(skl_ipc_unload_modules);
807
skl_ipc_set_large_config(struct sst_generic_ipc * ipc,struct skl_ipc_large_config_msg * msg,u32 * param)808 int skl_ipc_set_large_config(struct sst_generic_ipc *ipc,
809 struct skl_ipc_large_config_msg *msg, u32 *param)
810 {
811 struct skl_ipc_header header = {0};
812 u64 *ipc_header = (u64 *)(&header);
813 int ret = 0;
814 size_t sz_remaining, tx_size, data_offset;
815
816 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
817 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
818 header.primary |= IPC_GLB_TYPE(IPC_MOD_LARGE_CONFIG_SET);
819 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
820 header.primary |= IPC_MOD_ID(msg->module_id);
821
822 header.extension = IPC_DATA_OFFSET_SZ(msg->param_data_size);
823 header.extension |= IPC_LARGE_PARAM_ID(msg->large_param_id);
824 header.extension |= IPC_FINAL_BLOCK(0);
825 header.extension |= IPC_INITIAL_BLOCK(1);
826
827 sz_remaining = msg->param_data_size;
828 data_offset = 0;
829 while (sz_remaining != 0) {
830 tx_size = sz_remaining > SKL_ADSP_W1_SZ
831 ? SKL_ADSP_W1_SZ : sz_remaining;
832 if (tx_size == sz_remaining)
833 header.extension |= IPC_FINAL_BLOCK(1);
834
835 dev_dbg(ipc->dev, "In %s primary=%#x ext=%#x\n", __func__,
836 header.primary, header.extension);
837 dev_dbg(ipc->dev, "transmitting offset: %#x, size: %#x\n",
838 (unsigned)data_offset, (unsigned)tx_size);
839 ret = sst_ipc_tx_message_wait(ipc, *ipc_header,
840 ((char *)param) + data_offset,
841 tx_size, NULL, 0);
842 if (ret < 0) {
843 dev_err(ipc->dev,
844 "ipc: set large config fail, err: %d\n", ret);
845 return ret;
846 }
847 sz_remaining -= tx_size;
848 data_offset = msg->param_data_size - sz_remaining;
849
850 /* clear the fields */
851 header.extension &= IPC_INITIAL_BLOCK_CLEAR;
852 header.extension &= IPC_DATA_OFFSET_SZ_CLEAR;
853 /* fill the fields */
854 header.extension |= IPC_INITIAL_BLOCK(0);
855 header.extension |= IPC_DATA_OFFSET_SZ(data_offset);
856 }
857
858 return ret;
859 }
860 EXPORT_SYMBOL_GPL(skl_ipc_set_large_config);
861
skl_ipc_get_large_config(struct sst_generic_ipc * ipc,struct skl_ipc_large_config_msg * msg,u32 * param)862 int skl_ipc_get_large_config(struct sst_generic_ipc *ipc,
863 struct skl_ipc_large_config_msg *msg, u32 *param)
864 {
865 struct skl_ipc_header header = {0};
866 u64 *ipc_header = (u64 *)(&header);
867 int ret = 0;
868 size_t sz_remaining, rx_size, data_offset;
869
870 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
871 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
872 header.primary |= IPC_GLB_TYPE(IPC_MOD_LARGE_CONFIG_GET);
873 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
874 header.primary |= IPC_MOD_ID(msg->module_id);
875
876 header.extension = IPC_DATA_OFFSET_SZ(msg->param_data_size);
877 header.extension |= IPC_LARGE_PARAM_ID(msg->large_param_id);
878 header.extension |= IPC_FINAL_BLOCK(1);
879 header.extension |= IPC_INITIAL_BLOCK(1);
880
881 sz_remaining = msg->param_data_size;
882 data_offset = 0;
883
884 while (sz_remaining != 0) {
885 rx_size = sz_remaining > SKL_ADSP_W1_SZ
886 ? SKL_ADSP_W1_SZ : sz_remaining;
887 if (rx_size == sz_remaining)
888 header.extension |= IPC_FINAL_BLOCK(1);
889
890 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0,
891 ((char *)param) + data_offset,
892 msg->param_data_size);
893 if (ret < 0) {
894 dev_err(ipc->dev,
895 "ipc: get large config fail, err: %d\n", ret);
896 return ret;
897 }
898 sz_remaining -= rx_size;
899 data_offset = msg->param_data_size - sz_remaining;
900
901 /* clear the fields */
902 header.extension &= IPC_INITIAL_BLOCK_CLEAR;
903 header.extension &= IPC_DATA_OFFSET_SZ_CLEAR;
904 /* fill the fields */
905 header.extension |= IPC_INITIAL_BLOCK(1);
906 header.extension |= IPC_DATA_OFFSET_SZ(data_offset);
907 }
908
909 return ret;
910 }
911 EXPORT_SYMBOL_GPL(skl_ipc_get_large_config);
912
skl_sst_ipc_load_library(struct sst_generic_ipc * ipc,u8 dma_id,u8 table_id)913 int skl_sst_ipc_load_library(struct sst_generic_ipc *ipc,
914 u8 dma_id, u8 table_id)
915 {
916 struct skl_ipc_header header = {0};
917 u64 *ipc_header = (u64 *)(&header);
918 int ret = 0;
919
920 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
921 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
922 header.primary |= IPC_GLB_TYPE(IPC_GLB_LOAD_LIBRARY);
923 header.primary |= IPC_MOD_INSTANCE_ID(table_id);
924 header.primary |= IPC_MOD_ID(dma_id);
925
926 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
927
928 if (ret < 0)
929 dev_err(ipc->dev, "ipc: load lib failed\n");
930
931 return ret;
932 }
933 EXPORT_SYMBOL_GPL(skl_sst_ipc_load_library);
934