1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <drm/amdgpu_drm.h>
27 #include "pp_instance.h"
28 #include "smumgr.h"
29 #include "cgs_common.h"
30 #include "linux/delay.h"
31
32
smum_init(struct amd_pp_init * pp_init,struct pp_instance * handle)33 int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
34 {
35 struct pp_smumgr *smumgr;
36
37 if ((handle == NULL) || (pp_init == NULL))
38 return -EINVAL;
39
40 smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL);
41 if (smumgr == NULL)
42 return -ENOMEM;
43
44 smumgr->device = pp_init->device;
45 smumgr->chip_family = pp_init->chip_family;
46 smumgr->chip_id = pp_init->chip_id;
47 smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
48 smumgr->reload_fw = 1;
49 handle->smu_mgr = smumgr;
50
51 switch (smumgr->chip_family) {
52 case AMDGPU_FAMILY_CZ:
53 cz_smum_init(smumgr);
54 break;
55 case AMDGPU_FAMILY_VI:
56 switch (smumgr->chip_id) {
57 case CHIP_TOPAZ:
58 iceland_smum_init(smumgr);
59 break;
60 case CHIP_TONGA:
61 tonga_smum_init(smumgr);
62 break;
63 case CHIP_FIJI:
64 fiji_smum_init(smumgr);
65 break;
66 case CHIP_POLARIS11:
67 case CHIP_POLARIS10:
68 polaris10_smum_init(smumgr);
69 break;
70 default:
71 return -EINVAL;
72 }
73 break;
74 default:
75 kfree(smumgr);
76 return -EINVAL;
77 }
78
79 return 0;
80 }
81
smum_fini(struct pp_smumgr * smumgr)82 int smum_fini(struct pp_smumgr *smumgr)
83 {
84 kfree(smumgr->device);
85 kfree(smumgr);
86 return 0;
87 }
88
smum_thermal_avfs_enable(struct pp_hwmgr * hwmgr,void * input,void * output,void * storage,int result)89 int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
90 void *input, void *output, void *storage, int result)
91 {
92 if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable)
93 return hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable(hwmgr);
94
95 return 0;
96 }
97
smum_thermal_setup_fan_table(struct pp_hwmgr * hwmgr,void * input,void * output,void * storage,int result)98 int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
99 void *input, void *output, void *storage, int result)
100 {
101 if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table)
102 return hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table(hwmgr);
103
104 return 0;
105 }
106
smum_update_sclk_threshold(struct pp_hwmgr * hwmgr)107 int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr)
108 {
109
110 if (NULL != hwmgr->smumgr->smumgr_funcs->update_sclk_threshold)
111 return hwmgr->smumgr->smumgr_funcs->update_sclk_threshold(hwmgr);
112
113 return 0;
114 }
115
smum_update_smc_table(struct pp_hwmgr * hwmgr,uint32_t type)116 int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
117 {
118
119 if (NULL != hwmgr->smumgr->smumgr_funcs->update_smc_table)
120 return hwmgr->smumgr->smumgr_funcs->update_smc_table(hwmgr, type);
121
122 return 0;
123 }
124
smum_get_offsetof(struct pp_smumgr * smumgr,uint32_t type,uint32_t member)125 uint32_t smum_get_offsetof(struct pp_smumgr *smumgr, uint32_t type, uint32_t member)
126 {
127 if (NULL != smumgr->smumgr_funcs->get_offsetof)
128 return smumgr->smumgr_funcs->get_offsetof(type, member);
129
130 return 0;
131 }
132
smum_process_firmware_header(struct pp_hwmgr * hwmgr)133 int smum_process_firmware_header(struct pp_hwmgr *hwmgr)
134 {
135 if (NULL != hwmgr->smumgr->smumgr_funcs->process_firmware_header)
136 return hwmgr->smumgr->smumgr_funcs->process_firmware_header(hwmgr);
137 return 0;
138 }
139
smum_get_argument(struct pp_smumgr * smumgr)140 int smum_get_argument(struct pp_smumgr *smumgr)
141 {
142 if (NULL != smumgr->smumgr_funcs->get_argument)
143 return smumgr->smumgr_funcs->get_argument(smumgr);
144
145 return 0;
146 }
147
smum_get_mac_definition(struct pp_smumgr * smumgr,uint32_t value)148 uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value)
149 {
150 if (NULL != smumgr->smumgr_funcs->get_mac_definition)
151 return smumgr->smumgr_funcs->get_mac_definition(value);
152
153 return 0;
154 }
155
smum_download_powerplay_table(struct pp_smumgr * smumgr,void ** table)156 int smum_download_powerplay_table(struct pp_smumgr *smumgr,
157 void **table)
158 {
159 if (NULL != smumgr->smumgr_funcs->download_pptable_settings)
160 return smumgr->smumgr_funcs->download_pptable_settings(smumgr,
161 table);
162 return 0;
163 }
164
smum_upload_powerplay_table(struct pp_smumgr * smumgr)165 int smum_upload_powerplay_table(struct pp_smumgr *smumgr)
166 {
167 if (NULL != smumgr->smumgr_funcs->upload_pptable_settings)
168 return smumgr->smumgr_funcs->upload_pptable_settings(smumgr);
169
170 return 0;
171 }
172
smum_send_msg_to_smc(struct pp_smumgr * smumgr,uint16_t msg)173 int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
174 {
175 if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL)
176 return -EINVAL;
177
178 return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg);
179 }
180
smum_send_msg_to_smc_with_parameter(struct pp_smumgr * smumgr,uint16_t msg,uint32_t parameter)181 int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
182 uint16_t msg, uint32_t parameter)
183 {
184 if (smumgr == NULL ||
185 smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
186 return -EINVAL;
187 return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter(
188 smumgr, msg, parameter);
189 }
190
191 /*
192 * Returns once the part of the register indicated by the mask has
193 * reached the given value.
194 */
smum_wait_on_register(struct pp_smumgr * smumgr,uint32_t index,uint32_t value,uint32_t mask)195 int smum_wait_on_register(struct pp_smumgr *smumgr,
196 uint32_t index,
197 uint32_t value, uint32_t mask)
198 {
199 uint32_t i;
200 uint32_t cur_value;
201
202 if (smumgr == NULL || smumgr->device == NULL)
203 return -EINVAL;
204
205 for (i = 0; i < smumgr->usec_timeout; i++) {
206 cur_value = cgs_read_register(smumgr->device, index);
207 if ((cur_value & mask) == (value & mask))
208 break;
209 udelay(1);
210 }
211
212 /* timeout means wrong logic*/
213 if (i == smumgr->usec_timeout)
214 return -1;
215
216 return 0;
217 }
218
smum_wait_for_register_unequal(struct pp_smumgr * smumgr,uint32_t index,uint32_t value,uint32_t mask)219 int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
220 uint32_t index,
221 uint32_t value, uint32_t mask)
222 {
223 uint32_t i;
224 uint32_t cur_value;
225
226 if (smumgr == NULL)
227 return -EINVAL;
228
229 for (i = 0; i < smumgr->usec_timeout; i++) {
230 cur_value = cgs_read_register(smumgr->device,
231 index);
232 if ((cur_value & mask) != (value & mask))
233 break;
234 udelay(1);
235 }
236
237 /* timeout means wrong logic */
238 if (i == smumgr->usec_timeout)
239 return -1;
240
241 return 0;
242 }
243
244
245 /*
246 * Returns once the part of the register indicated by the mask
247 * has reached the given value.The indirect space is described by
248 * giving the memory-mapped index of the indirect index register.
249 */
smum_wait_on_indirect_register(struct pp_smumgr * smumgr,uint32_t indirect_port,uint32_t index,uint32_t value,uint32_t mask)250 int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
251 uint32_t indirect_port,
252 uint32_t index,
253 uint32_t value,
254 uint32_t mask)
255 {
256 if (smumgr == NULL || smumgr->device == NULL)
257 return -EINVAL;
258
259 cgs_write_register(smumgr->device, indirect_port, index);
260 return smum_wait_on_register(smumgr, indirect_port + 1,
261 mask, value);
262 }
263
smum_wait_for_indirect_register_unequal(struct pp_smumgr * smumgr,uint32_t indirect_port,uint32_t index,uint32_t value,uint32_t mask)264 void smum_wait_for_indirect_register_unequal(
265 struct pp_smumgr *smumgr,
266 uint32_t indirect_port,
267 uint32_t index,
268 uint32_t value,
269 uint32_t mask)
270 {
271 if (smumgr == NULL || smumgr->device == NULL)
272 return;
273 cgs_write_register(smumgr->device, indirect_port, index);
274 smum_wait_for_register_unequal(smumgr, indirect_port + 1,
275 value, mask);
276 }
277
smu_allocate_memory(void * device,uint32_t size,enum cgs_gpu_mem_type type,uint32_t byte_align,uint64_t * mc_addr,void ** kptr,void * handle)278 int smu_allocate_memory(void *device, uint32_t size,
279 enum cgs_gpu_mem_type type,
280 uint32_t byte_align, uint64_t *mc_addr,
281 void **kptr, void *handle)
282 {
283 int ret = 0;
284 cgs_handle_t cgs_handle;
285
286 if (device == NULL || handle == NULL ||
287 mc_addr == NULL || kptr == NULL)
288 return -EINVAL;
289
290 ret = cgs_alloc_gpu_mem(device, type, size, byte_align,
291 0, 0, (cgs_handle_t *)handle);
292 if (ret)
293 return -ENOMEM;
294
295 cgs_handle = *(cgs_handle_t *)handle;
296
297 ret = cgs_gmap_gpu_mem(device, cgs_handle, mc_addr);
298 if (ret)
299 goto error_gmap;
300
301 ret = cgs_kmap_gpu_mem(device, cgs_handle, kptr);
302 if (ret)
303 goto error_kmap;
304
305 return 0;
306
307 error_kmap:
308 cgs_gunmap_gpu_mem(device, cgs_handle);
309
310 error_gmap:
311 cgs_free_gpu_mem(device, cgs_handle);
312 return ret;
313 }
314
smu_free_memory(void * device,void * handle)315 int smu_free_memory(void *device, void *handle)
316 {
317 cgs_handle_t cgs_handle = (cgs_handle_t)handle;
318
319 if (device == NULL || handle == NULL)
320 return -EINVAL;
321
322 cgs_kunmap_gpu_mem(device, cgs_handle);
323 cgs_gunmap_gpu_mem(device, cgs_handle);
324 cgs_free_gpu_mem(device, cgs_handle);
325
326 return 0;
327 }
328
smum_init_smc_table(struct pp_hwmgr * hwmgr)329 int smum_init_smc_table(struct pp_hwmgr *hwmgr)
330 {
331 if (NULL != hwmgr->smumgr->smumgr_funcs->init_smc_table)
332 return hwmgr->smumgr->smumgr_funcs->init_smc_table(hwmgr);
333
334 return 0;
335 }
336
smum_populate_all_graphic_levels(struct pp_hwmgr * hwmgr)337 int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
338 {
339 if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels)
340 return hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels(hwmgr);
341
342 return 0;
343 }
344
smum_populate_all_memory_levels(struct pp_hwmgr * hwmgr)345 int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
346 {
347 if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels)
348 return hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels(hwmgr);
349
350 return 0;
351 }
352
353 /*this interface is needed by island ci/vi */
smum_initialize_mc_reg_table(struct pp_hwmgr * hwmgr)354 int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
355 {
356 if (NULL != hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table)
357 return hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table(hwmgr);
358
359 return 0;
360 }
361
smum_is_dpm_running(struct pp_hwmgr * hwmgr)362 bool smum_is_dpm_running(struct pp_hwmgr *hwmgr)
363 {
364 if (NULL != hwmgr->smumgr->smumgr_funcs->is_dpm_running)
365 return hwmgr->smumgr->smumgr_funcs->is_dpm_running(hwmgr);
366
367 return true;
368 }
369