1 /*
2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
4 *
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
7 *
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
19 #include <linux/sizes.h>
20
21 #include <linux/mtd/mtd.h>
22 #include <linux/of_platform.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/spi-nor.h>
25
26 /* Define max times to check status register before we give up. */
27
28 /*
29 * For everything but full-chip erase; probably could be much smaller, but kept
30 * around for safety for now
31 */
32 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
33
34 /*
35 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
36 * for larger flash
37 */
38 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
39
40 #define SPI_NOR_MAX_ID_LEN 6
41 #define SPI_NOR_MAX_ADDR_WIDTH 4
42
43 struct flash_info {
44 char *name;
45
46 /*
47 * This array stores the ID bytes.
48 * The first three bytes are the JEDIC ID.
49 * JEDEC ID zero means "no ID" (mostly older chips).
50 */
51 u8 id[SPI_NOR_MAX_ID_LEN];
52 u8 id_len;
53
54 /* The size listed here is what works with SPINOR_OP_SE, which isn't
55 * necessarily called a "sector" by the vendor.
56 */
57 unsigned sector_size;
58 u16 n_sectors;
59
60 u16 page_size;
61 u16 addr_width;
62
63 u16 flags;
64 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
65 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
66 #define SST_WRITE BIT(2) /* use SST byte programming */
67 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
68 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
69 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
70 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
71 #define USE_FSR BIT(7) /* use flag status register */
72 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
73 #define SPI_NOR_HAS_TB BIT(9) /*
74 * Flash SR has Top/Bottom (TB) protect
75 * bit. Must be used with
76 * SPI_NOR_HAS_LOCK.
77 */
78 };
79
80 #define JEDEC_MFR(info) ((info)->id[0])
81
82 static const struct flash_info *spi_nor_match_id(const char *name);
83
84 /*
85 * Read the status register, returning its value in the location
86 * Return the status register value.
87 * Returns negative if error occurred.
88 */
read_sr(struct spi_nor * nor)89 static int read_sr(struct spi_nor *nor)
90 {
91 int ret;
92 u8 val;
93
94 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
95 if (ret < 0) {
96 pr_err("error %d reading SR\n", (int) ret);
97 return ret;
98 }
99
100 return val;
101 }
102
103 /*
104 * Read the flag status register, returning its value in the location
105 * Return the status register value.
106 * Returns negative if error occurred.
107 */
read_fsr(struct spi_nor * nor)108 static int read_fsr(struct spi_nor *nor)
109 {
110 int ret;
111 u8 val;
112
113 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
114 if (ret < 0) {
115 pr_err("error %d reading FSR\n", ret);
116 return ret;
117 }
118
119 return val;
120 }
121
122 /*
123 * Read configuration register, returning its value in the
124 * location. Return the configuration register value.
125 * Returns negative if error occured.
126 */
read_cr(struct spi_nor * nor)127 static int read_cr(struct spi_nor *nor)
128 {
129 int ret;
130 u8 val;
131
132 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
133 if (ret < 0) {
134 dev_err(nor->dev, "error %d reading CR\n", ret);
135 return ret;
136 }
137
138 return val;
139 }
140
141 /*
142 * Dummy Cycle calculation for different type of read.
143 * It can be used to support more commands with
144 * different dummy cycle requirements.
145 */
spi_nor_read_dummy_cycles(struct spi_nor * nor)146 static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
147 {
148 switch (nor->flash_read) {
149 case SPI_NOR_FAST:
150 case SPI_NOR_DUAL:
151 case SPI_NOR_QUAD:
152 return 8;
153 case SPI_NOR_NORMAL:
154 return 0;
155 }
156 return 0;
157 }
158
159 /*
160 * Write status register 1 byte
161 * Returns negative if error occurred.
162 */
write_sr(struct spi_nor * nor,u8 val)163 static inline int write_sr(struct spi_nor *nor, u8 val)
164 {
165 nor->cmd_buf[0] = val;
166 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
167 }
168
169 /*
170 * Set write enable latch with Write Enable command.
171 * Returns negative if error occurred.
172 */
write_enable(struct spi_nor * nor)173 static inline int write_enable(struct spi_nor *nor)
174 {
175 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
176 }
177
178 /*
179 * Send write disble instruction to the chip.
180 */
write_disable(struct spi_nor * nor)181 static inline int write_disable(struct spi_nor *nor)
182 {
183 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
184 }
185
mtd_to_spi_nor(struct mtd_info * mtd)186 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
187 {
188 return mtd->priv;
189 }
190
191 /* Enable/disable 4-byte addressing mode. */
set_4byte(struct spi_nor * nor,const struct flash_info * info,int enable)192 static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
193 int enable)
194 {
195 int status;
196 bool need_wren = false;
197 u8 cmd;
198
199 switch (JEDEC_MFR(info)) {
200 case SNOR_MFR_MICRON:
201 /* Some Micron need WREN command; all will accept it */
202 need_wren = true;
203 case SNOR_MFR_MACRONIX:
204 case SNOR_MFR_WINBOND:
205 if (need_wren)
206 write_enable(nor);
207
208 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
209 status = nor->write_reg(nor, cmd, NULL, 0);
210 if (need_wren)
211 write_disable(nor);
212
213 return status;
214 default:
215 /* Spansion style */
216 nor->cmd_buf[0] = enable << 7;
217 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
218 }
219 }
spi_nor_sr_ready(struct spi_nor * nor)220 static inline int spi_nor_sr_ready(struct spi_nor *nor)
221 {
222 int sr = read_sr(nor);
223 if (sr < 0)
224 return sr;
225 else
226 return !(sr & SR_WIP);
227 }
228
spi_nor_fsr_ready(struct spi_nor * nor)229 static inline int spi_nor_fsr_ready(struct spi_nor *nor)
230 {
231 int fsr = read_fsr(nor);
232 if (fsr < 0)
233 return fsr;
234 else
235 return fsr & FSR_READY;
236 }
237
spi_nor_ready(struct spi_nor * nor)238 static int spi_nor_ready(struct spi_nor *nor)
239 {
240 int sr, fsr;
241 sr = spi_nor_sr_ready(nor);
242 if (sr < 0)
243 return sr;
244 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
245 if (fsr < 0)
246 return fsr;
247 return sr && fsr;
248 }
249
250 /*
251 * Service routine to read status register until ready, or timeout occurs.
252 * Returns non-zero if error.
253 */
spi_nor_wait_till_ready_with_timeout(struct spi_nor * nor,unsigned long timeout_jiffies)254 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
255 unsigned long timeout_jiffies)
256 {
257 unsigned long deadline;
258 int timeout = 0, ret;
259
260 deadline = jiffies + timeout_jiffies;
261
262 while (!timeout) {
263 if (time_after_eq(jiffies, deadline))
264 timeout = 1;
265
266 ret = spi_nor_ready(nor);
267 if (ret < 0)
268 return ret;
269 if (ret)
270 return 0;
271
272 cond_resched();
273 }
274
275 dev_err(nor->dev, "flash operation timed out\n");
276
277 return -ETIMEDOUT;
278 }
279
spi_nor_wait_till_ready(struct spi_nor * nor)280 static int spi_nor_wait_till_ready(struct spi_nor *nor)
281 {
282 return spi_nor_wait_till_ready_with_timeout(nor,
283 DEFAULT_READY_WAIT_JIFFIES);
284 }
285
286 /*
287 * Erase the whole flash memory
288 *
289 * Returns 0 if successful, non-zero otherwise.
290 */
erase_chip(struct spi_nor * nor)291 static int erase_chip(struct spi_nor *nor)
292 {
293 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
294
295 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
296 }
297
spi_nor_lock_and_prep(struct spi_nor * nor,enum spi_nor_ops ops)298 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
299 {
300 int ret = 0;
301
302 mutex_lock(&nor->lock);
303
304 if (nor->prepare) {
305 ret = nor->prepare(nor, ops);
306 if (ret) {
307 dev_err(nor->dev, "failed in the preparation.\n");
308 mutex_unlock(&nor->lock);
309 return ret;
310 }
311 }
312 return ret;
313 }
314
spi_nor_unlock_and_unprep(struct spi_nor * nor,enum spi_nor_ops ops)315 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
316 {
317 if (nor->unprepare)
318 nor->unprepare(nor, ops);
319 mutex_unlock(&nor->lock);
320 }
321
322 /*
323 * Initiate the erasure of a single sector
324 */
spi_nor_erase_sector(struct spi_nor * nor,u32 addr)325 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
326 {
327 u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
328 int i;
329
330 if (nor->erase)
331 return nor->erase(nor, addr);
332
333 /*
334 * Default implementation, if driver doesn't have a specialized HW
335 * control
336 */
337 for (i = nor->addr_width - 1; i >= 0; i--) {
338 buf[i] = addr & 0xff;
339 addr >>= 8;
340 }
341
342 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
343 }
344
345 /*
346 * Erase an address range on the nor chip. The address range may extend
347 * one or more erase sectors. Return an error is there is a problem erasing.
348 */
spi_nor_erase(struct mtd_info * mtd,struct erase_info * instr)349 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
350 {
351 struct spi_nor *nor = mtd_to_spi_nor(mtd);
352 u32 addr, len;
353 uint32_t rem;
354 int ret;
355
356 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
357 (long long)instr->len);
358
359 div_u64_rem(instr->len, mtd->erasesize, &rem);
360 if (rem)
361 return -EINVAL;
362
363 addr = instr->addr;
364 len = instr->len;
365
366 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
367 if (ret)
368 return ret;
369
370 /* whole-chip erase? */
371 if (len == mtd->size) {
372 unsigned long timeout;
373
374 write_enable(nor);
375
376 if (erase_chip(nor)) {
377 ret = -EIO;
378 goto erase_err;
379 }
380
381 /*
382 * Scale the timeout linearly with the size of the flash, with
383 * a minimum calibrated to an old 2MB flash. We could try to
384 * pull these from CFI/SFDP, but these values should be good
385 * enough for now.
386 */
387 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
388 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
389 (unsigned long)(mtd->size / SZ_2M));
390 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
391 if (ret)
392 goto erase_err;
393
394 /* REVISIT in some cases we could speed up erasing large regions
395 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
396 * to use "small sector erase", but that's not always optimal.
397 */
398
399 /* "sector"-at-a-time erase */
400 } else {
401 while (len) {
402 write_enable(nor);
403
404 ret = spi_nor_erase_sector(nor, addr);
405 if (ret)
406 goto erase_err;
407
408 addr += mtd->erasesize;
409 len -= mtd->erasesize;
410
411 ret = spi_nor_wait_till_ready(nor);
412 if (ret)
413 goto erase_err;
414 }
415 }
416
417 write_disable(nor);
418
419 erase_err:
420 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
421
422 instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE;
423 mtd_erase_callback(instr);
424
425 return ret;
426 }
427
stm_get_locked_range(struct spi_nor * nor,u8 sr,loff_t * ofs,uint64_t * len)428 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
429 uint64_t *len)
430 {
431 struct mtd_info *mtd = &nor->mtd;
432 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
433 int shift = ffs(mask) - 1;
434 int pow;
435
436 if (!(sr & mask)) {
437 /* No protection */
438 *ofs = 0;
439 *len = 0;
440 } else {
441 pow = ((sr & mask) ^ mask) >> shift;
442 *len = mtd->size >> pow;
443 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
444 *ofs = 0;
445 else
446 *ofs = mtd->size - *len;
447 }
448 }
449
450 /*
451 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
452 * @locked is false); 0 otherwise
453 */
stm_check_lock_status_sr(struct spi_nor * nor,loff_t ofs,uint64_t len,u8 sr,bool locked)454 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
455 u8 sr, bool locked)
456 {
457 loff_t lock_offs;
458 uint64_t lock_len;
459
460 if (!len)
461 return 1;
462
463 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
464
465 if (locked)
466 /* Requested range is a sub-range of locked range */
467 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
468 else
469 /* Requested range does not overlap with locked range */
470 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
471 }
472
stm_is_locked_sr(struct spi_nor * nor,loff_t ofs,uint64_t len,u8 sr)473 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
474 u8 sr)
475 {
476 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
477 }
478
stm_is_unlocked_sr(struct spi_nor * nor,loff_t ofs,uint64_t len,u8 sr)479 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
480 u8 sr)
481 {
482 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
483 }
484
485 /*
486 * Lock a region of the flash. Compatible with ST Micro and similar flash.
487 * Supports the block protection bits BP{0,1,2} in the status register
488 * (SR). Does not support these features found in newer SR bitfields:
489 * - SEC: sector/block protect - only handle SEC=0 (block protect)
490 * - CMP: complement protect - only support CMP=0 (range is not complemented)
491 *
492 * Support for the following is provided conditionally for some flash:
493 * - TB: top/bottom protect
494 *
495 * Sample table portion for 8MB flash (Winbond w25q64fw):
496 *
497 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
498 * --------------------------------------------------------------------------
499 * X | X | 0 | 0 | 0 | NONE | NONE
500 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
501 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
502 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
503 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
504 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
505 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
506 * X | X | 1 | 1 | 1 | 8 MB | ALL
507 * ------|-------|-------|-------|-------|---------------|-------------------
508 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
509 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
510 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
511 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
512 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
513 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
514 *
515 * Returns negative on errors, 0 on success.
516 */
stm_lock(struct spi_nor * nor,loff_t ofs,uint64_t len)517 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
518 {
519 struct mtd_info *mtd = &nor->mtd;
520 int status_old, status_new;
521 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
522 u8 shift = ffs(mask) - 1, pow, val;
523 loff_t lock_len;
524 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
525 bool use_top;
526 int ret;
527
528 status_old = read_sr(nor);
529 if (status_old < 0)
530 return status_old;
531
532 /* If nothing in our range is unlocked, we don't need to do anything */
533 if (stm_is_locked_sr(nor, ofs, len, status_old))
534 return 0;
535
536 /* If anything below us is unlocked, we can't use 'bottom' protection */
537 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
538 can_be_bottom = false;
539
540 /* If anything above us is unlocked, we can't use 'top' protection */
541 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
542 status_old))
543 can_be_top = false;
544
545 if (!can_be_bottom && !can_be_top)
546 return -EINVAL;
547
548 /* Prefer top, if both are valid */
549 use_top = can_be_top;
550
551 /* lock_len: length of region that should end up locked */
552 if (use_top)
553 lock_len = mtd->size - ofs;
554 else
555 lock_len = ofs + len;
556
557 /*
558 * Need smallest pow such that:
559 *
560 * 1 / (2^pow) <= (len / size)
561 *
562 * so (assuming power-of-2 size) we do:
563 *
564 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
565 */
566 pow = ilog2(mtd->size) - ilog2(lock_len);
567 val = mask - (pow << shift);
568 if (val & ~mask)
569 return -EINVAL;
570 /* Don't "lock" with no region! */
571 if (!(val & mask))
572 return -EINVAL;
573
574 status_new = (status_old & ~mask & ~SR_TB) | val;
575
576 /* Disallow further writes if WP pin is asserted */
577 status_new |= SR_SRWD;
578
579 if (!use_top)
580 status_new |= SR_TB;
581
582 /* Don't bother if they're the same */
583 if (status_new == status_old)
584 return 0;
585
586 /* Only modify protection if it will not unlock other areas */
587 if ((status_new & mask) < (status_old & mask))
588 return -EINVAL;
589
590 write_enable(nor);
591 ret = write_sr(nor, status_new);
592 if (ret)
593 return ret;
594 return spi_nor_wait_till_ready(nor);
595 }
596
597 /*
598 * Unlock a region of the flash. See stm_lock() for more info
599 *
600 * Returns negative on errors, 0 on success.
601 */
stm_unlock(struct spi_nor * nor,loff_t ofs,uint64_t len)602 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
603 {
604 struct mtd_info *mtd = &nor->mtd;
605 int status_old, status_new;
606 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
607 u8 shift = ffs(mask) - 1, pow, val;
608 loff_t lock_len;
609 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
610 bool use_top;
611 int ret;
612
613 status_old = read_sr(nor);
614 if (status_old < 0)
615 return status_old;
616
617 /* If nothing in our range is locked, we don't need to do anything */
618 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
619 return 0;
620
621 /* If anything below us is locked, we can't use 'top' protection */
622 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
623 can_be_top = false;
624
625 /* If anything above us is locked, we can't use 'bottom' protection */
626 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
627 status_old))
628 can_be_bottom = false;
629
630 if (!can_be_bottom && !can_be_top)
631 return -EINVAL;
632
633 /* Prefer top, if both are valid */
634 use_top = can_be_top;
635
636 /* lock_len: length of region that should remain locked */
637 if (use_top)
638 lock_len = mtd->size - (ofs + len);
639 else
640 lock_len = ofs;
641
642 /*
643 * Need largest pow such that:
644 *
645 * 1 / (2^pow) >= (len / size)
646 *
647 * so (assuming power-of-2 size) we do:
648 *
649 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
650 */
651 pow = ilog2(mtd->size) - order_base_2(lock_len);
652 if (lock_len == 0) {
653 val = 0; /* fully unlocked */
654 } else {
655 val = mask - (pow << shift);
656 /* Some power-of-two sizes are not supported */
657 if (val & ~mask)
658 return -EINVAL;
659 }
660
661 status_new = (status_old & ~mask & ~SR_TB) | val;
662
663 /* Don't protect status register if we're fully unlocked */
664 if (lock_len == 0)
665 status_new &= ~SR_SRWD;
666
667 if (!use_top)
668 status_new |= SR_TB;
669
670 /* Don't bother if they're the same */
671 if (status_new == status_old)
672 return 0;
673
674 /* Only modify protection if it will not lock other areas */
675 if ((status_new & mask) > (status_old & mask))
676 return -EINVAL;
677
678 write_enable(nor);
679 ret = write_sr(nor, status_new);
680 if (ret)
681 return ret;
682 return spi_nor_wait_till_ready(nor);
683 }
684
685 /*
686 * Check if a region of the flash is (completely) locked. See stm_lock() for
687 * more info.
688 *
689 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
690 * negative on errors.
691 */
stm_is_locked(struct spi_nor * nor,loff_t ofs,uint64_t len)692 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
693 {
694 int status;
695
696 status = read_sr(nor);
697 if (status < 0)
698 return status;
699
700 return stm_is_locked_sr(nor, ofs, len, status);
701 }
702
spi_nor_lock(struct mtd_info * mtd,loff_t ofs,uint64_t len)703 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
704 {
705 struct spi_nor *nor = mtd_to_spi_nor(mtd);
706 int ret;
707
708 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
709 if (ret)
710 return ret;
711
712 ret = nor->flash_lock(nor, ofs, len);
713
714 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
715 return ret;
716 }
717
spi_nor_unlock(struct mtd_info * mtd,loff_t ofs,uint64_t len)718 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
719 {
720 struct spi_nor *nor = mtd_to_spi_nor(mtd);
721 int ret;
722
723 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
724 if (ret)
725 return ret;
726
727 ret = nor->flash_unlock(nor, ofs, len);
728
729 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
730 return ret;
731 }
732
spi_nor_is_locked(struct mtd_info * mtd,loff_t ofs,uint64_t len)733 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
734 {
735 struct spi_nor *nor = mtd_to_spi_nor(mtd);
736 int ret;
737
738 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
739 if (ret)
740 return ret;
741
742 ret = nor->flash_is_locked(nor, ofs, len);
743
744 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
745 return ret;
746 }
747
748 /* Used when the "_ext_id" is two bytes at most */
749 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
750 .id = { \
751 ((_jedec_id) >> 16) & 0xff, \
752 ((_jedec_id) >> 8) & 0xff, \
753 (_jedec_id) & 0xff, \
754 ((_ext_id) >> 8) & 0xff, \
755 (_ext_id) & 0xff, \
756 }, \
757 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
758 .sector_size = (_sector_size), \
759 .n_sectors = (_n_sectors), \
760 .page_size = 256, \
761 .flags = (_flags),
762
763 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
764 .id = { \
765 ((_jedec_id) >> 16) & 0xff, \
766 ((_jedec_id) >> 8) & 0xff, \
767 (_jedec_id) & 0xff, \
768 ((_ext_id) >> 16) & 0xff, \
769 ((_ext_id) >> 8) & 0xff, \
770 (_ext_id) & 0xff, \
771 }, \
772 .id_len = 6, \
773 .sector_size = (_sector_size), \
774 .n_sectors = (_n_sectors), \
775 .page_size = 256, \
776 .flags = (_flags),
777
778 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
779 .sector_size = (_sector_size), \
780 .n_sectors = (_n_sectors), \
781 .page_size = (_page_size), \
782 .addr_width = (_addr_width), \
783 .flags = (_flags),
784
785 /* NOTE: double check command sets and memory organization when you add
786 * more nor chips. This current list focusses on newer chips, which
787 * have been converging on command sets which including JEDEC ID.
788 *
789 * All newly added entries should describe *hardware* and should use SECT_4K
790 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
791 * scenarios excluding small sectors there is config option that can be
792 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
793 * For historical (and compatibility) reasons (before we got above config) some
794 * old entries may be missing 4K flag.
795 */
796 static const struct flash_info spi_nor_ids[] = {
797 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
798 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
799 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
800
801 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
802 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
803 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
804
805 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
806 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
807 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
808 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
809
810 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
811
812 /* EON -- en25xxx */
813 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
814 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
815 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
816 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
817 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
818 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
819 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
820 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
821
822 /* ESMT */
823 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
824
825 /* Everspin */
826 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
827 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
828
829 /* Fujitsu */
830 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
831
832 /* GigaDevice */
833 {
834 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
835 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
836 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
837 },
838 {
839 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
840 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
841 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
842 },
843 {
844 "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
845 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
846 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
847 },
848 {
849 "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
850 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
851 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
852 },
853
854 /* Intel/Numonyx -- xxxs33b */
855 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
856 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
857 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
858
859 /* ISSI */
860 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
861
862 /* Macronix */
863 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
864 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
865 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
866 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
867 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
868 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
869 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
870 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
871 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
872 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
873 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
874 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
875 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
876 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
877 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
878
879 /* Micron */
880 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
881 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
882 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
883 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
884 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
885 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
886 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
887 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
888 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
889 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
890 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
891
892 /* PMC */
893 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
894 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
895 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
896
897 /* Spansion -- single (large) sector size only, at least
898 * for the chips listed here (without boot sectors).
899 */
900 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
901 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
902 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
903 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
904 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
905 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
906 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
907 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
908 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
909 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
910 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
911 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
912 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
913 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
914 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
915 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
916 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
917 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
918 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
919 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
920 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
921 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
922 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
923 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
924
925 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
926 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
927 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
928 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
929 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
930 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
931 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
932 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
933 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
934 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
935 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
936 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
937 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
938
939 /* ST Microelectronics -- newer production may have feature updates */
940 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
941 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
942 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
943 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
944 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
945 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
946 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
947 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
948 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
949
950 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
951 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
952 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
953 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
954 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
955 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
956 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
957 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
958 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
959
960 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
961 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
962 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
963
964 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
965 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
966 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
967
968 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
969 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
970 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
971 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
972 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
973 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
974
975 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
976 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
977 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
978 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
979 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
980 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
981 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
982 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
983 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
984 {
985 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
986 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
987 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
988 },
989 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
990 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
991 {
992 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
993 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
994 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
995 },
996 {
997 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
998 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
999 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1000 },
1001 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
1002 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
1003 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1004 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
1005
1006 /* Catalyst / On Semiconductor -- non-JEDEC */
1007 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1008 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1009 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1010 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1011 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1012 { },
1013 };
1014
spi_nor_read_id(struct spi_nor * nor)1015 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
1016 {
1017 int tmp;
1018 u8 id[SPI_NOR_MAX_ID_LEN];
1019 const struct flash_info *info;
1020
1021 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
1022 if (tmp < 0) {
1023 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
1024 return ERR_PTR(tmp);
1025 }
1026
1027 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
1028 info = &spi_nor_ids[tmp];
1029 if (info->id_len) {
1030 if (!memcmp(info->id, id, info->id_len))
1031 return &spi_nor_ids[tmp];
1032 }
1033 }
1034 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1035 id[0], id[1], id[2]);
1036 return ERR_PTR(-ENODEV);
1037 }
1038
spi_nor_read(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1039 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1040 size_t *retlen, u_char *buf)
1041 {
1042 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1043 int ret;
1044
1045 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1046
1047 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
1048 if (ret)
1049 return ret;
1050
1051 while (len) {
1052 ret = nor->read(nor, from, len, buf);
1053 if (ret == 0) {
1054 /* We shouldn't see 0-length reads */
1055 ret = -EIO;
1056 goto read_err;
1057 }
1058 if (ret < 0)
1059 goto read_err;
1060
1061 WARN_ON(ret > len);
1062 *retlen += ret;
1063 buf += ret;
1064 from += ret;
1065 len -= ret;
1066 }
1067 ret = 0;
1068
1069 read_err:
1070 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
1071 return ret;
1072 }
1073
sst_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)1074 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1075 size_t *retlen, const u_char *buf)
1076 {
1077 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1078 size_t actual;
1079 int ret;
1080
1081 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1082
1083 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1084 if (ret)
1085 return ret;
1086
1087 write_enable(nor);
1088
1089 nor->sst_write_second = false;
1090
1091 actual = to % 2;
1092 /* Start write from odd address. */
1093 if (actual) {
1094 nor->program_opcode = SPINOR_OP_BP;
1095
1096 /* write one byte. */
1097 ret = nor->write(nor, to, 1, buf);
1098 if (ret < 0)
1099 goto sst_write_err;
1100 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
1101 (int)ret);
1102 ret = spi_nor_wait_till_ready(nor);
1103 if (ret)
1104 goto sst_write_err;
1105 }
1106 to += actual;
1107
1108 /* Write out most of the data here. */
1109 for (; actual < len - 1; actual += 2) {
1110 nor->program_opcode = SPINOR_OP_AAI_WP;
1111
1112 /* write two bytes. */
1113 ret = nor->write(nor, to, 2, buf + actual);
1114 if (ret < 0)
1115 goto sst_write_err;
1116 WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
1117 (int)ret);
1118 ret = spi_nor_wait_till_ready(nor);
1119 if (ret)
1120 goto sst_write_err;
1121 to += 2;
1122 nor->sst_write_second = true;
1123 }
1124 nor->sst_write_second = false;
1125
1126 write_disable(nor);
1127 ret = spi_nor_wait_till_ready(nor);
1128 if (ret)
1129 goto sst_write_err;
1130
1131 /* Write out trailing byte if it exists. */
1132 if (actual != len) {
1133 write_enable(nor);
1134
1135 nor->program_opcode = SPINOR_OP_BP;
1136 ret = nor->write(nor, to, 1, buf + actual);
1137 if (ret < 0)
1138 goto sst_write_err;
1139 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
1140 (int)ret);
1141 ret = spi_nor_wait_till_ready(nor);
1142 if (ret)
1143 goto sst_write_err;
1144 write_disable(nor);
1145 actual += 1;
1146 }
1147 sst_write_err:
1148 *retlen += actual;
1149 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1150 return ret;
1151 }
1152
1153 /*
1154 * Write an address range to the nor chip. Data must be written in
1155 * FLASH_PAGESIZE chunks. The address range may be any size provided
1156 * it is within the physical boundaries.
1157 */
spi_nor_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)1158 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1159 size_t *retlen, const u_char *buf)
1160 {
1161 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1162 size_t page_offset, page_remain, i;
1163 ssize_t ret;
1164
1165 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1166
1167 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1168 if (ret)
1169 return ret;
1170
1171 for (i = 0; i < len; ) {
1172 ssize_t written;
1173
1174 page_offset = (to + i) & (nor->page_size - 1);
1175 WARN_ONCE(page_offset,
1176 "Writing at offset %zu into a NOR page. Writing partial pages may decrease reliability and increase wear of NOR flash.",
1177 page_offset);
1178 /* the size of data remaining on the first page */
1179 page_remain = min_t(size_t,
1180 nor->page_size - page_offset, len - i);
1181
1182 write_enable(nor);
1183 ret = nor->write(nor, to + i, page_remain, buf + i);
1184 if (ret < 0)
1185 goto write_err;
1186 written = ret;
1187
1188 ret = spi_nor_wait_till_ready(nor);
1189 if (ret)
1190 goto write_err;
1191 *retlen += written;
1192 i += written;
1193 if (written != page_remain) {
1194 dev_err(nor->dev,
1195 "While writing %zu bytes written %zd bytes\n",
1196 page_remain, written);
1197 ret = -EIO;
1198 goto write_err;
1199 }
1200 }
1201
1202 write_err:
1203 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1204 return ret;
1205 }
1206
macronix_quad_enable(struct spi_nor * nor)1207 static int macronix_quad_enable(struct spi_nor *nor)
1208 {
1209 int ret, val;
1210
1211 val = read_sr(nor);
1212 if (val < 0)
1213 return val;
1214 write_enable(nor);
1215
1216 write_sr(nor, val | SR_QUAD_EN_MX);
1217
1218 if (spi_nor_wait_till_ready(nor))
1219 return 1;
1220
1221 ret = read_sr(nor);
1222 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1223 dev_err(nor->dev, "Macronix Quad bit not set\n");
1224 return -EINVAL;
1225 }
1226
1227 return 0;
1228 }
1229
1230 /*
1231 * Write status Register and configuration register with 2 bytes
1232 * The first byte will be written to the status register, while the
1233 * second byte will be written to the configuration register.
1234 * Return negative if error occured.
1235 */
write_sr_cr(struct spi_nor * nor,u16 val)1236 static int write_sr_cr(struct spi_nor *nor, u16 val)
1237 {
1238 nor->cmd_buf[0] = val & 0xff;
1239 nor->cmd_buf[1] = (val >> 8);
1240
1241 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
1242 }
1243
spansion_quad_enable(struct spi_nor * nor)1244 static int spansion_quad_enable(struct spi_nor *nor)
1245 {
1246 int ret;
1247 int quad_en = CR_QUAD_EN_SPAN << 8;
1248
1249 write_enable(nor);
1250
1251 ret = write_sr_cr(nor, quad_en);
1252 if (ret < 0) {
1253 dev_err(nor->dev,
1254 "error while writing configuration register\n");
1255 return -EINVAL;
1256 }
1257
1258 ret = spi_nor_wait_till_ready(nor);
1259 if (ret) {
1260 dev_err(nor->dev,
1261 "timeout while writing configuration register\n");
1262 return ret;
1263 }
1264
1265 /* read back and check it */
1266 ret = read_cr(nor);
1267 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1268 dev_err(nor->dev, "Spansion Quad bit not set\n");
1269 return -EINVAL;
1270 }
1271
1272 return 0;
1273 }
1274
set_quad_mode(struct spi_nor * nor,const struct flash_info * info)1275 static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
1276 {
1277 int status;
1278
1279 switch (JEDEC_MFR(info)) {
1280 case SNOR_MFR_MACRONIX:
1281 status = macronix_quad_enable(nor);
1282 if (status) {
1283 dev_err(nor->dev, "Macronix quad-read not enabled\n");
1284 return -EINVAL;
1285 }
1286 return status;
1287 case SNOR_MFR_MICRON:
1288 return 0;
1289 default:
1290 status = spansion_quad_enable(nor);
1291 if (status) {
1292 dev_err(nor->dev, "Spansion quad-read not enabled\n");
1293 return -EINVAL;
1294 }
1295 return status;
1296 }
1297 }
1298
spi_nor_check(struct spi_nor * nor)1299 static int spi_nor_check(struct spi_nor *nor)
1300 {
1301 if (!nor->dev || !nor->read || !nor->write ||
1302 !nor->read_reg || !nor->write_reg) {
1303 pr_err("spi-nor: please fill all the necessary fields!\n");
1304 return -EINVAL;
1305 }
1306
1307 return 0;
1308 }
1309
spi_nor_scan(struct spi_nor * nor,const char * name,enum read_mode mode)1310 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
1311 {
1312 const struct flash_info *info = NULL;
1313 struct device *dev = nor->dev;
1314 struct mtd_info *mtd = &nor->mtd;
1315 struct device_node *np = spi_nor_get_flash_node(nor);
1316 int ret;
1317 int i;
1318
1319 ret = spi_nor_check(nor);
1320 if (ret)
1321 return ret;
1322
1323 if (name)
1324 info = spi_nor_match_id(name);
1325 /* Try to auto-detect if chip name wasn't specified or not found */
1326 if (!info)
1327 info = spi_nor_read_id(nor);
1328 if (IS_ERR_OR_NULL(info))
1329 return -ENOENT;
1330
1331 /*
1332 * If caller has specified name of flash model that can normally be
1333 * detected using JEDEC, let's verify it.
1334 */
1335 if (name && info->id_len) {
1336 const struct flash_info *jinfo;
1337
1338 jinfo = spi_nor_read_id(nor);
1339 if (IS_ERR(jinfo)) {
1340 return PTR_ERR(jinfo);
1341 } else if (jinfo != info) {
1342 /*
1343 * JEDEC knows better, so overwrite platform ID. We
1344 * can't trust partitions any longer, but we'll let
1345 * mtd apply them anyway, since some partitions may be
1346 * marked read-only, and we don't want to lose that
1347 * information, even if it's not 100% accurate.
1348 */
1349 dev_warn(dev, "found %s, expected %s\n",
1350 jinfo->name, info->name);
1351 info = jinfo;
1352 }
1353 }
1354
1355 mutex_init(&nor->lock);
1356
1357 /*
1358 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
1359 * with the software protection bits set
1360 */
1361
1362 if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
1363 JEDEC_MFR(info) == SNOR_MFR_INTEL ||
1364 JEDEC_MFR(info) == SNOR_MFR_SST ||
1365 info->flags & SPI_NOR_HAS_LOCK) {
1366 write_enable(nor);
1367 write_sr(nor, 0);
1368 spi_nor_wait_till_ready(nor);
1369 }
1370
1371 if (!mtd->name)
1372 mtd->name = dev_name(dev);
1373 mtd->priv = nor;
1374 mtd->type = MTD_NORFLASH;
1375 mtd->writesize = 1;
1376 mtd->flags = MTD_CAP_NORFLASH;
1377 mtd->size = info->sector_size * info->n_sectors;
1378 mtd->_erase = spi_nor_erase;
1379 mtd->_read = spi_nor_read;
1380
1381 /* NOR protection support for STmicro/Micron chips and similar */
1382 if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
1383 info->flags & SPI_NOR_HAS_LOCK) {
1384 nor->flash_lock = stm_lock;
1385 nor->flash_unlock = stm_unlock;
1386 nor->flash_is_locked = stm_is_locked;
1387 }
1388
1389 if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
1390 mtd->_lock = spi_nor_lock;
1391 mtd->_unlock = spi_nor_unlock;
1392 mtd->_is_locked = spi_nor_is_locked;
1393 }
1394
1395 /* sst nor chips use AAI word program */
1396 if (info->flags & SST_WRITE)
1397 mtd->_write = sst_write;
1398 else
1399 mtd->_write = spi_nor_write;
1400
1401 if (info->flags & USE_FSR)
1402 nor->flags |= SNOR_F_USE_FSR;
1403 if (info->flags & SPI_NOR_HAS_TB)
1404 nor->flags |= SNOR_F_HAS_SR_TB;
1405
1406 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
1407 /* prefer "small sector" erase if possible */
1408 if (info->flags & SECT_4K) {
1409 nor->erase_opcode = SPINOR_OP_BE_4K;
1410 mtd->erasesize = 4096;
1411 } else if (info->flags & SECT_4K_PMC) {
1412 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
1413 mtd->erasesize = 4096;
1414 } else
1415 #endif
1416 {
1417 nor->erase_opcode = SPINOR_OP_SE;
1418 mtd->erasesize = info->sector_size;
1419 }
1420
1421 if (info->flags & SPI_NOR_NO_ERASE)
1422 mtd->flags |= MTD_NO_ERASE;
1423
1424 mtd->dev.parent = dev;
1425 nor->page_size = info->page_size;
1426 mtd->writebufsize = nor->page_size;
1427
1428 if (np) {
1429 /* If we were instantiated by DT, use it */
1430 if (of_property_read_bool(np, "m25p,fast-read"))
1431 nor->flash_read = SPI_NOR_FAST;
1432 else
1433 nor->flash_read = SPI_NOR_NORMAL;
1434 } else {
1435 /* If we weren't instantiated by DT, default to fast-read */
1436 nor->flash_read = SPI_NOR_FAST;
1437 }
1438
1439 /* Some devices cannot do fast-read, no matter what DT tells us */
1440 if (info->flags & SPI_NOR_NO_FR)
1441 nor->flash_read = SPI_NOR_NORMAL;
1442
1443 /* Quad/Dual-read mode takes precedence over fast/normal */
1444 if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
1445 ret = set_quad_mode(nor, info);
1446 if (ret) {
1447 dev_err(dev, "quad mode not supported\n");
1448 return ret;
1449 }
1450 nor->flash_read = SPI_NOR_QUAD;
1451 } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
1452 nor->flash_read = SPI_NOR_DUAL;
1453 }
1454
1455 /* Default commands */
1456 switch (nor->flash_read) {
1457 case SPI_NOR_QUAD:
1458 nor->read_opcode = SPINOR_OP_READ_1_1_4;
1459 break;
1460 case SPI_NOR_DUAL:
1461 nor->read_opcode = SPINOR_OP_READ_1_1_2;
1462 break;
1463 case SPI_NOR_FAST:
1464 nor->read_opcode = SPINOR_OP_READ_FAST;
1465 break;
1466 case SPI_NOR_NORMAL:
1467 nor->read_opcode = SPINOR_OP_READ;
1468 break;
1469 default:
1470 dev_err(dev, "No Read opcode defined\n");
1471 return -EINVAL;
1472 }
1473
1474 nor->program_opcode = SPINOR_OP_PP;
1475
1476 if (info->addr_width)
1477 nor->addr_width = info->addr_width;
1478 else if (mtd->size > 0x1000000) {
1479 /* enable 4-byte addressing if the device exceeds 16MiB */
1480 nor->addr_width = 4;
1481 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
1482 /* Dedicated 4-byte command set */
1483 switch (nor->flash_read) {
1484 case SPI_NOR_QUAD:
1485 nor->read_opcode = SPINOR_OP_READ4_1_1_4;
1486 break;
1487 case SPI_NOR_DUAL:
1488 nor->read_opcode = SPINOR_OP_READ4_1_1_2;
1489 break;
1490 case SPI_NOR_FAST:
1491 nor->read_opcode = SPINOR_OP_READ4_FAST;
1492 break;
1493 case SPI_NOR_NORMAL:
1494 nor->read_opcode = SPINOR_OP_READ4;
1495 break;
1496 }
1497 nor->program_opcode = SPINOR_OP_PP_4B;
1498 /* No small sector erase for 4-byte command set */
1499 nor->erase_opcode = SPINOR_OP_SE_4B;
1500 mtd->erasesize = info->sector_size;
1501 } else
1502 set_4byte(nor, info, 1);
1503 } else {
1504 nor->addr_width = 3;
1505 }
1506
1507 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
1508 dev_err(dev, "address width is too large: %u\n",
1509 nor->addr_width);
1510 return -EINVAL;
1511 }
1512
1513 nor->read_dummy = spi_nor_read_dummy_cycles(nor);
1514
1515 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
1516 (long long)mtd->size >> 10);
1517
1518 dev_dbg(dev,
1519 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1520 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1521 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
1522 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
1523
1524 if (mtd->numeraseregions)
1525 for (i = 0; i < mtd->numeraseregions; i++)
1526 dev_dbg(dev,
1527 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1528 ".erasesize = 0x%.8x (%uKiB), "
1529 ".numblocks = %d }\n",
1530 i, (long long)mtd->eraseregions[i].offset,
1531 mtd->eraseregions[i].erasesize,
1532 mtd->eraseregions[i].erasesize / 1024,
1533 mtd->eraseregions[i].numblocks);
1534 return 0;
1535 }
1536 EXPORT_SYMBOL_GPL(spi_nor_scan);
1537
spi_nor_match_id(const char * name)1538 static const struct flash_info *spi_nor_match_id(const char *name)
1539 {
1540 const struct flash_info *id = spi_nor_ids;
1541
1542 while (id->name) {
1543 if (!strcmp(name, id->name))
1544 return id;
1545 id++;
1546 }
1547 return NULL;
1548 }
1549
1550 MODULE_LICENSE("GPL");
1551 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1552 MODULE_AUTHOR("Mike Lavender");
1553 MODULE_DESCRIPTION("framework for SPI NOR");
1554