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1 /*******************************************************************************
2 *
3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses.  You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenFabrics.org BSD license below:
10 *
11 *   Redistribution and use in source and binary forms, with or
12 *   without modification, are permitted provided that the following
13 *   conditions are met:
14 *
15 *    - Redistributions of source code must retain the above
16 *	copyright notice, this list of conditions and the following
17 *	disclaimer.
18 *
19 *    - Redistributions in binary form must reproduce the above
20 *	copyright notice, this list of conditions and the following
21 *	disclaimer in the documentation and/or other materials
22 *	provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 *
33 *******************************************************************************/
34 
35 #ifndef I40IW_TYPE_H
36 #define I40IW_TYPE_H
37 #include "i40iw_user.h"
38 #include "i40iw_hmc.h"
39 #include "i40iw_vf.h"
40 #include "i40iw_virtchnl.h"
41 
42 struct i40iw_cqp_sq_wqe {
43 	u64 buf[I40IW_CQP_WQE_SIZE];
44 };
45 
46 struct i40iw_sc_aeqe {
47 	u64 buf[I40IW_AEQE_SIZE];
48 };
49 
50 struct i40iw_ceqe {
51 	u64 buf[I40IW_CEQE_SIZE];
52 };
53 
54 struct i40iw_cqp_ctx {
55 	u64 buf[I40IW_CQP_CTX_SIZE];
56 };
57 
58 struct i40iw_cq_shadow_area {
59 	u64 buf[I40IW_SHADOW_AREA_SIZE];
60 };
61 
62 struct i40iw_sc_dev;
63 struct i40iw_hmc_info;
64 struct i40iw_dev_pestat;
65 
66 struct i40iw_cqp_ops;
67 struct i40iw_ccq_ops;
68 struct i40iw_ceq_ops;
69 struct i40iw_aeq_ops;
70 struct i40iw_mr_ops;
71 struct i40iw_cqp_misc_ops;
72 struct i40iw_pd_ops;
73 struct i40iw_priv_qp_ops;
74 struct i40iw_priv_cq_ops;
75 struct i40iw_hmc_ops;
76 
77 enum i40iw_resource_indicator_type {
78 	I40IW_RSRC_INDICATOR_TYPE_ADAPTER = 0,
79 	I40IW_RSRC_INDICATOR_TYPE_CQ,
80 	I40IW_RSRC_INDICATOR_TYPE_QP,
81 	I40IW_RSRC_INDICATOR_TYPE_SRQ
82 };
83 
84 enum i40iw_hdrct_flags {
85 	DDP_LEN_FLAG = 0x80,
86 	DDP_HDR_FLAG = 0x40,
87 	RDMA_HDR_FLAG = 0x20
88 };
89 
90 enum i40iw_term_layers {
91 	LAYER_RDMA = 0,
92 	LAYER_DDP = 1,
93 	LAYER_MPA = 2
94 };
95 
96 enum i40iw_term_error_types {
97 	RDMAP_REMOTE_PROT = 1,
98 	RDMAP_REMOTE_OP = 2,
99 	DDP_CATASTROPHIC = 0,
100 	DDP_TAGGED_BUFFER = 1,
101 	DDP_UNTAGGED_BUFFER = 2,
102 	DDP_LLP = 3
103 };
104 
105 enum i40iw_term_rdma_errors {
106 	RDMAP_INV_STAG = 0x00,
107 	RDMAP_INV_BOUNDS = 0x01,
108 	RDMAP_ACCESS = 0x02,
109 	RDMAP_UNASSOC_STAG = 0x03,
110 	RDMAP_TO_WRAP = 0x04,
111 	RDMAP_INV_RDMAP_VER = 0x05,
112 	RDMAP_UNEXPECTED_OP = 0x06,
113 	RDMAP_CATASTROPHIC_LOCAL = 0x07,
114 	RDMAP_CATASTROPHIC_GLOBAL = 0x08,
115 	RDMAP_CANT_INV_STAG = 0x09,
116 	RDMAP_UNSPECIFIED = 0xff
117 };
118 
119 enum i40iw_term_ddp_errors {
120 	DDP_CATASTROPHIC_LOCAL = 0x00,
121 	DDP_TAGGED_INV_STAG = 0x00,
122 	DDP_TAGGED_BOUNDS = 0x01,
123 	DDP_TAGGED_UNASSOC_STAG = 0x02,
124 	DDP_TAGGED_TO_WRAP = 0x03,
125 	DDP_TAGGED_INV_DDP_VER = 0x04,
126 	DDP_UNTAGGED_INV_QN = 0x01,
127 	DDP_UNTAGGED_INV_MSN_NO_BUF = 0x02,
128 	DDP_UNTAGGED_INV_MSN_RANGE = 0x03,
129 	DDP_UNTAGGED_INV_MO = 0x04,
130 	DDP_UNTAGGED_INV_TOO_LONG = 0x05,
131 	DDP_UNTAGGED_INV_DDP_VER = 0x06
132 };
133 
134 enum i40iw_term_mpa_errors {
135 	MPA_CLOSED = 0x01,
136 	MPA_CRC = 0x02,
137 	MPA_MARKER = 0x03,
138 	MPA_REQ_RSP = 0x04,
139 };
140 
141 enum i40iw_flush_opcode {
142 	FLUSH_INVALID = 0,
143 	FLUSH_PROT_ERR,
144 	FLUSH_REM_ACCESS_ERR,
145 	FLUSH_LOC_QP_OP_ERR,
146 	FLUSH_REM_OP_ERR,
147 	FLUSH_LOC_LEN_ERR,
148 	FLUSH_GENERAL_ERR,
149 	FLUSH_FATAL_ERR
150 };
151 
152 enum i40iw_term_eventtypes {
153 	TERM_EVENT_QP_FATAL,
154 	TERM_EVENT_QP_ACCESS_ERR
155 };
156 
157 struct i40iw_terminate_hdr {
158 	u8 layer_etype;
159 	u8 error_code;
160 	u8 hdrct;
161 	u8 rsvd;
162 };
163 
164 enum i40iw_debug_flag {
165 	I40IW_DEBUG_NONE	= 0x00000000,
166 	I40IW_DEBUG_ERR		= 0x00000001,
167 	I40IW_DEBUG_INIT	= 0x00000002,
168 	I40IW_DEBUG_DEV		= 0x00000004,
169 	I40IW_DEBUG_CM		= 0x00000008,
170 	I40IW_DEBUG_VERBS	= 0x00000010,
171 	I40IW_DEBUG_PUDA	= 0x00000020,
172 	I40IW_DEBUG_ILQ		= 0x00000040,
173 	I40IW_DEBUG_IEQ		= 0x00000080,
174 	I40IW_DEBUG_QP		= 0x00000100,
175 	I40IW_DEBUG_CQ		= 0x00000200,
176 	I40IW_DEBUG_MR		= 0x00000400,
177 	I40IW_DEBUG_PBLE	= 0x00000800,
178 	I40IW_DEBUG_WQE		= 0x00001000,
179 	I40IW_DEBUG_AEQ		= 0x00002000,
180 	I40IW_DEBUG_CQP		= 0x00004000,
181 	I40IW_DEBUG_HMC		= 0x00008000,
182 	I40IW_DEBUG_USER	= 0x00010000,
183 	I40IW_DEBUG_VIRT	= 0x00020000,
184 	I40IW_DEBUG_DCB		= 0x00040000,
185 	I40IW_DEBUG_CQE		= 0x00800000,
186 	I40IW_DEBUG_ALL		= 0xFFFFFFFF
187 };
188 
189 enum i40iw_hw_stat_index_32b {
190 	I40IW_HW_STAT_INDEX_IP4RXDISCARD = 0,
191 	I40IW_HW_STAT_INDEX_IP4RXTRUNC,
192 	I40IW_HW_STAT_INDEX_IP4TXNOROUTE,
193 	I40IW_HW_STAT_INDEX_IP6RXDISCARD,
194 	I40IW_HW_STAT_INDEX_IP6RXTRUNC,
195 	I40IW_HW_STAT_INDEX_IP6TXNOROUTE,
196 	I40IW_HW_STAT_INDEX_TCPRTXSEG,
197 	I40IW_HW_STAT_INDEX_TCPRXOPTERR,
198 	I40IW_HW_STAT_INDEX_TCPRXPROTOERR,
199 	I40IW_HW_STAT_INDEX_MAX_32
200 };
201 
202 enum i40iw_hw_stat_index_64b {
203 	I40IW_HW_STAT_INDEX_IP4RXOCTS = 0,
204 	I40IW_HW_STAT_INDEX_IP4RXPKTS,
205 	I40IW_HW_STAT_INDEX_IP4RXFRAGS,
206 	I40IW_HW_STAT_INDEX_IP4RXMCPKTS,
207 	I40IW_HW_STAT_INDEX_IP4TXOCTS,
208 	I40IW_HW_STAT_INDEX_IP4TXPKTS,
209 	I40IW_HW_STAT_INDEX_IP4TXFRAGS,
210 	I40IW_HW_STAT_INDEX_IP4TXMCPKTS,
211 	I40IW_HW_STAT_INDEX_IP6RXOCTS,
212 	I40IW_HW_STAT_INDEX_IP6RXPKTS,
213 	I40IW_HW_STAT_INDEX_IP6RXFRAGS,
214 	I40IW_HW_STAT_INDEX_IP6RXMCPKTS,
215 	I40IW_HW_STAT_INDEX_IP6TXOCTS,
216 	I40IW_HW_STAT_INDEX_IP6TXPKTS,
217 	I40IW_HW_STAT_INDEX_IP6TXFRAGS,
218 	I40IW_HW_STAT_INDEX_IP6TXMCPKTS,
219 	I40IW_HW_STAT_INDEX_TCPRXSEGS,
220 	I40IW_HW_STAT_INDEX_TCPTXSEG,
221 	I40IW_HW_STAT_INDEX_RDMARXRDS,
222 	I40IW_HW_STAT_INDEX_RDMARXSNDS,
223 	I40IW_HW_STAT_INDEX_RDMARXWRS,
224 	I40IW_HW_STAT_INDEX_RDMATXRDS,
225 	I40IW_HW_STAT_INDEX_RDMATXSNDS,
226 	I40IW_HW_STAT_INDEX_RDMATXWRS,
227 	I40IW_HW_STAT_INDEX_RDMAVBND,
228 	I40IW_HW_STAT_INDEX_RDMAVINV,
229 	I40IW_HW_STAT_INDEX_MAX_64
230 };
231 
232 struct i40iw_dev_hw_stat_offsets {
233 	u32 stat_offset_32[I40IW_HW_STAT_INDEX_MAX_32];
234 	u32 stat_offset_64[I40IW_HW_STAT_INDEX_MAX_64];
235 };
236 
237 struct i40iw_dev_hw_stats {
238 	u64 stat_value_32[I40IW_HW_STAT_INDEX_MAX_32];
239 	u64 stat_value_64[I40IW_HW_STAT_INDEX_MAX_64];
240 };
241 
242 struct i40iw_device_pestat_ops {
243 	void (*iw_hw_stat_init)(struct i40iw_dev_pestat *, u8, struct i40iw_hw *, bool);
244 	void (*iw_hw_stat_read_32)(struct i40iw_dev_pestat *, enum i40iw_hw_stat_index_32b, u64 *);
245 	void (*iw_hw_stat_read_64)(struct i40iw_dev_pestat *, enum i40iw_hw_stat_index_64b, u64 *);
246 	void (*iw_hw_stat_read_all)(struct i40iw_dev_pestat *, struct i40iw_dev_hw_stats *);
247 	void (*iw_hw_stat_refresh_all)(struct i40iw_dev_pestat *);
248 };
249 
250 struct i40iw_dev_pestat {
251 	struct i40iw_hw *hw;
252 	struct i40iw_device_pestat_ops ops;
253 	struct i40iw_dev_hw_stats hw_stats;
254 	struct i40iw_dev_hw_stats last_read_hw_stats;
255 	struct i40iw_dev_hw_stat_offsets hw_stat_offsets;
256 	struct timer_list stats_timer;
257 	spinlock_t stats_lock; /* rdma stats lock */
258 };
259 
260 struct i40iw_hw {
261 	u8 __iomem *hw_addr;
262 	void *dev_context;
263 	struct i40iw_hmc_info hmc;
264 };
265 
266 struct i40iw_pfpdu {
267 	struct list_head rxlist;
268 	u32 rcv_nxt;
269 	u32 fps;
270 	u32 max_fpdu_data;
271 	bool mode;
272 	bool mpa_crc_err;
273 	u64 total_ieq_bufs;
274 	u64 fpdu_processed;
275 	u64 bad_seq_num;
276 	u64 crc_err;
277 	u64 no_tx_bufs;
278 	u64 tx_err;
279 	u64 out_of_order;
280 	u64 pmode_count;
281 };
282 
283 struct i40iw_sc_pd {
284 	u32 size;
285 	struct i40iw_sc_dev *dev;
286 	u16 pd_id;
287 };
288 
289 struct i40iw_cqp_quanta {
290 	u64 elem[I40IW_CQP_WQE_SIZE];
291 };
292 
293 struct i40iw_sc_cqp {
294 	u32 size;
295 	u64 sq_pa;
296 	u64 host_ctx_pa;
297 	void *back_cqp;
298 	struct i40iw_sc_dev *dev;
299 	enum i40iw_status_code (*process_cqp_sds)(struct i40iw_sc_dev *,
300 						  struct i40iw_update_sds_info *);
301 	struct i40iw_dma_mem sdbuf;
302 	struct i40iw_ring sq_ring;
303 	struct i40iw_cqp_quanta *sq_base;
304 	u64 *host_ctx;
305 	u64 *scratch_array;
306 	u32 cqp_id;
307 	u32 sq_size;
308 	u32 hw_sq_size;
309 	u8 struct_ver;
310 	u8 polarity;
311 	bool en_datacenter_tcp;
312 	u8 hmc_profile;
313 	u8 enabled_vf_count;
314 	u8 timeout_count;
315 };
316 
317 struct i40iw_sc_aeq {
318 	u32 size;
319 	u64 aeq_elem_pa;
320 	struct i40iw_sc_dev *dev;
321 	struct i40iw_sc_aeqe *aeqe_base;
322 	void *pbl_list;
323 	u32 elem_cnt;
324 	struct i40iw_ring aeq_ring;
325 	bool virtual_map;
326 	u8 pbl_chunk_size;
327 	u32 first_pm_pbl_idx;
328 	u8 polarity;
329 };
330 
331 struct i40iw_sc_ceq {
332 	u32 size;
333 	u64 ceq_elem_pa;
334 	struct i40iw_sc_dev *dev;
335 	struct i40iw_ceqe *ceqe_base;
336 	void *pbl_list;
337 	u32 ceq_id;
338 	u32 elem_cnt;
339 	struct i40iw_ring ceq_ring;
340 	bool virtual_map;
341 	u8 pbl_chunk_size;
342 	bool tph_en;
343 	u8 tph_val;
344 	u32 first_pm_pbl_idx;
345 	u8 polarity;
346 };
347 
348 struct i40iw_sc_cq {
349 	struct i40iw_cq_uk cq_uk;
350 	u64 cq_pa;
351 	u64 shadow_area_pa;
352 	struct i40iw_sc_dev *dev;
353 	void *pbl_list;
354 	void *back_cq;
355 	u32 ceq_id;
356 	u32 shadow_read_threshold;
357 	bool ceqe_mask;
358 	bool virtual_map;
359 	u8 pbl_chunk_size;
360 	u8 cq_type;
361 	bool ceq_id_valid;
362 	bool tph_en;
363 	u8 tph_val;
364 	u32 first_pm_pbl_idx;
365 	bool check_overflow;
366 };
367 
368 struct i40iw_sc_qp {
369 	struct i40iw_qp_uk qp_uk;
370 	u64 sq_pa;
371 	u64 rq_pa;
372 	u64 hw_host_ctx_pa;
373 	u64 shadow_area_pa;
374 	u64 q2_pa;
375 	struct i40iw_sc_dev *dev;
376 	struct i40iw_sc_pd *pd;
377 	u64 *hw_host_ctx;
378 	void *llp_stream_handle;
379 	void *back_qp;
380 	struct i40iw_pfpdu pfpdu;
381 	u8 *q2_buf;
382 	u64 qp_compl_ctx;
383 	u16 qs_handle;
384 	u16 exception_lan_queue;
385 	u16 push_idx;
386 	u8 sq_tph_val;
387 	u8 rq_tph_val;
388 	u8 qp_state;
389 	u8 qp_type;
390 	u8 hw_sq_size;
391 	u8 hw_rq_size;
392 	u8 src_mac_addr_idx;
393 	bool sq_tph_en;
394 	bool rq_tph_en;
395 	bool rcv_tph_en;
396 	bool xmit_tph_en;
397 	bool virtual_map;
398 	bool flush_sq;
399 	bool flush_rq;
400 	bool sq_flush;
401 	enum i40iw_flush_opcode flush_code;
402 	enum i40iw_term_eventtypes eventtype;
403 	u8 term_flags;
404 };
405 
406 struct i40iw_hmc_fpm_misc {
407 	u32 max_ceqs;
408 	u32 max_sds;
409 	u32 xf_block_size;
410 	u32 q1_block_size;
411 	u32 ht_multiplier;
412 	u32 timer_bucket;
413 };
414 
415 struct i40iw_vchnl_if {
416 	enum i40iw_status_code (*vchnl_recv)(struct i40iw_sc_dev *, u32, u8 *, u16);
417 	enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *dev, u32, u8 *, u16);
418 };
419 
420 #define I40IW_VCHNL_MAX_VF_MSG_SIZE 512
421 
422 struct i40iw_vchnl_vf_msg_buffer {
423 	struct i40iw_virtchnl_op_buf vchnl_msg;
424 	char parm_buffer[I40IW_VCHNL_MAX_VF_MSG_SIZE - 1];
425 };
426 
427 struct i40iw_vfdev {
428 	struct i40iw_sc_dev *pf_dev;
429 	u8 *hmc_info_mem;
430 	struct i40iw_dev_pestat dev_pestat;
431 	struct i40iw_hmc_pble_info *pble_info;
432 	struct i40iw_hmc_info hmc_info;
433 	struct i40iw_vchnl_vf_msg_buffer vf_msg_buffer;
434 	u64 fpm_query_buf_pa;
435 	u64 *fpm_query_buf;
436 	u32 vf_id;
437 	u32 msg_count;
438 	bool pf_hmc_initialized;
439 	u16 pmf_index;
440 	u16 iw_vf_idx;		/* VF Device table index */
441 	bool stats_initialized;
442 };
443 
444 struct i40iw_sc_dev {
445 	struct list_head cqp_cmd_head;	/* head of the CQP command list */
446 	spinlock_t cqp_lock; /* cqp list sync */
447 	struct i40iw_dev_uk dev_uk;
448 	struct i40iw_dev_pestat dev_pestat;
449 	struct i40iw_dma_mem vf_fpm_query_buf[I40IW_MAX_PE_ENABLED_VF_COUNT];
450 	u64 fpm_query_buf_pa;
451 	u64 fpm_commit_buf_pa;
452 	u64 *fpm_query_buf;
453 	u64 *fpm_commit_buf;
454 	void *back_dev;
455 	struct i40iw_hw *hw;
456 	u8 __iomem *db_addr;
457 	struct i40iw_hmc_info *hmc_info;
458 	struct i40iw_hmc_pble_info *pble_info;
459 	struct i40iw_vfdev *vf_dev[I40IW_MAX_PE_ENABLED_VF_COUNT];
460 	struct i40iw_sc_cqp *cqp;
461 	struct i40iw_sc_aeq *aeq;
462 	struct i40iw_sc_ceq *ceq[I40IW_CEQ_MAX_COUNT];
463 	struct i40iw_sc_cq *ccq;
464 	struct i40iw_cqp_ops *cqp_ops;
465 	struct i40iw_ccq_ops *ccq_ops;
466 	struct i40iw_ceq_ops *ceq_ops;
467 	struct i40iw_aeq_ops *aeq_ops;
468 	struct i40iw_pd_ops *iw_pd_ops;
469 	struct i40iw_priv_qp_ops *iw_priv_qp_ops;
470 	struct i40iw_priv_cq_ops *iw_priv_cq_ops;
471 	struct i40iw_mr_ops *mr_ops;
472 	struct i40iw_cqp_misc_ops *cqp_misc_ops;
473 	struct i40iw_hmc_ops *hmc_ops;
474 	struct i40iw_vchnl_if vchnl_if;
475 	u32 ilq_count;
476 	struct i40iw_virt_mem ilq_mem;
477 	struct i40iw_puda_rsrc *ilq;
478 	u32 ieq_count;
479 	struct i40iw_virt_mem ieq_mem;
480 	struct i40iw_puda_rsrc *ieq;
481 
482 	const struct i40iw_vf_cqp_ops *iw_vf_cqp_ops;
483 
484 	struct i40iw_hmc_fpm_misc hmc_fpm_misc;
485 	u16 qs_handle;
486 	u32 debug_mask;
487 	u16 exception_lan_queue;
488 	u8 hmc_fn_id;
489 	bool is_pf;
490 	bool vchnl_up;
491 	u8 vf_id;
492 	wait_queue_head_t vf_reqs;
493 	u64 cqp_cmd_stats[OP_SIZE_CQP_STAT_ARRAY];
494 	struct i40iw_vchnl_vf_msg_buffer vchnl_vf_msg_buf;
495 	u8 hw_rev;
496 };
497 
498 struct i40iw_modify_cq_info {
499 	u64 cq_pa;
500 	struct i40iw_cqe *cq_base;
501 	void *pbl_list;
502 	u32 ceq_id;
503 	u32 cq_size;
504 	u32 shadow_read_threshold;
505 	bool virtual_map;
506 	u8 pbl_chunk_size;
507 	bool check_overflow;
508 	bool cq_resize;
509 	bool ceq_change;
510 	bool check_overflow_change;
511 	u32 first_pm_pbl_idx;
512 	bool ceq_valid;
513 };
514 
515 struct i40iw_create_qp_info {
516 	u8 next_iwarp_state;
517 	bool ord_valid;
518 	bool tcp_ctx_valid;
519 	bool cq_num_valid;
520 	bool static_rsrc;
521 	bool arp_cache_idx_valid;
522 };
523 
524 struct i40iw_modify_qp_info {
525 	u64 rx_win0;
526 	u64 rx_win1;
527 	u16 new_mss;
528 	u8 next_iwarp_state;
529 	u8 termlen;
530 	bool ord_valid;
531 	bool tcp_ctx_valid;
532 	bool cq_num_valid;
533 	bool static_rsrc;
534 	bool arp_cache_idx_valid;
535 	bool reset_tcp_conn;
536 	bool remove_hash_idx;
537 	bool dont_send_term;
538 	bool dont_send_fin;
539 	bool cached_var_valid;
540 	bool mss_change;
541 	bool force_loopback;
542 };
543 
544 struct i40iw_ccq_cqe_info {
545 	struct i40iw_sc_cqp *cqp;
546 	u64 scratch;
547 	u32 op_ret_val;
548 	u16 maj_err_code;
549 	u16 min_err_code;
550 	u8 op_code;
551 	bool error;
552 };
553 
554 struct i40iw_l2params {
555 	u16 qs_handle_list[I40IW_MAX_USER_PRIORITY];
556 	u16 mss;
557 };
558 
559 struct i40iw_device_init_info {
560 	u64 fpm_query_buf_pa;
561 	u64 fpm_commit_buf_pa;
562 	u64 *fpm_query_buf;
563 	u64 *fpm_commit_buf;
564 	struct i40iw_hw *hw;
565 	void __iomem *bar0;
566 	enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *, u32, u8 *, u16);
567 	u16 qs_handle;
568 	u16 exception_lan_queue;
569 	u8 hmc_fn_id;
570 	bool is_pf;
571 	u32 debug_mask;
572 };
573 
574 enum i40iw_cqp_hmc_profile {
575 	I40IW_HMC_PROFILE_DEFAULT = 1,
576 	I40IW_HMC_PROFILE_FAVOR_VF = 2,
577 	I40IW_HMC_PROFILE_EQUAL = 3,
578 };
579 
580 struct i40iw_cqp_init_info {
581 	u64 cqp_compl_ctx;
582 	u64 host_ctx_pa;
583 	u64 sq_pa;
584 	struct i40iw_sc_dev *dev;
585 	struct i40iw_cqp_quanta *sq;
586 	u64 *host_ctx;
587 	u64 *scratch_array;
588 	u32 sq_size;
589 	u8 struct_ver;
590 	bool en_datacenter_tcp;
591 	u8 hmc_profile;
592 	u8 enabled_vf_count;
593 };
594 
595 struct i40iw_ceq_init_info {
596 	u64 ceqe_pa;
597 	struct i40iw_sc_dev *dev;
598 	u64 *ceqe_base;
599 	void *pbl_list;
600 	u32 elem_cnt;
601 	u32 ceq_id;
602 	bool virtual_map;
603 	u8 pbl_chunk_size;
604 	bool tph_en;
605 	u8 tph_val;
606 	u32 first_pm_pbl_idx;
607 };
608 
609 struct i40iw_aeq_init_info {
610 	u64 aeq_elem_pa;
611 	struct i40iw_sc_dev *dev;
612 	u32 *aeqe_base;
613 	void *pbl_list;
614 	u32 elem_cnt;
615 	bool virtual_map;
616 	u8 pbl_chunk_size;
617 	u32 first_pm_pbl_idx;
618 };
619 
620 struct i40iw_ccq_init_info {
621 	u64 cq_pa;
622 	u64 shadow_area_pa;
623 	struct i40iw_sc_dev *dev;
624 	struct i40iw_cqe *cq_base;
625 	u64 *shadow_area;
626 	void *pbl_list;
627 	u32 num_elem;
628 	u32 ceq_id;
629 	u32 shadow_read_threshold;
630 	bool ceqe_mask;
631 	bool ceq_id_valid;
632 	bool tph_en;
633 	u8 tph_val;
634 	bool avoid_mem_cflct;
635 	bool virtual_map;
636 	u8 pbl_chunk_size;
637 	u32 first_pm_pbl_idx;
638 };
639 
640 struct i40iwarp_offload_info {
641 	u16 rcv_mark_offset;
642 	u16 snd_mark_offset;
643 	u16 pd_id;
644 	u8 ddp_ver;
645 	u8 rdmap_ver;
646 	u8 ord_size;
647 	u8 ird_size;
648 	bool wr_rdresp_en;
649 	bool rd_enable;
650 	bool snd_mark_en;
651 	bool rcv_mark_en;
652 	bool bind_en;
653 	bool fast_reg_en;
654 	bool priv_mode_en;
655 	bool lsmm_present;
656 	u8 iwarp_mode;
657 	bool align_hdrs;
658 	bool rcv_no_mpa_crc;
659 
660 	u8 last_byte_sent;
661 };
662 
663 struct i40iw_tcp_offload_info {
664 	bool ipv4;
665 	bool no_nagle;
666 	bool insert_vlan_tag;
667 	bool time_stamp;
668 	u8 cwnd_inc_limit;
669 	bool drop_ooo_seg;
670 	u8 dup_ack_thresh;
671 	u8 ttl;
672 	u8 src_mac_addr_idx;
673 	bool avoid_stretch_ack;
674 	u8 tos;
675 	u16 src_port;
676 	u16 dst_port;
677 	u32 dest_ip_addr0;
678 	u32 dest_ip_addr1;
679 	u32 dest_ip_addr2;
680 	u32 dest_ip_addr3;
681 	u32 snd_mss;
682 	u16 vlan_tag;
683 	u16 arp_idx;
684 	u32 flow_label;
685 	bool wscale;
686 	u8 tcp_state;
687 	u8 snd_wscale;
688 	u8 rcv_wscale;
689 	u32 time_stamp_recent;
690 	u32 time_stamp_age;
691 	u32 snd_nxt;
692 	u32 snd_wnd;
693 	u32 rcv_nxt;
694 	u32 rcv_wnd;
695 	u32 snd_max;
696 	u32 snd_una;
697 	u32 srtt;
698 	u32 rtt_var;
699 	u32 ss_thresh;
700 	u32 cwnd;
701 	u32 snd_wl1;
702 	u32 snd_wl2;
703 	u32 max_snd_window;
704 	u8 rexmit_thresh;
705 	u32 local_ipaddr0;
706 	u32 local_ipaddr1;
707 	u32 local_ipaddr2;
708 	u32 local_ipaddr3;
709 	bool ignore_tcp_opt;
710 	bool ignore_tcp_uns_opt;
711 };
712 
713 struct i40iw_qp_host_ctx_info {
714 	u64 qp_compl_ctx;
715 	struct i40iw_tcp_offload_info *tcp_info;
716 	struct i40iwarp_offload_info *iwarp_info;
717 	u32 send_cq_num;
718 	u32 rcv_cq_num;
719 	u16 push_idx;
720 	bool push_mode_en;
721 	bool tcp_info_valid;
722 	bool iwarp_info_valid;
723 	bool err_rq_idx_valid;
724 	u16 err_rq_idx;
725 };
726 
727 struct i40iw_aeqe_info {
728 	u64 compl_ctx;
729 	u32 qp_cq_id;
730 	u16 ae_id;
731 	u16 wqe_idx;
732 	u8 tcp_state;
733 	u8 iwarp_state;
734 	bool qp;
735 	bool cq;
736 	bool sq;
737 	bool in_rdrsp_wr;
738 	bool out_rdrsp;
739 	u8 q2_data_written;
740 	bool aeqe_overflow;
741 };
742 
743 struct i40iw_allocate_stag_info {
744 	u64 total_len;
745 	u32 chunk_size;
746 	u32 stag_idx;
747 	u32 page_size;
748 	u16 pd_id;
749 	u16 access_rights;
750 	bool remote_access;
751 	bool use_hmc_fcn_index;
752 	u8 hmc_fcn_index;
753 	bool use_pf_rid;
754 };
755 
756 struct i40iw_reg_ns_stag_info {
757 	u64 reg_addr_pa;
758 	u64 fbo;
759 	void *va;
760 	u64 total_len;
761 	u32 page_size;
762 	u32 chunk_size;
763 	u32 first_pm_pbl_index;
764 	enum i40iw_addressing_type addr_type;
765 	i40iw_stag_index stag_idx;
766 	u16 access_rights;
767 	u16 pd_id;
768 	i40iw_stag_key stag_key;
769 	bool use_hmc_fcn_index;
770 	u8 hmc_fcn_index;
771 	bool use_pf_rid;
772 };
773 
774 struct i40iw_fast_reg_stag_info {
775 	u64 wr_id;
776 	u64 reg_addr_pa;
777 	u64 fbo;
778 	void *va;
779 	u64 total_len;
780 	u32 page_size;
781 	u32 chunk_size;
782 	u32 first_pm_pbl_index;
783 	enum i40iw_addressing_type addr_type;
784 	i40iw_stag_index stag_idx;
785 	u16 access_rights;
786 	u16 pd_id;
787 	i40iw_stag_key stag_key;
788 	bool local_fence;
789 	bool read_fence;
790 	bool signaled;
791 	bool use_hmc_fcn_index;
792 	u8 hmc_fcn_index;
793 	bool use_pf_rid;
794 	bool defer_flag;
795 };
796 
797 struct i40iw_dealloc_stag_info {
798 	u32 stag_idx;
799 	u16 pd_id;
800 	bool mr;
801 	bool dealloc_pbl;
802 };
803 
804 struct i40iw_register_shared_stag {
805 	void *va;
806 	enum i40iw_addressing_type addr_type;
807 	i40iw_stag_index new_stag_idx;
808 	i40iw_stag_index parent_stag_idx;
809 	u32 access_rights;
810 	u16 pd_id;
811 	i40iw_stag_key new_stag_key;
812 };
813 
814 struct i40iw_qp_init_info {
815 	struct i40iw_qp_uk_init_info qp_uk_init_info;
816 	struct i40iw_sc_pd *pd;
817 	u64 *host_ctx;
818 	u8 *q2;
819 	u64 sq_pa;
820 	u64 rq_pa;
821 	u64 host_ctx_pa;
822 	u64 q2_pa;
823 	u64 shadow_area_pa;
824 	u8 sq_tph_val;
825 	u8 rq_tph_val;
826 	u8 type;
827 	bool sq_tph_en;
828 	bool rq_tph_en;
829 	bool rcv_tph_en;
830 	bool xmit_tph_en;
831 	bool virtual_map;
832 };
833 
834 struct i40iw_cq_init_info {
835 	struct i40iw_sc_dev *dev;
836 	u64 cq_base_pa;
837 	u64 shadow_area_pa;
838 	u32 ceq_id;
839 	u32 shadow_read_threshold;
840 	bool virtual_map;
841 	bool ceqe_mask;
842 	u8 pbl_chunk_size;
843 	u32 first_pm_pbl_idx;
844 	bool ceq_id_valid;
845 	bool tph_en;
846 	u8 tph_val;
847 	u8 type;
848 	struct i40iw_cq_uk_init_info cq_uk_init_info;
849 };
850 
851 struct i40iw_upload_context_info {
852 	u64 buf_pa;
853 	bool freeze_qp;
854 	bool raw_format;
855 	u32 qp_id;
856 	u8 qp_type;
857 };
858 
859 struct i40iw_add_arp_cache_entry_info {
860 	u8 mac_addr[6];
861 	u32 reach_max;
862 	u16 arp_index;
863 	bool permanent;
864 };
865 
866 struct i40iw_apbvt_info {
867 	u16 port;
868 	bool add;
869 };
870 
871 enum i40iw_quad_entry_type {
872 	I40IW_QHASH_TYPE_TCP_ESTABLISHED = 1,
873 	I40IW_QHASH_TYPE_TCP_SYN,
874 };
875 
876 enum i40iw_quad_hash_manage_type {
877 	I40IW_QHASH_MANAGE_TYPE_DELETE = 0,
878 	I40IW_QHASH_MANAGE_TYPE_ADD,
879 	I40IW_QHASH_MANAGE_TYPE_MODIFY
880 };
881 
882 struct i40iw_qhash_table_info {
883 	enum i40iw_quad_hash_manage_type manage;
884 	enum i40iw_quad_entry_type entry_type;
885 	bool vlan_valid;
886 	bool ipv4_valid;
887 	u8 mac_addr[6];
888 	u16 vlan_id;
889 	u16 qs_handle;
890 	u32 qp_num;
891 	u32 dest_ip[4];
892 	u32 src_ip[4];
893 	u16 dest_port;
894 	u16 src_port;
895 };
896 
897 struct i40iw_local_mac_ipaddr_entry_info {
898 	u8 mac_addr[6];
899 	u8 entry_idx;
900 };
901 
902 struct i40iw_cqp_manage_push_page_info {
903 	u32 push_idx;
904 	u16 qs_handle;
905 	u8 free_page;
906 };
907 
908 struct i40iw_qp_flush_info {
909 	u16 sq_minor_code;
910 	u16 sq_major_code;
911 	u16 rq_minor_code;
912 	u16 rq_major_code;
913 	u16 ae_code;
914 	u8 ae_source;
915 	bool sq;
916 	bool rq;
917 	bool userflushcode;
918 	bool generate_ae;
919 };
920 
921 struct i40iw_cqp_commit_fpm_values {
922 	u64 qp_base;
923 	u64 cq_base;
924 	u32 hte_base;
925 	u32 arp_base;
926 	u32 apbvt_inuse_base;
927 	u32 mr_base;
928 	u32 xf_base;
929 	u32 xffl_base;
930 	u32 q1_base;
931 	u32 q1fl_base;
932 	u32 fsimc_base;
933 	u32 fsiav_base;
934 	u32 pbl_base;
935 
936 	u32 qp_cnt;
937 	u32 cq_cnt;
938 	u32 hte_cnt;
939 	u32 arp_cnt;
940 	u32 mr_cnt;
941 	u32 xf_cnt;
942 	u32 xffl_cnt;
943 	u32 q1_cnt;
944 	u32 q1fl_cnt;
945 	u32 fsimc_cnt;
946 	u32 fsiav_cnt;
947 	u32 pbl_cnt;
948 };
949 
950 struct i40iw_cqp_query_fpm_values {
951 	u16 first_pe_sd_index;
952 	u32 qp_objsize;
953 	u32 cq_objsize;
954 	u32 hte_objsize;
955 	u32 arp_objsize;
956 	u32 mr_objsize;
957 	u32 xf_objsize;
958 	u32 q1_objsize;
959 	u32 fsimc_objsize;
960 	u32 fsiav_objsize;
961 
962 	u32 qp_max;
963 	u32 cq_max;
964 	u32 hte_max;
965 	u32 arp_max;
966 	u32 mr_max;
967 	u32 xf_max;
968 	u32 xffl_max;
969 	u32 q1_max;
970 	u32 q1fl_max;
971 	u32 fsimc_max;
972 	u32 fsiav_max;
973 	u32 pbl_max;
974 };
975 
976 struct i40iw_cqp_ops {
977 	enum i40iw_status_code (*cqp_init)(struct i40iw_sc_cqp *,
978 					   struct i40iw_cqp_init_info *);
979 	enum i40iw_status_code (*cqp_create)(struct i40iw_sc_cqp *, bool, u16 *, u16 *);
980 	void (*cqp_post_sq)(struct i40iw_sc_cqp *);
981 	u64 *(*cqp_get_next_send_wqe)(struct i40iw_sc_cqp *, u64 scratch);
982 	enum i40iw_status_code (*cqp_destroy)(struct i40iw_sc_cqp *);
983 	enum i40iw_status_code (*poll_for_cqp_op_done)(struct i40iw_sc_cqp *, u8,
984 						       struct i40iw_ccq_cqe_info *);
985 };
986 
987 struct i40iw_ccq_ops {
988 	enum i40iw_status_code (*ccq_init)(struct i40iw_sc_cq *,
989 					   struct i40iw_ccq_init_info *);
990 	enum i40iw_status_code (*ccq_create)(struct i40iw_sc_cq *, u64, bool, bool);
991 	enum i40iw_status_code (*ccq_destroy)(struct i40iw_sc_cq *, u64, bool);
992 	enum i40iw_status_code (*ccq_create_done)(struct i40iw_sc_cq *);
993 	enum i40iw_status_code (*ccq_get_cqe_info)(struct i40iw_sc_cq *,
994 						   struct i40iw_ccq_cqe_info *);
995 	void (*ccq_arm)(struct i40iw_sc_cq *);
996 };
997 
998 struct i40iw_ceq_ops {
999 	enum i40iw_status_code (*ceq_init)(struct i40iw_sc_ceq *,
1000 					   struct i40iw_ceq_init_info *);
1001 	enum i40iw_status_code (*ceq_create)(struct i40iw_sc_ceq *, u64, bool);
1002 	enum i40iw_status_code (*cceq_create_done)(struct i40iw_sc_ceq *);
1003 	enum i40iw_status_code (*cceq_destroy_done)(struct i40iw_sc_ceq *);
1004 	enum i40iw_status_code (*cceq_create)(struct i40iw_sc_ceq *, u64);
1005 	enum i40iw_status_code (*ceq_destroy)(struct i40iw_sc_ceq *, u64, bool);
1006 	void *(*process_ceq)(struct i40iw_sc_dev *, struct i40iw_sc_ceq *);
1007 };
1008 
1009 struct i40iw_aeq_ops {
1010 	enum i40iw_status_code (*aeq_init)(struct i40iw_sc_aeq *,
1011 					   struct i40iw_aeq_init_info *);
1012 	enum i40iw_status_code (*aeq_create)(struct i40iw_sc_aeq *, u64, bool);
1013 	enum i40iw_status_code (*aeq_destroy)(struct i40iw_sc_aeq *, u64, bool);
1014 	enum i40iw_status_code (*get_next_aeqe)(struct i40iw_sc_aeq *,
1015 						struct i40iw_aeqe_info *);
1016 	enum i40iw_status_code (*repost_aeq_entries)(struct i40iw_sc_dev *, u32);
1017 	enum i40iw_status_code (*aeq_create_done)(struct i40iw_sc_aeq *);
1018 	enum i40iw_status_code (*aeq_destroy_done)(struct i40iw_sc_aeq *);
1019 };
1020 
1021 struct i40iw_pd_ops {
1022 	void (*pd_init)(struct i40iw_sc_dev *, struct i40iw_sc_pd *, u16);
1023 };
1024 
1025 struct i40iw_priv_qp_ops {
1026 	enum i40iw_status_code (*qp_init)(struct i40iw_sc_qp *, struct i40iw_qp_init_info *);
1027 	enum i40iw_status_code (*qp_create)(struct i40iw_sc_qp *,
1028 					    struct i40iw_create_qp_info *, u64, bool);
1029 	enum i40iw_status_code (*qp_modify)(struct i40iw_sc_qp *,
1030 					    struct i40iw_modify_qp_info *, u64, bool);
1031 	enum i40iw_status_code (*qp_destroy)(struct i40iw_sc_qp *, u64, bool, bool, bool);
1032 	enum i40iw_status_code (*qp_flush_wqes)(struct i40iw_sc_qp *,
1033 						struct i40iw_qp_flush_info *, u64, bool);
1034 	enum i40iw_status_code (*qp_upload_context)(struct i40iw_sc_dev *,
1035 						    struct i40iw_upload_context_info *,
1036 						    u64, bool);
1037 	enum i40iw_status_code (*qp_setctx)(struct i40iw_sc_qp *, u64 *,
1038 					    struct i40iw_qp_host_ctx_info *);
1039 
1040 	void (*qp_send_lsmm)(struct i40iw_sc_qp *, void *, u32, i40iw_stag);
1041 	void (*qp_send_lsmm_nostag)(struct i40iw_sc_qp *, void *, u32);
1042 	void (*qp_send_rtt)(struct i40iw_sc_qp *, bool);
1043 	enum i40iw_status_code (*qp_post_wqe0)(struct i40iw_sc_qp *, u8);
1044 	enum i40iw_status_code (*iw_mr_fast_register)(struct i40iw_sc_qp *,
1045 						      struct i40iw_fast_reg_stag_info *,
1046 						      bool);
1047 };
1048 
1049 struct i40iw_priv_cq_ops {
1050 	enum i40iw_status_code (*cq_init)(struct i40iw_sc_cq *, struct i40iw_cq_init_info *);
1051 	enum i40iw_status_code (*cq_create)(struct i40iw_sc_cq *, u64, bool, bool);
1052 	enum i40iw_status_code (*cq_destroy)(struct i40iw_sc_cq *, u64, bool);
1053 	enum i40iw_status_code (*cq_modify)(struct i40iw_sc_cq *,
1054 					    struct i40iw_modify_cq_info *, u64, bool);
1055 };
1056 
1057 struct i40iw_mr_ops {
1058 	enum i40iw_status_code (*alloc_stag)(struct i40iw_sc_dev *,
1059 					     struct i40iw_allocate_stag_info *, u64, bool);
1060 	enum i40iw_status_code (*mr_reg_non_shared)(struct i40iw_sc_dev *,
1061 						    struct i40iw_reg_ns_stag_info *,
1062 						    u64, bool);
1063 	enum i40iw_status_code (*mr_reg_shared)(struct i40iw_sc_dev *,
1064 						struct i40iw_register_shared_stag *,
1065 						u64, bool);
1066 	enum i40iw_status_code (*dealloc_stag)(struct i40iw_sc_dev *,
1067 					       struct i40iw_dealloc_stag_info *,
1068 					       u64, bool);
1069 	enum i40iw_status_code (*query_stag)(struct i40iw_sc_dev *, u64, u32, bool);
1070 	enum i40iw_status_code (*mw_alloc)(struct i40iw_sc_dev *, u64, u32, u16, bool);
1071 };
1072 
1073 struct i40iw_cqp_misc_ops {
1074 	enum i40iw_status_code (*manage_push_page)(struct i40iw_sc_cqp *,
1075 						   struct i40iw_cqp_manage_push_page_info *,
1076 						   u64, bool);
1077 	enum i40iw_status_code (*manage_hmc_pm_func_table)(struct i40iw_sc_cqp *,
1078 							   u64, u8, bool, bool);
1079 	enum i40iw_status_code (*set_hmc_resource_profile)(struct i40iw_sc_cqp *,
1080 							   u64, u8, u8, bool, bool);
1081 	enum i40iw_status_code (*commit_fpm_values)(struct i40iw_sc_cqp *, u64, u8,
1082 						    struct i40iw_dma_mem *, bool, u8);
1083 	enum i40iw_status_code (*query_fpm_values)(struct i40iw_sc_cqp *, u64, u8,
1084 						   struct i40iw_dma_mem *, bool, u8);
1085 	enum i40iw_status_code (*static_hmc_pages_allocated)(struct i40iw_sc_cqp *,
1086 							     u64, u8, bool, bool);
1087 	enum i40iw_status_code (*add_arp_cache_entry)(struct i40iw_sc_cqp *,
1088 						      struct i40iw_add_arp_cache_entry_info *,
1089 						      u64, bool);
1090 	enum i40iw_status_code (*del_arp_cache_entry)(struct i40iw_sc_cqp *, u64, u16, bool);
1091 	enum i40iw_status_code (*query_arp_cache_entry)(struct i40iw_sc_cqp *, u64, u16, bool);
1092 	enum i40iw_status_code (*manage_apbvt_entry)(struct i40iw_sc_cqp *,
1093 						     struct i40iw_apbvt_info *, u64, bool);
1094 	enum i40iw_status_code (*manage_qhash_table_entry)(struct i40iw_sc_cqp *,
1095 							   struct i40iw_qhash_table_info *, u64, bool);
1096 	enum i40iw_status_code (*alloc_local_mac_ipaddr_table_entry)(struct i40iw_sc_cqp *, u64, bool);
1097 	enum i40iw_status_code (*add_local_mac_ipaddr_entry)(struct i40iw_sc_cqp *,
1098 							     struct i40iw_local_mac_ipaddr_entry_info *,
1099 							     u64, bool);
1100 	enum i40iw_status_code (*del_local_mac_ipaddr_entry)(struct i40iw_sc_cqp *, u64, u8, u8, bool);
1101 	enum i40iw_status_code (*cqp_nop)(struct i40iw_sc_cqp *, u64, bool);
1102 	enum i40iw_status_code (*commit_fpm_values_done)(struct i40iw_sc_cqp
1103 							  *);
1104 	enum i40iw_status_code (*query_fpm_values_done)(struct i40iw_sc_cqp *);
1105 	enum i40iw_status_code (*manage_hmc_pm_func_table_done)(struct i40iw_sc_cqp *);
1106 	enum i40iw_status_code (*update_suspend_qp)(struct i40iw_sc_cqp *, struct i40iw_sc_qp *, u64);
1107 	enum i40iw_status_code (*update_resume_qp)(struct i40iw_sc_cqp *, struct i40iw_sc_qp *, u64);
1108 };
1109 
1110 struct i40iw_hmc_ops {
1111 	enum i40iw_status_code (*init_iw_hmc)(struct i40iw_sc_dev *, u8);
1112 	enum i40iw_status_code (*parse_fpm_query_buf)(u64 *, struct i40iw_hmc_info *,
1113 						      struct i40iw_hmc_fpm_misc *);
1114 	enum i40iw_status_code (*configure_iw_fpm)(struct i40iw_sc_dev *, u8);
1115 	enum i40iw_status_code (*parse_fpm_commit_buf)(u64 *, struct i40iw_hmc_obj_info *, u32 *sd);
1116 	enum i40iw_status_code (*create_hmc_object)(struct i40iw_sc_dev *dev,
1117 						    struct i40iw_hmc_create_obj_info *);
1118 	enum i40iw_status_code (*del_hmc_object)(struct i40iw_sc_dev *dev,
1119 						 struct i40iw_hmc_del_obj_info *,
1120 						 bool reset);
1121 	enum i40iw_status_code (*pf_init_vfhmc)(struct i40iw_sc_dev *, u8, u32 *);
1122 	enum i40iw_status_code (*vf_configure_vffpm)(struct i40iw_sc_dev *, u32 *);
1123 };
1124 
1125 struct cqp_info {
1126 	union {
1127 		struct {
1128 			struct i40iw_sc_qp *qp;
1129 			struct i40iw_create_qp_info info;
1130 			u64 scratch;
1131 		} qp_create;
1132 
1133 		struct {
1134 			struct i40iw_sc_qp *qp;
1135 			struct i40iw_modify_qp_info info;
1136 			u64 scratch;
1137 		} qp_modify;
1138 
1139 		struct {
1140 			struct i40iw_sc_qp *qp;
1141 			u64 scratch;
1142 			bool remove_hash_idx;
1143 			bool ignore_mw_bnd;
1144 		} qp_destroy;
1145 
1146 		struct {
1147 			struct i40iw_sc_cq *cq;
1148 			u64 scratch;
1149 			bool check_overflow;
1150 		} cq_create;
1151 
1152 		struct {
1153 			struct i40iw_sc_cq *cq;
1154 			u64 scratch;
1155 		} cq_destroy;
1156 
1157 		struct {
1158 			struct i40iw_sc_dev *dev;
1159 			struct i40iw_allocate_stag_info info;
1160 			u64 scratch;
1161 		} alloc_stag;
1162 
1163 		struct {
1164 			struct i40iw_sc_dev *dev;
1165 			u64 scratch;
1166 			u32 mw_stag_index;
1167 			u16 pd_id;
1168 		} mw_alloc;
1169 
1170 		struct {
1171 			struct i40iw_sc_dev *dev;
1172 			struct i40iw_reg_ns_stag_info info;
1173 			u64 scratch;
1174 		} mr_reg_non_shared;
1175 
1176 		struct {
1177 			struct i40iw_sc_dev *dev;
1178 			struct i40iw_dealloc_stag_info info;
1179 			u64 scratch;
1180 		} dealloc_stag;
1181 
1182 		struct {
1183 			struct i40iw_sc_cqp *cqp;
1184 			struct i40iw_local_mac_ipaddr_entry_info info;
1185 			u64 scratch;
1186 		} add_local_mac_ipaddr_entry;
1187 
1188 		struct {
1189 			struct i40iw_sc_cqp *cqp;
1190 			struct i40iw_add_arp_cache_entry_info info;
1191 			u64 scratch;
1192 		} add_arp_cache_entry;
1193 
1194 		struct {
1195 			struct i40iw_sc_cqp *cqp;
1196 			u64 scratch;
1197 			u8 entry_idx;
1198 			u8 ignore_ref_count;
1199 		} del_local_mac_ipaddr_entry;
1200 
1201 		struct {
1202 			struct i40iw_sc_cqp *cqp;
1203 			u64 scratch;
1204 			u16 arp_index;
1205 		} del_arp_cache_entry;
1206 
1207 		struct {
1208 			struct i40iw_sc_cqp *cqp;
1209 			struct i40iw_manage_vf_pble_info info;
1210 			u64 scratch;
1211 		} manage_vf_pble_bp;
1212 
1213 		struct {
1214 			struct i40iw_sc_cqp *cqp;
1215 			struct i40iw_cqp_manage_push_page_info info;
1216 			u64 scratch;
1217 		} manage_push_page;
1218 
1219 		struct {
1220 			struct i40iw_sc_dev *dev;
1221 			struct i40iw_upload_context_info info;
1222 			u64 scratch;
1223 		} qp_upload_context;
1224 
1225 		struct {
1226 			struct i40iw_sc_cqp *cqp;
1227 			u64 scratch;
1228 		} alloc_local_mac_ipaddr_entry;
1229 
1230 		struct {
1231 			struct i40iw_sc_dev *dev;
1232 			struct i40iw_hmc_fcn_info info;
1233 			u64 scratch;
1234 		} manage_hmc_pm;
1235 
1236 		struct {
1237 			struct i40iw_sc_ceq *ceq;
1238 			u64 scratch;
1239 		} ceq_create;
1240 
1241 		struct {
1242 			struct i40iw_sc_ceq *ceq;
1243 			u64 scratch;
1244 		} ceq_destroy;
1245 
1246 		struct {
1247 			struct i40iw_sc_aeq *aeq;
1248 			u64 scratch;
1249 		} aeq_create;
1250 
1251 		struct {
1252 			struct i40iw_sc_aeq *aeq;
1253 			u64 scratch;
1254 		} aeq_destroy;
1255 
1256 		struct {
1257 			struct i40iw_sc_qp *qp;
1258 			struct i40iw_qp_flush_info info;
1259 			u64 scratch;
1260 		} qp_flush_wqes;
1261 
1262 		struct {
1263 			struct i40iw_sc_cqp *cqp;
1264 			void *fpm_values_va;
1265 			u64 fpm_values_pa;
1266 			u8 hmc_fn_id;
1267 			u64 scratch;
1268 		} query_fpm_values;
1269 
1270 		struct {
1271 			struct i40iw_sc_cqp *cqp;
1272 			void *fpm_values_va;
1273 			u64 fpm_values_pa;
1274 			u8 hmc_fn_id;
1275 			u64 scratch;
1276 		} commit_fpm_values;
1277 
1278 		struct {
1279 			struct i40iw_sc_cqp *cqp;
1280 			struct i40iw_apbvt_info info;
1281 			u64 scratch;
1282 		} manage_apbvt_entry;
1283 
1284 		struct {
1285 			struct i40iw_sc_cqp *cqp;
1286 			struct i40iw_qhash_table_info info;
1287 			u64 scratch;
1288 		} manage_qhash_table_entry;
1289 
1290 		struct {
1291 			struct i40iw_sc_dev *dev;
1292 			struct i40iw_update_sds_info info;
1293 			u64 scratch;
1294 		} update_pe_sds;
1295 
1296 		struct {
1297 			struct i40iw_sc_cqp *cqp;
1298 			struct i40iw_sc_qp *qp;
1299 			u64 scratch;
1300 		} suspend_resume;
1301 	} u;
1302 };
1303 
1304 struct cqp_commands_info {
1305 	struct list_head cqp_cmd_entry;
1306 	u8 cqp_cmd;
1307 	u8 post_sq;
1308 	struct cqp_info in;
1309 };
1310 
1311 struct i40iw_virtchnl_work_info {
1312 	void (*callback_fcn)(void *vf_dev);
1313 	void *worker_vf_dev;
1314 };
1315 
1316 #endif
1317