1 /*
2 * Copyright (C) 2014 ARM Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/cpu.h>
10 #include <linux/init.h>
11 #include <linux/list.h>
12 #include <linux/perf_event.h>
13 #include <linux/sched.h>
14 #include <linux/slab.h>
15 #include <linux/sysctl.h>
16
17 #include <asm/cpufeature.h>
18 #include <asm/insn.h>
19 #include <asm/opcodes.h>
20 #include <asm/sysreg.h>
21 #include <asm/system_misc.h>
22 #include <asm/traps.h>
23 #include <asm/uaccess.h>
24 #include <asm/cpufeature.h>
25
26 #define CREATE_TRACE_POINTS
27 #include "trace-events-emulation.h"
28
29 /*
30 * The runtime support for deprecated instruction support can be in one of
31 * following three states -
32 *
33 * 0 = undef
34 * 1 = emulate (software emulation)
35 * 2 = hw (supported in hardware)
36 */
37 enum insn_emulation_mode {
38 INSN_UNDEF,
39 INSN_EMULATE,
40 INSN_HW,
41 };
42
43 enum legacy_insn_status {
44 INSN_DEPRECATED,
45 INSN_OBSOLETE,
46 };
47
48 struct insn_emulation_ops {
49 const char *name;
50 enum legacy_insn_status status;
51 struct undef_hook *hooks;
52 int (*set_hw_mode)(bool enable);
53 };
54
55 struct insn_emulation {
56 struct list_head node;
57 struct insn_emulation_ops *ops;
58 int current_mode;
59 int min;
60 int max;
61 };
62
63 static LIST_HEAD(insn_emulation);
64 static int nr_insn_emulated __initdata;
65 static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
66
register_emulation_hooks(struct insn_emulation_ops * ops)67 static void register_emulation_hooks(struct insn_emulation_ops *ops)
68 {
69 struct undef_hook *hook;
70
71 BUG_ON(!ops->hooks);
72
73 for (hook = ops->hooks; hook->instr_mask; hook++)
74 register_undef_hook(hook);
75
76 pr_notice("Registered %s emulation handler\n", ops->name);
77 }
78
remove_emulation_hooks(struct insn_emulation_ops * ops)79 static void remove_emulation_hooks(struct insn_emulation_ops *ops)
80 {
81 struct undef_hook *hook;
82
83 BUG_ON(!ops->hooks);
84
85 for (hook = ops->hooks; hook->instr_mask; hook++)
86 unregister_undef_hook(hook);
87
88 pr_notice("Removed %s emulation handler\n", ops->name);
89 }
90
enable_insn_hw_mode(void * data)91 static void enable_insn_hw_mode(void *data)
92 {
93 struct insn_emulation *insn = (struct insn_emulation *)data;
94 if (insn->ops->set_hw_mode)
95 insn->ops->set_hw_mode(true);
96 }
97
disable_insn_hw_mode(void * data)98 static void disable_insn_hw_mode(void *data)
99 {
100 struct insn_emulation *insn = (struct insn_emulation *)data;
101 if (insn->ops->set_hw_mode)
102 insn->ops->set_hw_mode(false);
103 }
104
105 /* Run set_hw_mode(mode) on all active CPUs */
run_all_cpu_set_hw_mode(struct insn_emulation * insn,bool enable)106 static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
107 {
108 if (!insn->ops->set_hw_mode)
109 return -EINVAL;
110 if (enable)
111 on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
112 else
113 on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
114 return 0;
115 }
116
117 /*
118 * Run set_hw_mode for all insns on a starting CPU.
119 * Returns:
120 * 0 - If all the hooks ran successfully.
121 * -EINVAL - At least one hook is not supported by the CPU.
122 */
run_all_insn_set_hw_mode(unsigned int cpu)123 static int run_all_insn_set_hw_mode(unsigned int cpu)
124 {
125 int rc = 0;
126 unsigned long flags;
127 struct insn_emulation *insn;
128
129 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
130 list_for_each_entry(insn, &insn_emulation, node) {
131 bool enable = (insn->current_mode == INSN_HW);
132 if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
133 pr_warn("CPU[%u] cannot support the emulation of %s",
134 cpu, insn->ops->name);
135 rc = -EINVAL;
136 }
137 }
138 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
139 return rc;
140 }
141
update_insn_emulation_mode(struct insn_emulation * insn,enum insn_emulation_mode prev)142 static int update_insn_emulation_mode(struct insn_emulation *insn,
143 enum insn_emulation_mode prev)
144 {
145 int ret = 0;
146
147 switch (prev) {
148 case INSN_UNDEF: /* Nothing to be done */
149 break;
150 case INSN_EMULATE:
151 remove_emulation_hooks(insn->ops);
152 break;
153 case INSN_HW:
154 if (!run_all_cpu_set_hw_mode(insn, false))
155 pr_notice("Disabled %s support\n", insn->ops->name);
156 break;
157 }
158
159 switch (insn->current_mode) {
160 case INSN_UNDEF:
161 break;
162 case INSN_EMULATE:
163 register_emulation_hooks(insn->ops);
164 break;
165 case INSN_HW:
166 ret = run_all_cpu_set_hw_mode(insn, true);
167 if (!ret)
168 pr_notice("Enabled %s support\n", insn->ops->name);
169 break;
170 }
171
172 return ret;
173 }
174
register_insn_emulation(struct insn_emulation_ops * ops)175 static void __init register_insn_emulation(struct insn_emulation_ops *ops)
176 {
177 unsigned long flags;
178 struct insn_emulation *insn;
179
180 insn = kzalloc(sizeof(*insn), GFP_KERNEL);
181 insn->ops = ops;
182 insn->min = INSN_UNDEF;
183
184 switch (ops->status) {
185 case INSN_DEPRECATED:
186 insn->current_mode = INSN_EMULATE;
187 /* Disable the HW mode if it was turned on at early boot time */
188 run_all_cpu_set_hw_mode(insn, false);
189 insn->max = INSN_HW;
190 break;
191 case INSN_OBSOLETE:
192 insn->current_mode = INSN_UNDEF;
193 insn->max = INSN_EMULATE;
194 break;
195 }
196
197 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
198 list_add(&insn->node, &insn_emulation);
199 nr_insn_emulated++;
200 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
201
202 /* Register any handlers if required */
203 update_insn_emulation_mode(insn, INSN_UNDEF);
204 }
205
emulation_proc_handler(struct ctl_table * table,int write,void __user * buffer,size_t * lenp,loff_t * ppos)206 static int emulation_proc_handler(struct ctl_table *table, int write,
207 void __user *buffer, size_t *lenp,
208 loff_t *ppos)
209 {
210 int ret = 0;
211 struct insn_emulation *insn = (struct insn_emulation *) table->data;
212 enum insn_emulation_mode prev_mode = insn->current_mode;
213
214 table->data = &insn->current_mode;
215 ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
216
217 if (ret || !write || prev_mode == insn->current_mode)
218 goto ret;
219
220 ret = update_insn_emulation_mode(insn, prev_mode);
221 if (ret) {
222 /* Mode change failed, revert to previous mode. */
223 insn->current_mode = prev_mode;
224 update_insn_emulation_mode(insn, INSN_UNDEF);
225 }
226 ret:
227 table->data = insn;
228 return ret;
229 }
230
231 static struct ctl_table ctl_abi[] = {
232 {
233 .procname = "abi",
234 .mode = 0555,
235 },
236 { }
237 };
238
register_insn_emulation_sysctl(struct ctl_table * table)239 static void __init register_insn_emulation_sysctl(struct ctl_table *table)
240 {
241 unsigned long flags;
242 int i = 0;
243 struct insn_emulation *insn;
244 struct ctl_table *insns_sysctl, *sysctl;
245
246 insns_sysctl = kzalloc(sizeof(*sysctl) * (nr_insn_emulated + 1),
247 GFP_KERNEL);
248
249 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
250 list_for_each_entry(insn, &insn_emulation, node) {
251 sysctl = &insns_sysctl[i];
252
253 sysctl->mode = 0644;
254 sysctl->maxlen = sizeof(int);
255
256 sysctl->procname = insn->ops->name;
257 sysctl->data = insn;
258 sysctl->extra1 = &insn->min;
259 sysctl->extra2 = &insn->max;
260 sysctl->proc_handler = emulation_proc_handler;
261 i++;
262 }
263 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
264
265 table->child = insns_sysctl;
266 register_sysctl_table(table);
267 }
268
269 /*
270 * Implement emulation of the SWP/SWPB instructions using load-exclusive and
271 * store-exclusive.
272 *
273 * Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
274 * Where: Rt = destination
275 * Rt2 = source
276 * Rn = address
277 */
278
279 /*
280 * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
281 */
282
283 /* Arbitrary constant to ensure forward-progress of the LL/SC loop */
284 #define __SWP_LL_SC_LOOPS 4
285
286 #define __user_swpX_asm(data, addr, res, temp, temp2, B) \
287 do { \
288 uaccess_enable(); \
289 __asm__ __volatile__( \
290 " mov %w3, %w7\n" \
291 "0: ldxr"B" %w2, [%4]\n" \
292 "1: stxr"B" %w0, %w1, [%4]\n" \
293 " cbz %w0, 2f\n" \
294 " sub %w3, %w3, #1\n" \
295 " cbnz %w3, 0b\n" \
296 " mov %w0, %w5\n" \
297 " b 3f\n" \
298 "2:\n" \
299 " mov %w1, %w2\n" \
300 "3:\n" \
301 " .pushsection .fixup,\"ax\"\n" \
302 " .align 2\n" \
303 "4: mov %w0, %w6\n" \
304 " b 3b\n" \
305 " .popsection" \
306 _ASM_EXTABLE(0b, 4b) \
307 _ASM_EXTABLE(1b, 4b) \
308 : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
309 : "r" ((unsigned long)addr), "i" (-EAGAIN), \
310 "i" (-EFAULT), \
311 "i" (__SWP_LL_SC_LOOPS) \
312 : "memory"); \
313 uaccess_disable(); \
314 } while (0)
315
316 #define __user_swp_asm(data, addr, res, temp, temp2) \
317 __user_swpX_asm(data, addr, res, temp, temp2, "")
318 #define __user_swpb_asm(data, addr, res, temp, temp2) \
319 __user_swpX_asm(data, addr, res, temp, temp2, "b")
320
321 /*
322 * Bit 22 of the instruction encoding distinguishes between
323 * the SWP and SWPB variants (bit set means SWPB).
324 */
325 #define TYPE_SWPB (1 << 22)
326
emulate_swpX(unsigned int address,unsigned int * data,unsigned int type)327 static int emulate_swpX(unsigned int address, unsigned int *data,
328 unsigned int type)
329 {
330 unsigned int res = 0;
331
332 if ((type != TYPE_SWPB) && (address & 0x3)) {
333 /* SWP to unaligned address not permitted */
334 pr_debug("SWP instruction on unaligned pointer!\n");
335 return -EFAULT;
336 }
337
338 while (1) {
339 unsigned long temp, temp2;
340
341 if (type == TYPE_SWPB)
342 __user_swpb_asm(*data, address, res, temp, temp2);
343 else
344 __user_swp_asm(*data, address, res, temp, temp2);
345
346 if (likely(res != -EAGAIN) || signal_pending(current))
347 break;
348
349 cond_resched();
350 }
351
352 return res;
353 }
354
355 #define ARM_OPCODE_CONDITION_UNCOND 0xf
356
aarch32_check_condition(u32 opcode,u32 psr)357 static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
358 {
359 u32 cc_bits = opcode >> 28;
360
361 if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
362 if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
363 return ARM_OPCODE_CONDTEST_PASS;
364 else
365 return ARM_OPCODE_CONDTEST_FAIL;
366 }
367 return ARM_OPCODE_CONDTEST_UNCOND;
368 }
369
370 /*
371 * swp_handler logs the id of calling process, dissects the instruction, sanity
372 * checks the memory location, calls emulate_swpX for the actual operation and
373 * deals with fixup/error handling before returning
374 */
swp_handler(struct pt_regs * regs,u32 instr)375 static int swp_handler(struct pt_regs *regs, u32 instr)
376 {
377 u32 destreg, data, type, address = 0;
378 int rn, rt2, res = 0;
379
380 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
381
382 type = instr & TYPE_SWPB;
383
384 switch (aarch32_check_condition(instr, regs->pstate)) {
385 case ARM_OPCODE_CONDTEST_PASS:
386 break;
387 case ARM_OPCODE_CONDTEST_FAIL:
388 /* Condition failed - return to next instruction */
389 goto ret;
390 case ARM_OPCODE_CONDTEST_UNCOND:
391 /* If unconditional encoding - not a SWP, undef */
392 return -EFAULT;
393 default:
394 return -EINVAL;
395 }
396
397 rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
398 rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
399
400 address = (u32)regs->user_regs.regs[rn];
401 data = (u32)regs->user_regs.regs[rt2];
402 destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
403
404 pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
405 rn, address, destreg,
406 aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
407
408 /* Check access in reasonable access range for both SWP and SWPB */
409 if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
410 pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
411 address);
412 goto fault;
413 }
414
415 res = emulate_swpX(address, &data, type);
416 if (res == -EFAULT)
417 goto fault;
418 else if (res == 0)
419 regs->user_regs.regs[destreg] = data;
420
421 ret:
422 if (type == TYPE_SWPB)
423 trace_instruction_emulation("swpb", regs->pc);
424 else
425 trace_instruction_emulation("swp", regs->pc);
426
427 pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
428 current->comm, (unsigned long)current->pid, regs->pc);
429
430 regs->pc += 4;
431 return 0;
432
433 fault:
434 pr_debug("SWP{B} emulation: access caused memory abort!\n");
435 arm64_notify_segfault(regs, address);
436
437 return 0;
438 }
439
440 /*
441 * Only emulate SWP/SWPB executed in ARM state/User mode.
442 * The kernel must be SWP free and SWP{B} does not exist in Thumb.
443 */
444 static struct undef_hook swp_hooks[] = {
445 {
446 .instr_mask = 0x0fb00ff0,
447 .instr_val = 0x01000090,
448 .pstate_mask = COMPAT_PSR_MODE_MASK,
449 .pstate_val = COMPAT_PSR_MODE_USR,
450 .fn = swp_handler
451 },
452 { }
453 };
454
455 static struct insn_emulation_ops swp_ops = {
456 .name = "swp",
457 .status = INSN_OBSOLETE,
458 .hooks = swp_hooks,
459 .set_hw_mode = NULL,
460 };
461
cp15barrier_handler(struct pt_regs * regs,u32 instr)462 static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
463 {
464 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
465
466 switch (aarch32_check_condition(instr, regs->pstate)) {
467 case ARM_OPCODE_CONDTEST_PASS:
468 break;
469 case ARM_OPCODE_CONDTEST_FAIL:
470 /* Condition failed - return to next instruction */
471 goto ret;
472 case ARM_OPCODE_CONDTEST_UNCOND:
473 /* If unconditional encoding - not a barrier instruction */
474 return -EFAULT;
475 default:
476 return -EINVAL;
477 }
478
479 switch (aarch32_insn_mcr_extract_crm(instr)) {
480 case 10:
481 /*
482 * dmb - mcr p15, 0, Rt, c7, c10, 5
483 * dsb - mcr p15, 0, Rt, c7, c10, 4
484 */
485 if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
486 dmb(sy);
487 trace_instruction_emulation(
488 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
489 } else {
490 dsb(sy);
491 trace_instruction_emulation(
492 "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
493 }
494 break;
495 case 5:
496 /*
497 * isb - mcr p15, 0, Rt, c7, c5, 4
498 *
499 * Taking an exception or returning from one acts as an
500 * instruction barrier. So no explicit barrier needed here.
501 */
502 trace_instruction_emulation(
503 "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
504 break;
505 }
506
507 ret:
508 pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
509 current->comm, (unsigned long)current->pid, regs->pc);
510
511 regs->pc += 4;
512 return 0;
513 }
514
cp15_barrier_set_hw_mode(bool enable)515 static int cp15_barrier_set_hw_mode(bool enable)
516 {
517 if (enable)
518 config_sctlr_el1(0, SCTLR_EL1_CP15BEN);
519 else
520 config_sctlr_el1(SCTLR_EL1_CP15BEN, 0);
521 return 0;
522 }
523
524 static struct undef_hook cp15_barrier_hooks[] = {
525 {
526 .instr_mask = 0x0fff0fdf,
527 .instr_val = 0x0e070f9a,
528 .pstate_mask = COMPAT_PSR_MODE_MASK,
529 .pstate_val = COMPAT_PSR_MODE_USR,
530 .fn = cp15barrier_handler,
531 },
532 {
533 .instr_mask = 0x0fff0fff,
534 .instr_val = 0x0e070f95,
535 .pstate_mask = COMPAT_PSR_MODE_MASK,
536 .pstate_val = COMPAT_PSR_MODE_USR,
537 .fn = cp15barrier_handler,
538 },
539 { }
540 };
541
542 static struct insn_emulation_ops cp15_barrier_ops = {
543 .name = "cp15_barrier",
544 .status = INSN_DEPRECATED,
545 .hooks = cp15_barrier_hooks,
546 .set_hw_mode = cp15_barrier_set_hw_mode,
547 };
548
setend_set_hw_mode(bool enable)549 static int setend_set_hw_mode(bool enable)
550 {
551 if (!cpu_supports_mixed_endian_el0())
552 return -EINVAL;
553
554 if (enable)
555 config_sctlr_el1(SCTLR_EL1_SED, 0);
556 else
557 config_sctlr_el1(0, SCTLR_EL1_SED);
558 return 0;
559 }
560
compat_setend_handler(struct pt_regs * regs,u32 big_endian)561 static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
562 {
563 char *insn;
564
565 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
566
567 if (big_endian) {
568 insn = "setend be";
569 regs->pstate |= COMPAT_PSR_E_BIT;
570 } else {
571 insn = "setend le";
572 regs->pstate &= ~COMPAT_PSR_E_BIT;
573 }
574
575 trace_instruction_emulation(insn, regs->pc);
576 pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
577 current->comm, (unsigned long)current->pid, regs->pc);
578
579 return 0;
580 }
581
a32_setend_handler(struct pt_regs * regs,u32 instr)582 static int a32_setend_handler(struct pt_regs *regs, u32 instr)
583 {
584 int rc = compat_setend_handler(regs, (instr >> 9) & 1);
585 regs->pc += 4;
586 return rc;
587 }
588
t16_setend_handler(struct pt_regs * regs,u32 instr)589 static int t16_setend_handler(struct pt_regs *regs, u32 instr)
590 {
591 int rc = compat_setend_handler(regs, (instr >> 3) & 1);
592 regs->pc += 2;
593 return rc;
594 }
595
596 static struct undef_hook setend_hooks[] = {
597 {
598 .instr_mask = 0xfffffdff,
599 .instr_val = 0xf1010000,
600 .pstate_mask = COMPAT_PSR_MODE_MASK,
601 .pstate_val = COMPAT_PSR_MODE_USR,
602 .fn = a32_setend_handler,
603 },
604 {
605 /* Thumb mode */
606 .instr_mask = 0x0000fff7,
607 .instr_val = 0x0000b650,
608 .pstate_mask = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_MASK),
609 .pstate_val = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_USR),
610 .fn = t16_setend_handler,
611 },
612 {}
613 };
614
615 static struct insn_emulation_ops setend_ops = {
616 .name = "setend",
617 .status = INSN_DEPRECATED,
618 .hooks = setend_hooks,
619 .set_hw_mode = setend_set_hw_mode,
620 };
621
622 /*
623 * Invoked as late_initcall, since not needed before init spawned.
624 */
armv8_deprecated_init(void)625 static int __init armv8_deprecated_init(void)
626 {
627 if (IS_ENABLED(CONFIG_SWP_EMULATION))
628 register_insn_emulation(&swp_ops);
629
630 if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
631 register_insn_emulation(&cp15_barrier_ops);
632
633 if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
634 if(system_supports_mixed_endian_el0())
635 register_insn_emulation(&setend_ops);
636 else
637 pr_info("setend instruction emulation is not supported on the system");
638 }
639
640 cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
641 "AP_ARM64_ISNDEP_STARTING",
642 run_all_insn_set_hw_mode, NULL);
643 register_insn_emulation_sysctl(ctl_abi);
644
645 return 0;
646 }
647
648 late_initcall(armv8_deprecated_init);
649