1 /*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
30
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
35
36 #include <video/display_timing.h>
37 #include <video/videomode.h>
38
39 struct panel_desc {
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
42 const struct display_timing *timings;
43 unsigned int num_timings;
44
45 unsigned int bpc;
46
47 /**
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
50 */
51 struct {
52 unsigned int width;
53 unsigned int height;
54 } size;
55
56 /**
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @enable: the time (in milliseconds) that it takes for the panel to
60 * display the first valid frame after starting to receive
61 * video data
62 * @disable: the time (in milliseconds) that it takes for the panel to
63 * turn the display off (no content is visible)
64 * @unprepare: the time (in milliseconds) that it takes for the panel
65 * to power itself down completely
66 */
67 struct {
68 unsigned int prepare;
69 unsigned int enable;
70 unsigned int disable;
71 unsigned int unprepare;
72 } delay;
73
74 u32 bus_format;
75 u32 bus_flags;
76 };
77
78 struct panel_simple {
79 struct drm_panel base;
80 bool prepared;
81 bool enabled;
82
83 const struct panel_desc *desc;
84
85 struct backlight_device *backlight;
86 struct regulator *supply;
87 struct i2c_adapter *ddc;
88
89 struct gpio_desc *enable_gpio;
90 };
91
to_panel_simple(struct drm_panel * panel)92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
93 {
94 return container_of(panel, struct panel_simple, base);
95 }
96
panel_simple_get_fixed_modes(struct panel_simple * panel)97 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
98 {
99 struct drm_connector *connector = panel->base.connector;
100 struct drm_device *drm = panel->base.drm;
101 struct drm_display_mode *mode;
102 unsigned int i, num = 0;
103
104 if (!panel->desc)
105 return 0;
106
107 for (i = 0; i < panel->desc->num_timings; i++) {
108 const struct display_timing *dt = &panel->desc->timings[i];
109 struct videomode vm;
110
111 videomode_from_timing(dt, &vm);
112 mode = drm_mode_create(drm);
113 if (!mode) {
114 dev_err(drm->dev, "failed to add mode %ux%u\n",
115 dt->hactive.typ, dt->vactive.typ);
116 continue;
117 }
118
119 drm_display_mode_from_videomode(&vm, mode);
120
121 mode->type |= DRM_MODE_TYPE_DRIVER;
122
123 if (panel->desc->num_timings == 1)
124 mode->type |= DRM_MODE_TYPE_PREFERRED;
125
126 drm_mode_probed_add(connector, mode);
127 num++;
128 }
129
130 for (i = 0; i < panel->desc->num_modes; i++) {
131 const struct drm_display_mode *m = &panel->desc->modes[i];
132
133 mode = drm_mode_duplicate(drm, m);
134 if (!mode) {
135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
136 m->hdisplay, m->vdisplay, m->vrefresh);
137 continue;
138 }
139
140 mode->type |= DRM_MODE_TYPE_DRIVER;
141
142 if (panel->desc->num_modes == 1)
143 mode->type |= DRM_MODE_TYPE_PREFERRED;
144
145 drm_mode_set_name(mode);
146
147 drm_mode_probed_add(connector, mode);
148 num++;
149 }
150
151 connector->display_info.bpc = panel->desc->bpc;
152 connector->display_info.width_mm = panel->desc->size.width;
153 connector->display_info.height_mm = panel->desc->size.height;
154 if (panel->desc->bus_format)
155 drm_display_info_set_bus_formats(&connector->display_info,
156 &panel->desc->bus_format, 1);
157 connector->display_info.bus_flags = panel->desc->bus_flags;
158
159 return num;
160 }
161
panel_simple_disable(struct drm_panel * panel)162 static int panel_simple_disable(struct drm_panel *panel)
163 {
164 struct panel_simple *p = to_panel_simple(panel);
165
166 if (!p->enabled)
167 return 0;
168
169 if (p->backlight) {
170 p->backlight->props.power = FB_BLANK_POWERDOWN;
171 p->backlight->props.state |= BL_CORE_FBBLANK;
172 backlight_update_status(p->backlight);
173 }
174
175 if (p->desc->delay.disable)
176 msleep(p->desc->delay.disable);
177
178 p->enabled = false;
179
180 return 0;
181 }
182
panel_simple_unprepare(struct drm_panel * panel)183 static int panel_simple_unprepare(struct drm_panel *panel)
184 {
185 struct panel_simple *p = to_panel_simple(panel);
186
187 if (!p->prepared)
188 return 0;
189
190 if (p->enable_gpio)
191 gpiod_set_value_cansleep(p->enable_gpio, 0);
192
193 regulator_disable(p->supply);
194
195 if (p->desc->delay.unprepare)
196 msleep(p->desc->delay.unprepare);
197
198 p->prepared = false;
199
200 return 0;
201 }
202
panel_simple_prepare(struct drm_panel * panel)203 static int panel_simple_prepare(struct drm_panel *panel)
204 {
205 struct panel_simple *p = to_panel_simple(panel);
206 int err;
207
208 if (p->prepared)
209 return 0;
210
211 err = regulator_enable(p->supply);
212 if (err < 0) {
213 dev_err(panel->dev, "failed to enable supply: %d\n", err);
214 return err;
215 }
216
217 if (p->enable_gpio)
218 gpiod_set_value_cansleep(p->enable_gpio, 1);
219
220 if (p->desc->delay.prepare)
221 msleep(p->desc->delay.prepare);
222
223 p->prepared = true;
224
225 return 0;
226 }
227
panel_simple_enable(struct drm_panel * panel)228 static int panel_simple_enable(struct drm_panel *panel)
229 {
230 struct panel_simple *p = to_panel_simple(panel);
231
232 if (p->enabled)
233 return 0;
234
235 if (p->desc->delay.enable)
236 msleep(p->desc->delay.enable);
237
238 if (p->backlight) {
239 p->backlight->props.state &= ~BL_CORE_FBBLANK;
240 p->backlight->props.power = FB_BLANK_UNBLANK;
241 backlight_update_status(p->backlight);
242 }
243
244 p->enabled = true;
245
246 return 0;
247 }
248
panel_simple_get_modes(struct drm_panel * panel)249 static int panel_simple_get_modes(struct drm_panel *panel)
250 {
251 struct panel_simple *p = to_panel_simple(panel);
252 int num = 0;
253
254 /* probe EDID if a DDC bus is available */
255 if (p->ddc) {
256 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
257 drm_mode_connector_update_edid_property(panel->connector, edid);
258 if (edid) {
259 num += drm_add_edid_modes(panel->connector, edid);
260 kfree(edid);
261 }
262 }
263
264 /* add hard-coded panel modes */
265 num += panel_simple_get_fixed_modes(p);
266
267 return num;
268 }
269
panel_simple_get_timings(struct drm_panel * panel,unsigned int num_timings,struct display_timing * timings)270 static int panel_simple_get_timings(struct drm_panel *panel,
271 unsigned int num_timings,
272 struct display_timing *timings)
273 {
274 struct panel_simple *p = to_panel_simple(panel);
275 unsigned int i;
276
277 if (p->desc->num_timings < num_timings)
278 num_timings = p->desc->num_timings;
279
280 if (timings)
281 for (i = 0; i < num_timings; i++)
282 timings[i] = p->desc->timings[i];
283
284 return p->desc->num_timings;
285 }
286
287 static const struct drm_panel_funcs panel_simple_funcs = {
288 .disable = panel_simple_disable,
289 .unprepare = panel_simple_unprepare,
290 .prepare = panel_simple_prepare,
291 .enable = panel_simple_enable,
292 .get_modes = panel_simple_get_modes,
293 .get_timings = panel_simple_get_timings,
294 };
295
panel_simple_probe(struct device * dev,const struct panel_desc * desc)296 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
297 {
298 struct device_node *backlight, *ddc;
299 struct panel_simple *panel;
300 int err;
301
302 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
303 if (!panel)
304 return -ENOMEM;
305
306 panel->enabled = false;
307 panel->prepared = false;
308 panel->desc = desc;
309
310 panel->supply = devm_regulator_get(dev, "power");
311 if (IS_ERR(panel->supply))
312 return PTR_ERR(panel->supply);
313
314 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
315 GPIOD_OUT_LOW);
316 if (IS_ERR(panel->enable_gpio)) {
317 err = PTR_ERR(panel->enable_gpio);
318 dev_err(dev, "failed to request GPIO: %d\n", err);
319 return err;
320 }
321
322 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
323 if (backlight) {
324 panel->backlight = of_find_backlight_by_node(backlight);
325 of_node_put(backlight);
326
327 if (!panel->backlight)
328 return -EPROBE_DEFER;
329 }
330
331 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
332 if (ddc) {
333 panel->ddc = of_find_i2c_adapter_by_node(ddc);
334 of_node_put(ddc);
335
336 if (!panel->ddc) {
337 err = -EPROBE_DEFER;
338 goto free_backlight;
339 }
340 }
341
342 drm_panel_init(&panel->base);
343 panel->base.dev = dev;
344 panel->base.funcs = &panel_simple_funcs;
345
346 err = drm_panel_add(&panel->base);
347 if (err < 0)
348 goto free_ddc;
349
350 dev_set_drvdata(dev, panel);
351
352 return 0;
353
354 free_ddc:
355 if (panel->ddc)
356 put_device(&panel->ddc->dev);
357 free_backlight:
358 if (panel->backlight)
359 put_device(&panel->backlight->dev);
360
361 return err;
362 }
363
panel_simple_remove(struct device * dev)364 static int panel_simple_remove(struct device *dev)
365 {
366 struct panel_simple *panel = dev_get_drvdata(dev);
367
368 drm_panel_detach(&panel->base);
369 drm_panel_remove(&panel->base);
370
371 panel_simple_disable(&panel->base);
372 panel_simple_unprepare(&panel->base);
373
374 if (panel->ddc)
375 put_device(&panel->ddc->dev);
376
377 if (panel->backlight)
378 put_device(&panel->backlight->dev);
379
380 return 0;
381 }
382
panel_simple_shutdown(struct device * dev)383 static void panel_simple_shutdown(struct device *dev)
384 {
385 struct panel_simple *panel = dev_get_drvdata(dev);
386
387 panel_simple_disable(&panel->base);
388 panel_simple_unprepare(&panel->base);
389 }
390
391 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
392 .clock = 33333,
393 .hdisplay = 800,
394 .hsync_start = 800 + 0,
395 .hsync_end = 800 + 0 + 255,
396 .htotal = 800 + 0 + 255 + 0,
397 .vdisplay = 480,
398 .vsync_start = 480 + 2,
399 .vsync_end = 480 + 2 + 45,
400 .vtotal = 480 + 2 + 45 + 0,
401 .vrefresh = 60,
402 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
403 };
404
405 static const struct panel_desc ampire_am800480r3tmqwa1h = {
406 .modes = &ire_am800480r3tmqwa1h_mode,
407 .num_modes = 1,
408 .bpc = 6,
409 .size = {
410 .width = 152,
411 .height = 91,
412 },
413 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
414 };
415
416 static const struct drm_display_mode auo_b101aw03_mode = {
417 .clock = 51450,
418 .hdisplay = 1024,
419 .hsync_start = 1024 + 156,
420 .hsync_end = 1024 + 156 + 8,
421 .htotal = 1024 + 156 + 8 + 156,
422 .vdisplay = 600,
423 .vsync_start = 600 + 16,
424 .vsync_end = 600 + 16 + 6,
425 .vtotal = 600 + 16 + 6 + 16,
426 .vrefresh = 60,
427 };
428
429 static const struct panel_desc auo_b101aw03 = {
430 .modes = &auo_b101aw03_mode,
431 .num_modes = 1,
432 .bpc = 6,
433 .size = {
434 .width = 223,
435 .height = 125,
436 },
437 };
438
439 static const struct drm_display_mode auo_b101ean01_mode = {
440 .clock = 72500,
441 .hdisplay = 1280,
442 .hsync_start = 1280 + 119,
443 .hsync_end = 1280 + 119 + 32,
444 .htotal = 1280 + 119 + 32 + 21,
445 .vdisplay = 800,
446 .vsync_start = 800 + 4,
447 .vsync_end = 800 + 4 + 20,
448 .vtotal = 800 + 4 + 20 + 8,
449 .vrefresh = 60,
450 };
451
452 static const struct panel_desc auo_b101ean01 = {
453 .modes = &auo_b101ean01_mode,
454 .num_modes = 1,
455 .bpc = 6,
456 .size = {
457 .width = 217,
458 .height = 136,
459 },
460 };
461
462 static const struct drm_display_mode auo_b101xtn01_mode = {
463 .clock = 72000,
464 .hdisplay = 1366,
465 .hsync_start = 1366 + 20,
466 .hsync_end = 1366 + 20 + 70,
467 .htotal = 1366 + 20 + 70,
468 .vdisplay = 768,
469 .vsync_start = 768 + 14,
470 .vsync_end = 768 + 14 + 42,
471 .vtotal = 768 + 14 + 42,
472 .vrefresh = 60,
473 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
474 };
475
476 static const struct panel_desc auo_b101xtn01 = {
477 .modes = &auo_b101xtn01_mode,
478 .num_modes = 1,
479 .bpc = 6,
480 .size = {
481 .width = 223,
482 .height = 125,
483 },
484 };
485
486 static const struct drm_display_mode auo_b116xw03_mode = {
487 .clock = 70589,
488 .hdisplay = 1366,
489 .hsync_start = 1366 + 40,
490 .hsync_end = 1366 + 40 + 40,
491 .htotal = 1366 + 40 + 40 + 32,
492 .vdisplay = 768,
493 .vsync_start = 768 + 10,
494 .vsync_end = 768 + 10 + 12,
495 .vtotal = 768 + 10 + 12 + 6,
496 .vrefresh = 60,
497 };
498
499 static const struct panel_desc auo_b116xw03 = {
500 .modes = &auo_b116xw03_mode,
501 .num_modes = 1,
502 .bpc = 6,
503 .size = {
504 .width = 256,
505 .height = 144,
506 },
507 };
508
509 static const struct drm_display_mode auo_b133xtn01_mode = {
510 .clock = 69500,
511 .hdisplay = 1366,
512 .hsync_start = 1366 + 48,
513 .hsync_end = 1366 + 48 + 32,
514 .htotal = 1366 + 48 + 32 + 20,
515 .vdisplay = 768,
516 .vsync_start = 768 + 3,
517 .vsync_end = 768 + 3 + 6,
518 .vtotal = 768 + 3 + 6 + 13,
519 .vrefresh = 60,
520 };
521
522 static const struct panel_desc auo_b133xtn01 = {
523 .modes = &auo_b133xtn01_mode,
524 .num_modes = 1,
525 .bpc = 6,
526 .size = {
527 .width = 293,
528 .height = 165,
529 },
530 };
531
532 static const struct drm_display_mode auo_b133htn01_mode = {
533 .clock = 150660,
534 .hdisplay = 1920,
535 .hsync_start = 1920 + 172,
536 .hsync_end = 1920 + 172 + 80,
537 .htotal = 1920 + 172 + 80 + 60,
538 .vdisplay = 1080,
539 .vsync_start = 1080 + 25,
540 .vsync_end = 1080 + 25 + 10,
541 .vtotal = 1080 + 25 + 10 + 10,
542 .vrefresh = 60,
543 };
544
545 static const struct panel_desc auo_b133htn01 = {
546 .modes = &auo_b133htn01_mode,
547 .num_modes = 1,
548 .bpc = 6,
549 .size = {
550 .width = 293,
551 .height = 165,
552 },
553 .delay = {
554 .prepare = 105,
555 .enable = 20,
556 .unprepare = 50,
557 },
558 };
559
560 static const struct drm_display_mode avic_tm070ddh03_mode = {
561 .clock = 51200,
562 .hdisplay = 1024,
563 .hsync_start = 1024 + 160,
564 .hsync_end = 1024 + 160 + 4,
565 .htotal = 1024 + 160 + 4 + 156,
566 .vdisplay = 600,
567 .vsync_start = 600 + 17,
568 .vsync_end = 600 + 17 + 1,
569 .vtotal = 600 + 17 + 1 + 17,
570 .vrefresh = 60,
571 };
572
573 static const struct panel_desc avic_tm070ddh03 = {
574 .modes = &avic_tm070ddh03_mode,
575 .num_modes = 1,
576 .bpc = 8,
577 .size = {
578 .width = 154,
579 .height = 90,
580 },
581 .delay = {
582 .prepare = 20,
583 .enable = 200,
584 .disable = 200,
585 },
586 };
587
588 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
589 .clock = 72070,
590 .hdisplay = 1366,
591 .hsync_start = 1366 + 58,
592 .hsync_end = 1366 + 58 + 58,
593 .htotal = 1366 + 58 + 58 + 58,
594 .vdisplay = 768,
595 .vsync_start = 768 + 4,
596 .vsync_end = 768 + 4 + 4,
597 .vtotal = 768 + 4 + 4 + 4,
598 .vrefresh = 60,
599 };
600
601 static const struct panel_desc chunghwa_claa101wa01a = {
602 .modes = &chunghwa_claa101wa01a_mode,
603 .num_modes = 1,
604 .bpc = 6,
605 .size = {
606 .width = 220,
607 .height = 120,
608 },
609 };
610
611 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
612 .clock = 69300,
613 .hdisplay = 1366,
614 .hsync_start = 1366 + 48,
615 .hsync_end = 1366 + 48 + 32,
616 .htotal = 1366 + 48 + 32 + 20,
617 .vdisplay = 768,
618 .vsync_start = 768 + 16,
619 .vsync_end = 768 + 16 + 8,
620 .vtotal = 768 + 16 + 8 + 16,
621 .vrefresh = 60,
622 };
623
624 static const struct panel_desc chunghwa_claa101wb01 = {
625 .modes = &chunghwa_claa101wb01_mode,
626 .num_modes = 1,
627 .bpc = 6,
628 .size = {
629 .width = 223,
630 .height = 125,
631 },
632 };
633
634 static const struct drm_display_mode edt_et057090dhu_mode = {
635 .clock = 25175,
636 .hdisplay = 640,
637 .hsync_start = 640 + 16,
638 .hsync_end = 640 + 16 + 30,
639 .htotal = 640 + 16 + 30 + 114,
640 .vdisplay = 480,
641 .vsync_start = 480 + 10,
642 .vsync_end = 480 + 10 + 3,
643 .vtotal = 480 + 10 + 3 + 32,
644 .vrefresh = 60,
645 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
646 };
647
648 static const struct panel_desc edt_et057090dhu = {
649 .modes = &edt_et057090dhu_mode,
650 .num_modes = 1,
651 .bpc = 6,
652 .size = {
653 .width = 115,
654 .height = 86,
655 },
656 };
657
658 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
659 .clock = 33260,
660 .hdisplay = 800,
661 .hsync_start = 800 + 40,
662 .hsync_end = 800 + 40 + 128,
663 .htotal = 800 + 40 + 128 + 88,
664 .vdisplay = 480,
665 .vsync_start = 480 + 10,
666 .vsync_end = 480 + 10 + 2,
667 .vtotal = 480 + 10 + 2 + 33,
668 .vrefresh = 60,
669 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
670 };
671
672 static const struct panel_desc edt_etm0700g0dh6 = {
673 .modes = &edt_etm0700g0dh6_mode,
674 .num_modes = 1,
675 .bpc = 6,
676 .size = {
677 .width = 152,
678 .height = 91,
679 },
680 };
681
682 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
683 .clock = 32260,
684 .hdisplay = 800,
685 .hsync_start = 800 + 168,
686 .hsync_end = 800 + 168 + 64,
687 .htotal = 800 + 168 + 64 + 88,
688 .vdisplay = 480,
689 .vsync_start = 480 + 37,
690 .vsync_end = 480 + 37 + 2,
691 .vtotal = 480 + 37 + 2 + 8,
692 .vrefresh = 60,
693 };
694
695 static const struct panel_desc foxlink_fl500wvr00_a0t = {
696 .modes = &foxlink_fl500wvr00_a0t_mode,
697 .num_modes = 1,
698 .bpc = 8,
699 .size = {
700 .width = 108,
701 .height = 65,
702 },
703 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
704 };
705
706 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
707 .clock = 9000,
708 .hdisplay = 480,
709 .hsync_start = 480 + 5,
710 .hsync_end = 480 + 5 + 1,
711 .htotal = 480 + 5 + 1 + 40,
712 .vdisplay = 272,
713 .vsync_start = 272 + 8,
714 .vsync_end = 272 + 8 + 1,
715 .vtotal = 272 + 8 + 1 + 8,
716 .vrefresh = 60,
717 };
718
719 static const struct panel_desc giantplus_gpg482739qs5 = {
720 .modes = &giantplus_gpg482739qs5_mode,
721 .num_modes = 1,
722 .bpc = 8,
723 .size = {
724 .width = 95,
725 .height = 54,
726 },
727 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
728 };
729
730 static const struct display_timing hannstar_hsd070pww1_timing = {
731 .pixelclock = { 64300000, 71100000, 82000000 },
732 .hactive = { 1280, 1280, 1280 },
733 .hfront_porch = { 1, 1, 10 },
734 .hback_porch = { 1, 1, 10 },
735 /*
736 * According to the data sheet, the minimum horizontal blanking interval
737 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
738 * minimum working horizontal blanking interval to be 60 clocks.
739 */
740 .hsync_len = { 58, 158, 661 },
741 .vactive = { 800, 800, 800 },
742 .vfront_porch = { 1, 1, 10 },
743 .vback_porch = { 1, 1, 10 },
744 .vsync_len = { 1, 21, 203 },
745 .flags = DISPLAY_FLAGS_DE_HIGH,
746 };
747
748 static const struct panel_desc hannstar_hsd070pww1 = {
749 .timings = &hannstar_hsd070pww1_timing,
750 .num_timings = 1,
751 .bpc = 6,
752 .size = {
753 .width = 151,
754 .height = 94,
755 },
756 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
757 };
758
759 static const struct display_timing hannstar_hsd100pxn1_timing = {
760 .pixelclock = { 55000000, 65000000, 75000000 },
761 .hactive = { 1024, 1024, 1024 },
762 .hfront_porch = { 40, 40, 40 },
763 .hback_porch = { 220, 220, 220 },
764 .hsync_len = { 20, 60, 100 },
765 .vactive = { 768, 768, 768 },
766 .vfront_porch = { 7, 7, 7 },
767 .vback_porch = { 21, 21, 21 },
768 .vsync_len = { 10, 10, 10 },
769 .flags = DISPLAY_FLAGS_DE_HIGH,
770 };
771
772 static const struct panel_desc hannstar_hsd100pxn1 = {
773 .timings = &hannstar_hsd100pxn1_timing,
774 .num_timings = 1,
775 .bpc = 6,
776 .size = {
777 .width = 203,
778 .height = 152,
779 },
780 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
781 };
782
783 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
784 .clock = 33333,
785 .hdisplay = 800,
786 .hsync_start = 800 + 85,
787 .hsync_end = 800 + 85 + 86,
788 .htotal = 800 + 85 + 86 + 85,
789 .vdisplay = 480,
790 .vsync_start = 480 + 16,
791 .vsync_end = 480 + 16 + 13,
792 .vtotal = 480 + 16 + 13 + 16,
793 .vrefresh = 60,
794 };
795
796 static const struct panel_desc hitachi_tx23d38vm0caa = {
797 .modes = &hitachi_tx23d38vm0caa_mode,
798 .num_modes = 1,
799 .bpc = 6,
800 .size = {
801 .width = 195,
802 .height = 117,
803 },
804 };
805
806 static const struct drm_display_mode innolux_at043tn24_mode = {
807 .clock = 9000,
808 .hdisplay = 480,
809 .hsync_start = 480 + 2,
810 .hsync_end = 480 + 2 + 41,
811 .htotal = 480 + 2 + 41 + 2,
812 .vdisplay = 272,
813 .vsync_start = 272 + 2,
814 .vsync_end = 272 + 2 + 11,
815 .vtotal = 272 + 2 + 11 + 2,
816 .vrefresh = 60,
817 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
818 };
819
820 static const struct panel_desc innolux_at043tn24 = {
821 .modes = &innolux_at043tn24_mode,
822 .num_modes = 1,
823 .bpc = 8,
824 .size = {
825 .width = 95,
826 .height = 54,
827 },
828 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
829 };
830
831 static const struct drm_display_mode innolux_at070tn92_mode = {
832 .clock = 33333,
833 .hdisplay = 800,
834 .hsync_start = 800 + 210,
835 .hsync_end = 800 + 210 + 20,
836 .htotal = 800 + 210 + 20 + 46,
837 .vdisplay = 480,
838 .vsync_start = 480 + 22,
839 .vsync_end = 480 + 22 + 10,
840 .vtotal = 480 + 22 + 23 + 10,
841 .vrefresh = 60,
842 };
843
844 static const struct panel_desc innolux_at070tn92 = {
845 .modes = &innolux_at070tn92_mode,
846 .num_modes = 1,
847 .size = {
848 .width = 154,
849 .height = 86,
850 },
851 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
852 };
853
854 static const struct display_timing innolux_g101ice_l01_timing = {
855 .pixelclock = { 60400000, 71100000, 74700000 },
856 .hactive = { 1280, 1280, 1280 },
857 .hfront_porch = { 41, 80, 100 },
858 .hback_porch = { 40, 79, 99 },
859 .hsync_len = { 1, 1, 1 },
860 .vactive = { 800, 800, 800 },
861 .vfront_porch = { 5, 11, 14 },
862 .vback_porch = { 4, 11, 14 },
863 .vsync_len = { 1, 1, 1 },
864 .flags = DISPLAY_FLAGS_DE_HIGH,
865 };
866
867 static const struct panel_desc innolux_g101ice_l01 = {
868 .timings = &innolux_g101ice_l01_timing,
869 .num_timings = 1,
870 .bpc = 8,
871 .size = {
872 .width = 217,
873 .height = 135,
874 },
875 .delay = {
876 .enable = 200,
877 .disable = 200,
878 },
879 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
880 };
881
882 static const struct drm_display_mode innolux_g121i1_l01_mode = {
883 .clock = 71000,
884 .hdisplay = 1280,
885 .hsync_start = 1280 + 64,
886 .hsync_end = 1280 + 64 + 32,
887 .htotal = 1280 + 64 + 32 + 64,
888 .vdisplay = 800,
889 .vsync_start = 800 + 9,
890 .vsync_end = 800 + 9 + 6,
891 .vtotal = 800 + 9 + 6 + 9,
892 .vrefresh = 60,
893 };
894
895 static const struct panel_desc innolux_g121i1_l01 = {
896 .modes = &innolux_g121i1_l01_mode,
897 .num_modes = 1,
898 .bpc = 6,
899 .size = {
900 .width = 261,
901 .height = 163,
902 },
903 };
904
905 static const struct drm_display_mode innolux_g121x1_l03_mode = {
906 .clock = 65000,
907 .hdisplay = 1024,
908 .hsync_start = 1024 + 0,
909 .hsync_end = 1024 + 1,
910 .htotal = 1024 + 0 + 1 + 320,
911 .vdisplay = 768,
912 .vsync_start = 768 + 38,
913 .vsync_end = 768 + 38 + 1,
914 .vtotal = 768 + 38 + 1 + 0,
915 .vrefresh = 60,
916 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
917 };
918
919 static const struct panel_desc innolux_g121x1_l03 = {
920 .modes = &innolux_g121x1_l03_mode,
921 .num_modes = 1,
922 .bpc = 6,
923 .size = {
924 .width = 246,
925 .height = 185,
926 },
927 .delay = {
928 .enable = 200,
929 .unprepare = 200,
930 .disable = 400,
931 },
932 };
933
934 static const struct drm_display_mode innolux_n116bge_mode = {
935 .clock = 76420,
936 .hdisplay = 1366,
937 .hsync_start = 1366 + 136,
938 .hsync_end = 1366 + 136 + 30,
939 .htotal = 1366 + 136 + 30 + 60,
940 .vdisplay = 768,
941 .vsync_start = 768 + 8,
942 .vsync_end = 768 + 8 + 12,
943 .vtotal = 768 + 8 + 12 + 12,
944 .vrefresh = 60,
945 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
946 };
947
948 static const struct panel_desc innolux_n116bge = {
949 .modes = &innolux_n116bge_mode,
950 .num_modes = 1,
951 .bpc = 6,
952 .size = {
953 .width = 256,
954 .height = 144,
955 },
956 };
957
958 static const struct drm_display_mode innolux_n156bge_l21_mode = {
959 .clock = 69300,
960 .hdisplay = 1366,
961 .hsync_start = 1366 + 16,
962 .hsync_end = 1366 + 16 + 34,
963 .htotal = 1366 + 16 + 34 + 50,
964 .vdisplay = 768,
965 .vsync_start = 768 + 2,
966 .vsync_end = 768 + 2 + 6,
967 .vtotal = 768 + 2 + 6 + 12,
968 .vrefresh = 60,
969 };
970
971 static const struct panel_desc innolux_n156bge_l21 = {
972 .modes = &innolux_n156bge_l21_mode,
973 .num_modes = 1,
974 .bpc = 6,
975 .size = {
976 .width = 344,
977 .height = 193,
978 },
979 };
980
981 static const struct drm_display_mode innolux_zj070na_01p_mode = {
982 .clock = 51501,
983 .hdisplay = 1024,
984 .hsync_start = 1024 + 128,
985 .hsync_end = 1024 + 128 + 64,
986 .htotal = 1024 + 128 + 64 + 128,
987 .vdisplay = 600,
988 .vsync_start = 600 + 16,
989 .vsync_end = 600 + 16 + 4,
990 .vtotal = 600 + 16 + 4 + 16,
991 .vrefresh = 60,
992 };
993
994 static const struct panel_desc innolux_zj070na_01p = {
995 .modes = &innolux_zj070na_01p_mode,
996 .num_modes = 1,
997 .bpc = 6,
998 .size = {
999 .width = 154,
1000 .height = 90,
1001 },
1002 };
1003
1004 static const struct display_timing kyo_tcg121xglp_timing = {
1005 .pixelclock = { 52000000, 65000000, 71000000 },
1006 .hactive = { 1024, 1024, 1024 },
1007 .hfront_porch = { 2, 2, 2 },
1008 .hback_porch = { 2, 2, 2 },
1009 .hsync_len = { 86, 124, 244 },
1010 .vactive = { 768, 768, 768 },
1011 .vfront_porch = { 2, 2, 2 },
1012 .vback_porch = { 2, 2, 2 },
1013 .vsync_len = { 6, 34, 73 },
1014 .flags = DISPLAY_FLAGS_DE_HIGH,
1015 };
1016
1017 static const struct panel_desc kyo_tcg121xglp = {
1018 .timings = &kyo_tcg121xglp_timing,
1019 .num_timings = 1,
1020 .bpc = 8,
1021 .size = {
1022 .width = 246,
1023 .height = 184,
1024 },
1025 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1026 };
1027
1028 static const struct drm_display_mode lg_lb070wv8_mode = {
1029 .clock = 33246,
1030 .hdisplay = 800,
1031 .hsync_start = 800 + 88,
1032 .hsync_end = 800 + 88 + 80,
1033 .htotal = 800 + 88 + 80 + 88,
1034 .vdisplay = 480,
1035 .vsync_start = 480 + 10,
1036 .vsync_end = 480 + 10 + 25,
1037 .vtotal = 480 + 10 + 25 + 10,
1038 .vrefresh = 60,
1039 };
1040
1041 static const struct panel_desc lg_lb070wv8 = {
1042 .modes = &lg_lb070wv8_mode,
1043 .num_modes = 1,
1044 .bpc = 16,
1045 .size = {
1046 .width = 151,
1047 .height = 91,
1048 },
1049 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1050 };
1051
1052 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1053 .clock = 200000,
1054 .hdisplay = 1536,
1055 .hsync_start = 1536 + 12,
1056 .hsync_end = 1536 + 12 + 16,
1057 .htotal = 1536 + 12 + 16 + 48,
1058 .vdisplay = 2048,
1059 .vsync_start = 2048 + 8,
1060 .vsync_end = 2048 + 8 + 4,
1061 .vtotal = 2048 + 8 + 4 + 8,
1062 .vrefresh = 60,
1063 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1064 };
1065
1066 static const struct panel_desc lg_lp079qx1_sp0v = {
1067 .modes = &lg_lp079qx1_sp0v_mode,
1068 .num_modes = 1,
1069 .size = {
1070 .width = 129,
1071 .height = 171,
1072 },
1073 };
1074
1075 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1076 .clock = 205210,
1077 .hdisplay = 2048,
1078 .hsync_start = 2048 + 150,
1079 .hsync_end = 2048 + 150 + 5,
1080 .htotal = 2048 + 150 + 5 + 5,
1081 .vdisplay = 1536,
1082 .vsync_start = 1536 + 3,
1083 .vsync_end = 1536 + 3 + 1,
1084 .vtotal = 1536 + 3 + 1 + 9,
1085 .vrefresh = 60,
1086 };
1087
1088 static const struct panel_desc lg_lp097qx1_spa1 = {
1089 .modes = &lg_lp097qx1_spa1_mode,
1090 .num_modes = 1,
1091 .size = {
1092 .width = 208,
1093 .height = 147,
1094 },
1095 };
1096
1097 static const struct drm_display_mode lg_lp120up1_mode = {
1098 .clock = 162300,
1099 .hdisplay = 1920,
1100 .hsync_start = 1920 + 40,
1101 .hsync_end = 1920 + 40 + 40,
1102 .htotal = 1920 + 40 + 40+ 80,
1103 .vdisplay = 1280,
1104 .vsync_start = 1280 + 4,
1105 .vsync_end = 1280 + 4 + 4,
1106 .vtotal = 1280 + 4 + 4 + 12,
1107 .vrefresh = 60,
1108 };
1109
1110 static const struct panel_desc lg_lp120up1 = {
1111 .modes = &lg_lp120up1_mode,
1112 .num_modes = 1,
1113 .bpc = 8,
1114 .size = {
1115 .width = 267,
1116 .height = 183,
1117 },
1118 };
1119
1120 static const struct drm_display_mode lg_lp129qe_mode = {
1121 .clock = 285250,
1122 .hdisplay = 2560,
1123 .hsync_start = 2560 + 48,
1124 .hsync_end = 2560 + 48 + 32,
1125 .htotal = 2560 + 48 + 32 + 80,
1126 .vdisplay = 1700,
1127 .vsync_start = 1700 + 3,
1128 .vsync_end = 1700 + 3 + 10,
1129 .vtotal = 1700 + 3 + 10 + 36,
1130 .vrefresh = 60,
1131 };
1132
1133 static const struct panel_desc lg_lp129qe = {
1134 .modes = &lg_lp129qe_mode,
1135 .num_modes = 1,
1136 .bpc = 8,
1137 .size = {
1138 .width = 272,
1139 .height = 181,
1140 },
1141 };
1142
1143 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1144 .clock = 10870,
1145 .hdisplay = 480,
1146 .hsync_start = 480 + 2,
1147 .hsync_end = 480 + 2 + 41,
1148 .htotal = 480 + 2 + 41 + 2,
1149 .vdisplay = 272,
1150 .vsync_start = 272 + 2,
1151 .vsync_end = 272 + 2 + 4,
1152 .vtotal = 272 + 2 + 4 + 2,
1153 .vrefresh = 74,
1154 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1155 };
1156
1157 static const struct panel_desc nec_nl4827hc19_05b = {
1158 .modes = &nec_nl4827hc19_05b_mode,
1159 .num_modes = 1,
1160 .bpc = 8,
1161 .size = {
1162 .width = 95,
1163 .height = 54,
1164 },
1165 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1166 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1167 };
1168
1169 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1170 .pixelclock = { 30000000, 30000000, 40000000 },
1171 .hactive = { 800, 800, 800 },
1172 .hfront_porch = { 40, 40, 40 },
1173 .hback_porch = { 40, 40, 40 },
1174 .hsync_len = { 1, 48, 48 },
1175 .vactive = { 480, 480, 480 },
1176 .vfront_porch = { 13, 13, 13 },
1177 .vback_porch = { 29, 29, 29 },
1178 .vsync_len = { 3, 3, 3 },
1179 .flags = DISPLAY_FLAGS_DE_HIGH,
1180 };
1181
1182 static const struct panel_desc okaya_rs800480t_7x0gp = {
1183 .timings = &okaya_rs800480t_7x0gp_timing,
1184 .num_timings = 1,
1185 .bpc = 6,
1186 .size = {
1187 .width = 154,
1188 .height = 87,
1189 },
1190 .delay = {
1191 .prepare = 41,
1192 .enable = 50,
1193 .unprepare = 41,
1194 .disable = 50,
1195 },
1196 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1197 };
1198
1199 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1200 .clock = 9000,
1201 .hdisplay = 480,
1202 .hsync_start = 480 + 5,
1203 .hsync_end = 480 + 5 + 30,
1204 .htotal = 480 + 5 + 30 + 10,
1205 .vdisplay = 272,
1206 .vsync_start = 272 + 8,
1207 .vsync_end = 272 + 8 + 5,
1208 .vtotal = 272 + 8 + 5 + 3,
1209 .vrefresh = 60,
1210 };
1211
1212 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1213 .modes = &olimex_lcd_olinuxino_43ts_mode,
1214 .num_modes = 1,
1215 .size = {
1216 .width = 105,
1217 .height = 67,
1218 },
1219 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1220 };
1221
1222 /*
1223 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1224 * pixel clocks, but this is the timing that was being used in the Adafruit
1225 * installation instructions.
1226 */
1227 static const struct drm_display_mode ontat_yx700wv03_mode = {
1228 .clock = 29500,
1229 .hdisplay = 800,
1230 .hsync_start = 824,
1231 .hsync_end = 896,
1232 .htotal = 992,
1233 .vdisplay = 480,
1234 .vsync_start = 483,
1235 .vsync_end = 493,
1236 .vtotal = 500,
1237 .vrefresh = 60,
1238 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1239 };
1240
1241 /*
1242 * Specification at:
1243 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1244 */
1245 static const struct panel_desc ontat_yx700wv03 = {
1246 .modes = &ontat_yx700wv03_mode,
1247 .num_modes = 1,
1248 .bpc = 8,
1249 .size = {
1250 .width = 154,
1251 .height = 83,
1252 },
1253 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1254 };
1255
1256 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1257 .clock = 25000,
1258 .hdisplay = 480,
1259 .hsync_start = 480 + 10,
1260 .hsync_end = 480 + 10 + 10,
1261 .htotal = 480 + 10 + 10 + 15,
1262 .vdisplay = 800,
1263 .vsync_start = 800 + 3,
1264 .vsync_end = 800 + 3 + 3,
1265 .vtotal = 800 + 3 + 3 + 3,
1266 .vrefresh = 60,
1267 };
1268
1269 static const struct panel_desc ortustech_com43h4m85ulc = {
1270 .modes = &ortustech_com43h4m85ulc_mode,
1271 .num_modes = 1,
1272 .bpc = 8,
1273 .size = {
1274 .width = 56,
1275 .height = 93,
1276 },
1277 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1278 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1279 };
1280
1281 static const struct drm_display_mode qd43003c0_40_mode = {
1282 .clock = 9000,
1283 .hdisplay = 480,
1284 .hsync_start = 480 + 8,
1285 .hsync_end = 480 + 8 + 4,
1286 .htotal = 480 + 8 + 4 + 39,
1287 .vdisplay = 272,
1288 .vsync_start = 272 + 4,
1289 .vsync_end = 272 + 4 + 10,
1290 .vtotal = 272 + 4 + 10 + 2,
1291 .vrefresh = 60,
1292 };
1293
1294 static const struct panel_desc qd43003c0_40 = {
1295 .modes = &qd43003c0_40_mode,
1296 .num_modes = 1,
1297 .bpc = 8,
1298 .size = {
1299 .width = 95,
1300 .height = 53,
1301 },
1302 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1303 };
1304
1305 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1306 .clock = 271560,
1307 .hdisplay = 2560,
1308 .hsync_start = 2560 + 48,
1309 .hsync_end = 2560 + 48 + 32,
1310 .htotal = 2560 + 48 + 32 + 80,
1311 .vdisplay = 1600,
1312 .vsync_start = 1600 + 2,
1313 .vsync_end = 1600 + 2 + 5,
1314 .vtotal = 1600 + 2 + 5 + 57,
1315 .vrefresh = 60,
1316 };
1317
1318 static const struct panel_desc samsung_lsn122dl01_c01 = {
1319 .modes = &samsung_lsn122dl01_c01_mode,
1320 .num_modes = 1,
1321 .size = {
1322 .width = 263,
1323 .height = 164,
1324 },
1325 };
1326
1327 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1328 .clock = 54030,
1329 .hdisplay = 1024,
1330 .hsync_start = 1024 + 24,
1331 .hsync_end = 1024 + 24 + 136,
1332 .htotal = 1024 + 24 + 136 + 160,
1333 .vdisplay = 600,
1334 .vsync_start = 600 + 3,
1335 .vsync_end = 600 + 3 + 6,
1336 .vtotal = 600 + 3 + 6 + 61,
1337 .vrefresh = 60,
1338 };
1339
1340 static const struct panel_desc samsung_ltn101nt05 = {
1341 .modes = &samsung_ltn101nt05_mode,
1342 .num_modes = 1,
1343 .bpc = 6,
1344 .size = {
1345 .width = 223,
1346 .height = 125,
1347 },
1348 };
1349
1350 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1351 .clock = 76300,
1352 .hdisplay = 1366,
1353 .hsync_start = 1366 + 64,
1354 .hsync_end = 1366 + 64 + 48,
1355 .htotal = 1366 + 64 + 48 + 128,
1356 .vdisplay = 768,
1357 .vsync_start = 768 + 2,
1358 .vsync_end = 768 + 2 + 5,
1359 .vtotal = 768 + 2 + 5 + 17,
1360 .vrefresh = 60,
1361 };
1362
1363 static const struct panel_desc samsung_ltn140at29_301 = {
1364 .modes = &samsung_ltn140at29_301_mode,
1365 .num_modes = 1,
1366 .bpc = 6,
1367 .size = {
1368 .width = 320,
1369 .height = 187,
1370 },
1371 };
1372
1373 static const struct display_timing sharp_lq101k1ly04_timing = {
1374 .pixelclock = { 60000000, 65000000, 80000000 },
1375 .hactive = { 1280, 1280, 1280 },
1376 .hfront_porch = { 20, 20, 20 },
1377 .hback_porch = { 20, 20, 20 },
1378 .hsync_len = { 10, 10, 10 },
1379 .vactive = { 800, 800, 800 },
1380 .vfront_porch = { 4, 4, 4 },
1381 .vback_porch = { 4, 4, 4 },
1382 .vsync_len = { 4, 4, 4 },
1383 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
1384 };
1385
1386 static const struct panel_desc sharp_lq101k1ly04 = {
1387 .timings = &sharp_lq101k1ly04_timing,
1388 .num_timings = 1,
1389 .bpc = 8,
1390 .size = {
1391 .width = 217,
1392 .height = 136,
1393 },
1394 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1395 };
1396
1397 static const struct drm_display_mode sharp_lq123p1jx31_mode = {
1398 .clock = 252750,
1399 .hdisplay = 2400,
1400 .hsync_start = 2400 + 48,
1401 .hsync_end = 2400 + 48 + 32,
1402 .htotal = 2400 + 48 + 32 + 80,
1403 .vdisplay = 1600,
1404 .vsync_start = 1600 + 3,
1405 .vsync_end = 1600 + 3 + 10,
1406 .vtotal = 1600 + 3 + 10 + 33,
1407 .vrefresh = 60,
1408 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1409 };
1410
1411 static const struct panel_desc sharp_lq123p1jx31 = {
1412 .modes = &sharp_lq123p1jx31_mode,
1413 .num_modes = 1,
1414 .size = {
1415 .width = 259,
1416 .height = 173,
1417 },
1418 .delay = {
1419 .prepare = 110,
1420 .enable = 50,
1421 .unprepare = 550,
1422 },
1423 };
1424
1425 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1426 .clock = 33300,
1427 .hdisplay = 800,
1428 .hsync_start = 800 + 1,
1429 .hsync_end = 800 + 1 + 64,
1430 .htotal = 800 + 1 + 64 + 64,
1431 .vdisplay = 480,
1432 .vsync_start = 480 + 1,
1433 .vsync_end = 480 + 1 + 23,
1434 .vtotal = 480 + 1 + 23 + 22,
1435 .vrefresh = 60,
1436 };
1437
1438 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1439 .modes = &shelly_sca07010_bfn_lnn_mode,
1440 .num_modes = 1,
1441 .size = {
1442 .width = 152,
1443 .height = 91,
1444 },
1445 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1446 };
1447
1448 static const struct drm_display_mode starry_kr122ea0sra_mode = {
1449 .clock = 147000,
1450 .hdisplay = 1920,
1451 .hsync_start = 1920 + 16,
1452 .hsync_end = 1920 + 16 + 16,
1453 .htotal = 1920 + 16 + 16 + 32,
1454 .vdisplay = 1200,
1455 .vsync_start = 1200 + 15,
1456 .vsync_end = 1200 + 15 + 2,
1457 .vtotal = 1200 + 15 + 2 + 18,
1458 .vrefresh = 60,
1459 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1460 };
1461
1462 static const struct panel_desc starry_kr122ea0sra = {
1463 .modes = &starry_kr122ea0sra_mode,
1464 .num_modes = 1,
1465 .size = {
1466 .width = 263,
1467 .height = 164,
1468 },
1469 .delay = {
1470 .prepare = 10 + 200,
1471 .enable = 50,
1472 .unprepare = 10 + 500,
1473 },
1474 };
1475
1476 static const struct drm_display_mode tpk_f07a_0102_mode = {
1477 .clock = 33260,
1478 .hdisplay = 800,
1479 .hsync_start = 800 + 40,
1480 .hsync_end = 800 + 40 + 128,
1481 .htotal = 800 + 40 + 128 + 88,
1482 .vdisplay = 480,
1483 .vsync_start = 480 + 10,
1484 .vsync_end = 480 + 10 + 2,
1485 .vtotal = 480 + 10 + 2 + 33,
1486 .vrefresh = 60,
1487 };
1488
1489 static const struct panel_desc tpk_f07a_0102 = {
1490 .modes = &tpk_f07a_0102_mode,
1491 .num_modes = 1,
1492 .size = {
1493 .width = 152,
1494 .height = 91,
1495 },
1496 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1497 };
1498
1499 static const struct drm_display_mode tpk_f10a_0102_mode = {
1500 .clock = 45000,
1501 .hdisplay = 1024,
1502 .hsync_start = 1024 + 176,
1503 .hsync_end = 1024 + 176 + 5,
1504 .htotal = 1024 + 176 + 5 + 88,
1505 .vdisplay = 600,
1506 .vsync_start = 600 + 20,
1507 .vsync_end = 600 + 20 + 5,
1508 .vtotal = 600 + 20 + 5 + 25,
1509 .vrefresh = 60,
1510 };
1511
1512 static const struct panel_desc tpk_f10a_0102 = {
1513 .modes = &tpk_f10a_0102_mode,
1514 .num_modes = 1,
1515 .size = {
1516 .width = 223,
1517 .height = 125,
1518 },
1519 };
1520
1521 static const struct display_timing urt_umsh_8596md_timing = {
1522 .pixelclock = { 33260000, 33260000, 33260000 },
1523 .hactive = { 800, 800, 800 },
1524 .hfront_porch = { 41, 41, 41 },
1525 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
1526 .hsync_len = { 71, 128, 128 },
1527 .vactive = { 480, 480, 480 },
1528 .vfront_porch = { 10, 10, 10 },
1529 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
1530 .vsync_len = { 2, 2, 2 },
1531 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1532 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1533 };
1534
1535 static const struct panel_desc urt_umsh_8596md_lvds = {
1536 .timings = &urt_umsh_8596md_timing,
1537 .num_timings = 1,
1538 .bpc = 6,
1539 .size = {
1540 .width = 152,
1541 .height = 91,
1542 },
1543 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1544 };
1545
1546 static const struct panel_desc urt_umsh_8596md_parallel = {
1547 .timings = &urt_umsh_8596md_timing,
1548 .num_timings = 1,
1549 .bpc = 6,
1550 .size = {
1551 .width = 152,
1552 .height = 91,
1553 },
1554 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1555 };
1556
1557 static const struct of_device_id platform_of_match[] = {
1558 {
1559 .compatible = "ampire,am800480r3tmqwa1h",
1560 .data = &ire_am800480r3tmqwa1h,
1561 }, {
1562 .compatible = "auo,b101aw03",
1563 .data = &auo_b101aw03,
1564 }, {
1565 .compatible = "auo,b101ean01",
1566 .data = &auo_b101ean01,
1567 }, {
1568 .compatible = "auo,b101xtn01",
1569 .data = &auo_b101xtn01,
1570 }, {
1571 .compatible = "auo,b116xw03",
1572 .data = &auo_b116xw03,
1573 }, {
1574 .compatible = "auo,b133htn01",
1575 .data = &auo_b133htn01,
1576 }, {
1577 .compatible = "auo,b133xtn01",
1578 .data = &auo_b133xtn01,
1579 }, {
1580 .compatible = "avic,tm070ddh03",
1581 .data = &avic_tm070ddh03,
1582 }, {
1583 .compatible = "chunghwa,claa101wa01a",
1584 .data = &chunghwa_claa101wa01a
1585 }, {
1586 .compatible = "chunghwa,claa101wb01",
1587 .data = &chunghwa_claa101wb01
1588 }, {
1589 .compatible = "edt,et057090dhu",
1590 .data = &edt_et057090dhu,
1591 }, {
1592 .compatible = "edt,et070080dh6",
1593 .data = &edt_etm0700g0dh6,
1594 }, {
1595 .compatible = "edt,etm0700g0dh6",
1596 .data = &edt_etm0700g0dh6,
1597 }, {
1598 .compatible = "foxlink,fl500wvr00-a0t",
1599 .data = &foxlink_fl500wvr00_a0t,
1600 }, {
1601 .compatible = "giantplus,gpg482739qs5",
1602 .data = &giantplus_gpg482739qs5
1603 }, {
1604 .compatible = "hannstar,hsd070pww1",
1605 .data = &hannstar_hsd070pww1,
1606 }, {
1607 .compatible = "hannstar,hsd100pxn1",
1608 .data = &hannstar_hsd100pxn1,
1609 }, {
1610 .compatible = "hit,tx23d38vm0caa",
1611 .data = &hitachi_tx23d38vm0caa
1612 }, {
1613 .compatible = "innolux,at043tn24",
1614 .data = &innolux_at043tn24,
1615 }, {
1616 .compatible = "innolux,at070tn92",
1617 .data = &innolux_at070tn92,
1618 }, {
1619 .compatible ="innolux,g101ice-l01",
1620 .data = &innolux_g101ice_l01
1621 }, {
1622 .compatible ="innolux,g121i1-l01",
1623 .data = &innolux_g121i1_l01
1624 }, {
1625 .compatible = "innolux,g121x1-l03",
1626 .data = &innolux_g121x1_l03,
1627 }, {
1628 .compatible = "innolux,n116bge",
1629 .data = &innolux_n116bge,
1630 }, {
1631 .compatible = "innolux,n156bge-l21",
1632 .data = &innolux_n156bge_l21,
1633 }, {
1634 .compatible = "innolux,zj070na-01p",
1635 .data = &innolux_zj070na_01p,
1636 }, {
1637 .compatible = "kyo,tcg121xglp",
1638 .data = &kyo_tcg121xglp,
1639 }, {
1640 .compatible = "lg,lb070wv8",
1641 .data = &lg_lb070wv8,
1642 }, {
1643 .compatible = "lg,lp079qx1-sp0v",
1644 .data = &lg_lp079qx1_sp0v,
1645 }, {
1646 .compatible = "lg,lp097qx1-spa1",
1647 .data = &lg_lp097qx1_spa1,
1648 }, {
1649 .compatible = "lg,lp120up1",
1650 .data = &lg_lp120up1,
1651 }, {
1652 .compatible = "lg,lp129qe",
1653 .data = &lg_lp129qe,
1654 }, {
1655 .compatible = "nec,nl4827hc19-05b",
1656 .data = &nec_nl4827hc19_05b,
1657 }, {
1658 .compatible = "okaya,rs800480t-7x0gp",
1659 .data = &okaya_rs800480t_7x0gp,
1660 }, {
1661 .compatible = "olimex,lcd-olinuxino-43-ts",
1662 .data = &olimex_lcd_olinuxino_43ts,
1663 }, {
1664 .compatible = "ontat,yx700wv03",
1665 .data = &ontat_yx700wv03,
1666 }, {
1667 .compatible = "ortustech,com43h4m85ulc",
1668 .data = &ortustech_com43h4m85ulc,
1669 }, {
1670 .compatible = "qiaodian,qd43003c0-40",
1671 .data = &qd43003c0_40,
1672 }, {
1673 .compatible = "samsung,lsn122dl01-c01",
1674 .data = &samsung_lsn122dl01_c01,
1675 }, {
1676 .compatible = "samsung,ltn101nt05",
1677 .data = &samsung_ltn101nt05,
1678 }, {
1679 .compatible = "samsung,ltn140at29-301",
1680 .data = &samsung_ltn140at29_301,
1681 }, {
1682 .compatible = "sharp,lq101k1ly04",
1683 .data = &sharp_lq101k1ly04,
1684 }, {
1685 .compatible = "sharp,lq123p1jx31",
1686 .data = &sharp_lq123p1jx31,
1687 }, {
1688 .compatible = "shelly,sca07010-bfn-lnn",
1689 .data = &shelly_sca07010_bfn_lnn,
1690 }, {
1691 .compatible = "starry,kr122ea0sra",
1692 .data = &starry_kr122ea0sra,
1693 }, {
1694 .compatible = "tpk,f07a-0102",
1695 .data = &tpk_f07a_0102,
1696 }, {
1697 .compatible = "tpk,f10a-0102",
1698 .data = &tpk_f10a_0102,
1699 }, {
1700 .compatible = "urt,umsh-8596md-t",
1701 .data = &urt_umsh_8596md_parallel,
1702 }, {
1703 .compatible = "urt,umsh-8596md-1t",
1704 .data = &urt_umsh_8596md_parallel,
1705 }, {
1706 .compatible = "urt,umsh-8596md-7t",
1707 .data = &urt_umsh_8596md_parallel,
1708 }, {
1709 .compatible = "urt,umsh-8596md-11t",
1710 .data = &urt_umsh_8596md_lvds,
1711 }, {
1712 .compatible = "urt,umsh-8596md-19t",
1713 .data = &urt_umsh_8596md_lvds,
1714 }, {
1715 .compatible = "urt,umsh-8596md-20t",
1716 .data = &urt_umsh_8596md_parallel,
1717 }, {
1718 /* sentinel */
1719 }
1720 };
1721 MODULE_DEVICE_TABLE(of, platform_of_match);
1722
panel_simple_platform_probe(struct platform_device * pdev)1723 static int panel_simple_platform_probe(struct platform_device *pdev)
1724 {
1725 const struct of_device_id *id;
1726
1727 id = of_match_node(platform_of_match, pdev->dev.of_node);
1728 if (!id)
1729 return -ENODEV;
1730
1731 return panel_simple_probe(&pdev->dev, id->data);
1732 }
1733
panel_simple_platform_remove(struct platform_device * pdev)1734 static int panel_simple_platform_remove(struct platform_device *pdev)
1735 {
1736 return panel_simple_remove(&pdev->dev);
1737 }
1738
panel_simple_platform_shutdown(struct platform_device * pdev)1739 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1740 {
1741 panel_simple_shutdown(&pdev->dev);
1742 }
1743
1744 static struct platform_driver panel_simple_platform_driver = {
1745 .driver = {
1746 .name = "panel-simple",
1747 .of_match_table = platform_of_match,
1748 },
1749 .probe = panel_simple_platform_probe,
1750 .remove = panel_simple_platform_remove,
1751 .shutdown = panel_simple_platform_shutdown,
1752 };
1753
1754 struct panel_desc_dsi {
1755 struct panel_desc desc;
1756
1757 unsigned long flags;
1758 enum mipi_dsi_pixel_format format;
1759 unsigned int lanes;
1760 };
1761
1762 static const struct drm_display_mode auo_b080uan01_mode = {
1763 .clock = 154500,
1764 .hdisplay = 1200,
1765 .hsync_start = 1200 + 62,
1766 .hsync_end = 1200 + 62 + 4,
1767 .htotal = 1200 + 62 + 4 + 62,
1768 .vdisplay = 1920,
1769 .vsync_start = 1920 + 9,
1770 .vsync_end = 1920 + 9 + 2,
1771 .vtotal = 1920 + 9 + 2 + 8,
1772 .vrefresh = 60,
1773 };
1774
1775 static const struct panel_desc_dsi auo_b080uan01 = {
1776 .desc = {
1777 .modes = &auo_b080uan01_mode,
1778 .num_modes = 1,
1779 .bpc = 8,
1780 .size = {
1781 .width = 108,
1782 .height = 272,
1783 },
1784 },
1785 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1786 .format = MIPI_DSI_FMT_RGB888,
1787 .lanes = 4,
1788 };
1789
1790 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1791 .clock = 160000,
1792 .hdisplay = 1200,
1793 .hsync_start = 1200 + 120,
1794 .hsync_end = 1200 + 120 + 20,
1795 .htotal = 1200 + 120 + 20 + 21,
1796 .vdisplay = 1920,
1797 .vsync_start = 1920 + 21,
1798 .vsync_end = 1920 + 21 + 3,
1799 .vtotal = 1920 + 21 + 3 + 18,
1800 .vrefresh = 60,
1801 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1802 };
1803
1804 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1805 .desc = {
1806 .modes = &boe_tv080wum_nl0_mode,
1807 .num_modes = 1,
1808 .size = {
1809 .width = 107,
1810 .height = 172,
1811 },
1812 },
1813 .flags = MIPI_DSI_MODE_VIDEO |
1814 MIPI_DSI_MODE_VIDEO_BURST |
1815 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1816 .format = MIPI_DSI_FMT_RGB888,
1817 .lanes = 4,
1818 };
1819
1820 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1821 .clock = 71000,
1822 .hdisplay = 800,
1823 .hsync_start = 800 + 32,
1824 .hsync_end = 800 + 32 + 1,
1825 .htotal = 800 + 32 + 1 + 57,
1826 .vdisplay = 1280,
1827 .vsync_start = 1280 + 28,
1828 .vsync_end = 1280 + 28 + 1,
1829 .vtotal = 1280 + 28 + 1 + 14,
1830 .vrefresh = 60,
1831 };
1832
1833 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1834 .desc = {
1835 .modes = &lg_ld070wx3_sl01_mode,
1836 .num_modes = 1,
1837 .bpc = 8,
1838 .size = {
1839 .width = 94,
1840 .height = 151,
1841 },
1842 },
1843 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1844 .format = MIPI_DSI_FMT_RGB888,
1845 .lanes = 4,
1846 };
1847
1848 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1849 .clock = 67000,
1850 .hdisplay = 720,
1851 .hsync_start = 720 + 12,
1852 .hsync_end = 720 + 12 + 4,
1853 .htotal = 720 + 12 + 4 + 112,
1854 .vdisplay = 1280,
1855 .vsync_start = 1280 + 8,
1856 .vsync_end = 1280 + 8 + 4,
1857 .vtotal = 1280 + 8 + 4 + 12,
1858 .vrefresh = 60,
1859 };
1860
1861 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1862 .desc = {
1863 .modes = &lg_lh500wx1_sd03_mode,
1864 .num_modes = 1,
1865 .bpc = 8,
1866 .size = {
1867 .width = 62,
1868 .height = 110,
1869 },
1870 },
1871 .flags = MIPI_DSI_MODE_VIDEO,
1872 .format = MIPI_DSI_FMT_RGB888,
1873 .lanes = 4,
1874 };
1875
1876 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1877 .clock = 157200,
1878 .hdisplay = 1920,
1879 .hsync_start = 1920 + 154,
1880 .hsync_end = 1920 + 154 + 16,
1881 .htotal = 1920 + 154 + 16 + 32,
1882 .vdisplay = 1200,
1883 .vsync_start = 1200 + 17,
1884 .vsync_end = 1200 + 17 + 2,
1885 .vtotal = 1200 + 17 + 2 + 16,
1886 .vrefresh = 60,
1887 };
1888
1889 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1890 .desc = {
1891 .modes = &panasonic_vvx10f004b00_mode,
1892 .num_modes = 1,
1893 .bpc = 8,
1894 .size = {
1895 .width = 217,
1896 .height = 136,
1897 },
1898 },
1899 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1900 MIPI_DSI_CLOCK_NON_CONTINUOUS,
1901 .format = MIPI_DSI_FMT_RGB888,
1902 .lanes = 4,
1903 };
1904
1905 static const struct of_device_id dsi_of_match[] = {
1906 {
1907 .compatible = "auo,b080uan01",
1908 .data = &auo_b080uan01
1909 }, {
1910 .compatible = "boe,tv080wum-nl0",
1911 .data = &boe_tv080wum_nl0
1912 }, {
1913 .compatible = "lg,ld070wx3-sl01",
1914 .data = &lg_ld070wx3_sl01
1915 }, {
1916 .compatible = "lg,lh500wx1-sd03",
1917 .data = &lg_lh500wx1_sd03
1918 }, {
1919 .compatible = "panasonic,vvx10f004b00",
1920 .data = &panasonic_vvx10f004b00
1921 }, {
1922 /* sentinel */
1923 }
1924 };
1925 MODULE_DEVICE_TABLE(of, dsi_of_match);
1926
panel_simple_dsi_probe(struct mipi_dsi_device * dsi)1927 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1928 {
1929 const struct panel_desc_dsi *desc;
1930 const struct of_device_id *id;
1931 int err;
1932
1933 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1934 if (!id)
1935 return -ENODEV;
1936
1937 desc = id->data;
1938
1939 err = panel_simple_probe(&dsi->dev, &desc->desc);
1940 if (err < 0)
1941 return err;
1942
1943 dsi->mode_flags = desc->flags;
1944 dsi->format = desc->format;
1945 dsi->lanes = desc->lanes;
1946
1947 return mipi_dsi_attach(dsi);
1948 }
1949
panel_simple_dsi_remove(struct mipi_dsi_device * dsi)1950 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1951 {
1952 int err;
1953
1954 err = mipi_dsi_detach(dsi);
1955 if (err < 0)
1956 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1957
1958 return panel_simple_remove(&dsi->dev);
1959 }
1960
panel_simple_dsi_shutdown(struct mipi_dsi_device * dsi)1961 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1962 {
1963 panel_simple_shutdown(&dsi->dev);
1964 }
1965
1966 static struct mipi_dsi_driver panel_simple_dsi_driver = {
1967 .driver = {
1968 .name = "panel-simple-dsi",
1969 .of_match_table = dsi_of_match,
1970 },
1971 .probe = panel_simple_dsi_probe,
1972 .remove = panel_simple_dsi_remove,
1973 .shutdown = panel_simple_dsi_shutdown,
1974 };
1975
panel_simple_init(void)1976 static int __init panel_simple_init(void)
1977 {
1978 int err;
1979
1980 err = platform_driver_register(&panel_simple_platform_driver);
1981 if (err < 0)
1982 return err;
1983
1984 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1985 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1986 if (err < 0)
1987 return err;
1988 }
1989
1990 return 0;
1991 }
1992 module_init(panel_simple_init);
1993
panel_simple_exit(void)1994 static void __exit panel_simple_exit(void)
1995 {
1996 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1997 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1998
1999 platform_driver_unregister(&panel_simple_platform_driver);
2000 }
2001 module_exit(panel_simple_exit);
2002
2003 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2004 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2005 MODULE_LICENSE("GPL and additional rights");
2006