1 /*
2 * VFIO PCI config space virtualization
3 *
4 * Copyright (C) 2012 Red Hat, Inc. All rights reserved.
5 * Author: Alex Williamson <alex.williamson@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Derived from original vfio:
12 * Copyright 2010 Cisco Systems, Inc. All rights reserved.
13 * Author: Tom Lyon, pugs@cisco.com
14 */
15
16 /*
17 * This code handles reading and writing of PCI configuration registers.
18 * This is hairy because we want to allow a lot of flexibility to the
19 * user driver, but cannot trust it with all of the config fields.
20 * Tables determine which fields can be read and written, as well as
21 * which fields are 'virtualized' - special actions and translations to
22 * make it appear to the user that he has control, when in fact things
23 * must be negotiated with the underlying OS.
24 */
25
26 #include <linux/fs.h>
27 #include <linux/pci.h>
28 #include <linux/uaccess.h>
29 #include <linux/vfio.h>
30 #include <linux/slab.h>
31
32 #include "vfio_pci_private.h"
33
34 #define PCI_CFG_SPACE_SIZE 256
35
36 /* Fake capability ID for standard config space */
37 #define PCI_CAP_ID_BASIC 0
38
39 #define is_bar(offset) \
40 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
41 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
42
43 /*
44 * Lengths of PCI Config Capabilities
45 * 0: Removed from the user visible capability list
46 * FF: Variable length
47 */
48 static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = {
49 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */
50 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF,
51 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF,
52 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF,
53 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */
54 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */
55 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */
56 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */
57 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */
58 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */
59 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */
60 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */
61 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */
62 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */
63 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */
64 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */
65 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */
66 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF,
67 [PCI_CAP_ID_SATA] = 0xFF,
68 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF,
69 };
70
71 /*
72 * Lengths of PCIe/PCI-X Extended Config Capabilities
73 * 0: Removed or masked from the user visible capability list
74 * FF: Variable length
75 */
76 static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = {
77 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND,
78 [PCI_EXT_CAP_ID_VC] = 0xFF,
79 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF,
80 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF,
81 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */
82 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */
83 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */
84 [PCI_EXT_CAP_ID_MFVC] = 0xFF,
85 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */
86 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */
87 [PCI_EXT_CAP_ID_VNDR] = 0xFF,
88 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */
89 [PCI_EXT_CAP_ID_ACS] = 0xFF,
90 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF,
91 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF,
92 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF,
93 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */
94 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF,
95 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF,
96 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */
97 [PCI_EXT_CAP_ID_REBAR] = 0xFF,
98 [PCI_EXT_CAP_ID_DPA] = 0xFF,
99 [PCI_EXT_CAP_ID_TPH] = 0xFF,
100 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF,
101 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */
102 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */
103 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */
104 };
105
106 /*
107 * Read/Write Permission Bits - one bit for each bit in capability
108 * Any field can be read if it exists, but what is read depends on
109 * whether the field is 'virtualized', or just pass thru to the
110 * hardware. Any virtualized field is also virtualized for writes.
111 * Writes are only permitted if they have a 1 bit here.
112 */
113 struct perm_bits {
114 u8 *virt; /* read/write virtual data, not hw */
115 u8 *write; /* writeable bits */
116 int (*readfn)(struct vfio_pci_device *vdev, int pos, int count,
117 struct perm_bits *perm, int offset, __le32 *val);
118 int (*writefn)(struct vfio_pci_device *vdev, int pos, int count,
119 struct perm_bits *perm, int offset, __le32 val);
120 };
121
122 #define NO_VIRT 0
123 #define ALL_VIRT 0xFFFFFFFFU
124 #define NO_WRITE 0
125 #define ALL_WRITE 0xFFFFFFFFU
126
vfio_user_config_read(struct pci_dev * pdev,int offset,__le32 * val,int count)127 static int vfio_user_config_read(struct pci_dev *pdev, int offset,
128 __le32 *val, int count)
129 {
130 int ret = -EINVAL;
131 u32 tmp_val = 0;
132
133 switch (count) {
134 case 1:
135 {
136 u8 tmp;
137 ret = pci_user_read_config_byte(pdev, offset, &tmp);
138 tmp_val = tmp;
139 break;
140 }
141 case 2:
142 {
143 u16 tmp;
144 ret = pci_user_read_config_word(pdev, offset, &tmp);
145 tmp_val = tmp;
146 break;
147 }
148 case 4:
149 ret = pci_user_read_config_dword(pdev, offset, &tmp_val);
150 break;
151 }
152
153 *val = cpu_to_le32(tmp_val);
154
155 return pcibios_err_to_errno(ret);
156 }
157
vfio_user_config_write(struct pci_dev * pdev,int offset,__le32 val,int count)158 static int vfio_user_config_write(struct pci_dev *pdev, int offset,
159 __le32 val, int count)
160 {
161 int ret = -EINVAL;
162 u32 tmp_val = le32_to_cpu(val);
163
164 switch (count) {
165 case 1:
166 ret = pci_user_write_config_byte(pdev, offset, tmp_val);
167 break;
168 case 2:
169 ret = pci_user_write_config_word(pdev, offset, tmp_val);
170 break;
171 case 4:
172 ret = pci_user_write_config_dword(pdev, offset, tmp_val);
173 break;
174 }
175
176 return pcibios_err_to_errno(ret);
177 }
178
vfio_default_config_read(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 * val)179 static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos,
180 int count, struct perm_bits *perm,
181 int offset, __le32 *val)
182 {
183 __le32 virt = 0;
184
185 memcpy(val, vdev->vconfig + pos, count);
186
187 memcpy(&virt, perm->virt + offset, count);
188
189 /* Any non-virtualized bits? */
190 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) {
191 struct pci_dev *pdev = vdev->pdev;
192 __le32 phys_val = 0;
193 int ret;
194
195 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
196 if (ret)
197 return ret;
198
199 *val = (phys_val & ~virt) | (*val & virt);
200 }
201
202 return count;
203 }
204
vfio_default_config_write(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 val)205 static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos,
206 int count, struct perm_bits *perm,
207 int offset, __le32 val)
208 {
209 __le32 virt = 0, write = 0;
210
211 memcpy(&write, perm->write + offset, count);
212
213 if (!write)
214 return count; /* drop, no writable bits */
215
216 memcpy(&virt, perm->virt + offset, count);
217
218 /* Virtualized and writable bits go to vconfig */
219 if (write & virt) {
220 __le32 virt_val = 0;
221
222 memcpy(&virt_val, vdev->vconfig + pos, count);
223
224 virt_val &= ~(write & virt);
225 virt_val |= (val & (write & virt));
226
227 memcpy(vdev->vconfig + pos, &virt_val, count);
228 }
229
230 /* Non-virtualzed and writable bits go to hardware */
231 if (write & ~virt) {
232 struct pci_dev *pdev = vdev->pdev;
233 __le32 phys_val = 0;
234 int ret;
235
236 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
237 if (ret)
238 return ret;
239
240 phys_val &= ~(write & ~virt);
241 phys_val |= (val & (write & ~virt));
242
243 ret = vfio_user_config_write(pdev, pos, phys_val, count);
244 if (ret)
245 return ret;
246 }
247
248 return count;
249 }
250
251 /* Allow direct read from hardware, except for capability next pointer */
vfio_direct_config_read(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 * val)252 static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos,
253 int count, struct perm_bits *perm,
254 int offset, __le32 *val)
255 {
256 int ret;
257
258 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
259 if (ret)
260 return pcibios_err_to_errno(ret);
261
262 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */
263 if (offset < 4)
264 memcpy(val, vdev->vconfig + pos, count);
265 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */
266 if (offset == PCI_CAP_LIST_ID && count > 1)
267 memcpy(val, vdev->vconfig + pos,
268 min(PCI_CAP_FLAGS, count));
269 else if (offset == PCI_CAP_LIST_NEXT)
270 memcpy(val, vdev->vconfig + pos, 1);
271 }
272
273 return count;
274 }
275
276 /* Raw access skips any kind of virtualization */
vfio_raw_config_write(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 val)277 static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos,
278 int count, struct perm_bits *perm,
279 int offset, __le32 val)
280 {
281 int ret;
282
283 ret = vfio_user_config_write(vdev->pdev, pos, val, count);
284 if (ret)
285 return ret;
286
287 return count;
288 }
289
vfio_raw_config_read(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 * val)290 static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos,
291 int count, struct perm_bits *perm,
292 int offset, __le32 *val)
293 {
294 int ret;
295
296 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
297 if (ret)
298 return pcibios_err_to_errno(ret);
299
300 return count;
301 }
302
303 /* Virt access uses only virtualization */
vfio_virt_config_write(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 val)304 static int vfio_virt_config_write(struct vfio_pci_device *vdev, int pos,
305 int count, struct perm_bits *perm,
306 int offset, __le32 val)
307 {
308 memcpy(vdev->vconfig + pos, &val, count);
309 return count;
310 }
311
vfio_virt_config_read(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 * val)312 static int vfio_virt_config_read(struct vfio_pci_device *vdev, int pos,
313 int count, struct perm_bits *perm,
314 int offset, __le32 *val)
315 {
316 memcpy(val, vdev->vconfig + pos, count);
317 return count;
318 }
319
320 /* Default capability regions to read-only, no-virtualization */
321 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = {
322 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
323 };
324 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = {
325 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
326 };
327 /*
328 * Default unassigned regions to raw read-write access. Some devices
329 * require this to function as they hide registers between the gaps in
330 * config space (be2net). Like MMIO and I/O port registers, we have
331 * to trust the hardware isolation.
332 */
333 static struct perm_bits unassigned_perms = {
334 .readfn = vfio_raw_config_read,
335 .writefn = vfio_raw_config_write
336 };
337
338 static struct perm_bits virt_perms = {
339 .readfn = vfio_virt_config_read,
340 .writefn = vfio_virt_config_write
341 };
342
free_perm_bits(struct perm_bits * perm)343 static void free_perm_bits(struct perm_bits *perm)
344 {
345 kfree(perm->virt);
346 kfree(perm->write);
347 perm->virt = NULL;
348 perm->write = NULL;
349 }
350
alloc_perm_bits(struct perm_bits * perm,int size)351 static int alloc_perm_bits(struct perm_bits *perm, int size)
352 {
353 /*
354 * Round up all permission bits to the next dword, this lets us
355 * ignore whether a read/write exceeds the defined capability
356 * structure. We can do this because:
357 * - Standard config space is already dword aligned
358 * - Capabilities are all dword aligned (bits 0:1 of next reserved)
359 * - Express capabilities defined as dword aligned
360 */
361 size = round_up(size, 4);
362
363 /*
364 * Zero state is
365 * - All Readable, None Writeable, None Virtualized
366 */
367 perm->virt = kzalloc(size, GFP_KERNEL);
368 perm->write = kzalloc(size, GFP_KERNEL);
369 if (!perm->virt || !perm->write) {
370 free_perm_bits(perm);
371 return -ENOMEM;
372 }
373
374 perm->readfn = vfio_default_config_read;
375 perm->writefn = vfio_default_config_write;
376
377 return 0;
378 }
379
380 /*
381 * Helper functions for filling in permission tables
382 */
p_setb(struct perm_bits * p,int off,u8 virt,u8 write)383 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write)
384 {
385 p->virt[off] = virt;
386 p->write[off] = write;
387 }
388
389 /* Handle endian-ness - pci and tables are little-endian */
p_setw(struct perm_bits * p,int off,u16 virt,u16 write)390 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write)
391 {
392 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt);
393 *(__le16 *)(&p->write[off]) = cpu_to_le16(write);
394 }
395
396 /* Handle endian-ness - pci and tables are little-endian */
p_setd(struct perm_bits * p,int off,u32 virt,u32 write)397 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write)
398 {
399 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt);
400 *(__le32 *)(&p->write[off]) = cpu_to_le32(write);
401 }
402
403 /*
404 * Restore the *real* BARs after we detect a FLR or backdoor reset.
405 * (backdoor = some device specific technique that we didn't catch)
406 */
vfio_bar_restore(struct vfio_pci_device * vdev)407 static void vfio_bar_restore(struct vfio_pci_device *vdev)
408 {
409 struct pci_dev *pdev = vdev->pdev;
410 u32 *rbar = vdev->rbar;
411 u16 cmd;
412 int i;
413
414 if (pdev->is_virtfn)
415 return;
416
417 pr_info("%s: %s reset recovery - restoring bars\n",
418 __func__, dev_name(&pdev->dev));
419
420 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)
421 pci_user_write_config_dword(pdev, i, *rbar);
422
423 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
424
425 if (vdev->nointx) {
426 pci_user_read_config_word(pdev, PCI_COMMAND, &cmd);
427 cmd |= PCI_COMMAND_INTX_DISABLE;
428 pci_user_write_config_word(pdev, PCI_COMMAND, cmd);
429 }
430 }
431
vfio_generate_bar_flags(struct pci_dev * pdev,int bar)432 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)
433 {
434 unsigned long flags = pci_resource_flags(pdev, bar);
435 u32 val;
436
437 if (flags & IORESOURCE_IO)
438 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO);
439
440 val = PCI_BASE_ADDRESS_SPACE_MEMORY;
441
442 if (flags & IORESOURCE_PREFETCH)
443 val |= PCI_BASE_ADDRESS_MEM_PREFETCH;
444
445 if (flags & IORESOURCE_MEM_64)
446 val |= PCI_BASE_ADDRESS_MEM_TYPE_64;
447
448 return cpu_to_le32(val);
449 }
450
451 /*
452 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs
453 * to reflect the hardware capabilities. This implements BAR sizing.
454 */
vfio_bar_fixup(struct vfio_pci_device * vdev)455 static void vfio_bar_fixup(struct vfio_pci_device *vdev)
456 {
457 struct pci_dev *pdev = vdev->pdev;
458 int i;
459 __le32 *bar;
460 u64 mask;
461
462 bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
463
464 for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) {
465 if (!pci_resource_start(pdev, i)) {
466 *bar = 0; /* Unmapped by host = unimplemented to user */
467 continue;
468 }
469
470 mask = ~(pci_resource_len(pdev, i) - 1);
471
472 *bar &= cpu_to_le32((u32)mask);
473 *bar |= vfio_generate_bar_flags(pdev, i);
474
475 if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) {
476 bar++;
477 *bar &= cpu_to_le32((u32)(mask >> 32));
478 i++;
479 }
480 }
481
482 bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];
483
484 /*
485 * NB. REGION_INFO will have reported zero size if we weren't able
486 * to read the ROM, but we still return the actual BAR size here if
487 * it exists (or the shadow ROM space).
488 */
489 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) {
490 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1);
491 mask |= PCI_ROM_ADDRESS_ENABLE;
492 *bar &= cpu_to_le32((u32)mask);
493 } else if (pdev->resource[PCI_ROM_RESOURCE].flags &
494 IORESOURCE_ROM_SHADOW) {
495 mask = ~(0x20000 - 1);
496 mask |= PCI_ROM_ADDRESS_ENABLE;
497 *bar &= cpu_to_le32((u32)mask);
498 } else
499 *bar = 0;
500
501 vdev->bardirty = false;
502 }
503
vfio_basic_config_read(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 * val)504 static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos,
505 int count, struct perm_bits *perm,
506 int offset, __le32 *val)
507 {
508 if (is_bar(offset)) /* pos == offset for basic config */
509 vfio_bar_fixup(vdev);
510
511 count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
512
513 /* Mask in virtual memory enable for SR-IOV devices */
514 if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) {
515 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
516 u32 tmp_val = le32_to_cpu(*val);
517
518 tmp_val |= cmd & PCI_COMMAND_MEMORY;
519 *val = cpu_to_le32(tmp_val);
520 }
521
522 return count;
523 }
524
525 /* Test whether BARs match the value we think they should contain */
vfio_need_bar_restore(struct vfio_pci_device * vdev)526 static bool vfio_need_bar_restore(struct vfio_pci_device *vdev)
527 {
528 int i = 0, pos = PCI_BASE_ADDRESS_0, ret;
529 u32 bar;
530
531 for (; pos <= PCI_BASE_ADDRESS_5; i++, pos += 4) {
532 if (vdev->rbar[i]) {
533 ret = pci_user_read_config_dword(vdev->pdev, pos, &bar);
534 if (ret || vdev->rbar[i] != bar)
535 return true;
536 }
537 }
538
539 return false;
540 }
541
vfio_basic_config_write(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 val)542 static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos,
543 int count, struct perm_bits *perm,
544 int offset, __le32 val)
545 {
546 struct pci_dev *pdev = vdev->pdev;
547 __le16 *virt_cmd;
548 u16 new_cmd = 0;
549 int ret;
550
551 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND];
552
553 if (offset == PCI_COMMAND) {
554 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io;
555 u16 phys_cmd;
556
557 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd);
558 if (ret)
559 return ret;
560
561 new_cmd = le32_to_cpu(val);
562
563 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY);
564 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY);
565 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY);
566
567 phys_io = !!(phys_cmd & PCI_COMMAND_IO);
568 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO);
569 new_io = !!(new_cmd & PCI_COMMAND_IO);
570
571 /*
572 * If the user is writing mem/io enable (new_mem/io) and we
573 * think it's already enabled (virt_mem/io), but the hardware
574 * shows it disabled (phys_mem/io, then the device has
575 * undergone some kind of backdoor reset and needs to be
576 * restored before we allow it to enable the bars.
577 * SR-IOV devices will trigger this, but we catch them later
578 */
579 if ((new_mem && virt_mem && !phys_mem) ||
580 (new_io && virt_io && !phys_io) ||
581 vfio_need_bar_restore(vdev))
582 vfio_bar_restore(vdev);
583 }
584
585 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
586 if (count < 0)
587 return count;
588
589 /*
590 * Save current memory/io enable bits in vconfig to allow for
591 * the test above next time.
592 */
593 if (offset == PCI_COMMAND) {
594 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
595
596 *virt_cmd &= cpu_to_le16(~mask);
597 *virt_cmd |= cpu_to_le16(new_cmd & mask);
598 }
599
600 /* Emulate INTx disable */
601 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) {
602 bool virt_intx_disable;
603
604 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) &
605 PCI_COMMAND_INTX_DISABLE);
606
607 if (virt_intx_disable && !vdev->virq_disabled) {
608 vdev->virq_disabled = true;
609 vfio_pci_intx_mask(vdev);
610 } else if (!virt_intx_disable && vdev->virq_disabled) {
611 vdev->virq_disabled = false;
612 vfio_pci_intx_unmask(vdev);
613 }
614 }
615
616 if (is_bar(offset))
617 vdev->bardirty = true;
618
619 return count;
620 }
621
622 /* Permissions for the Basic PCI Header */
init_pci_cap_basic_perm(struct perm_bits * perm)623 static int __init init_pci_cap_basic_perm(struct perm_bits *perm)
624 {
625 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))
626 return -ENOMEM;
627
628 perm->readfn = vfio_basic_config_read;
629 perm->writefn = vfio_basic_config_write;
630
631 /* Virtualized for SR-IOV functions, which just have FFFF */
632 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);
633 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);
634
635 /*
636 * Virtualize INTx disable, we use it internally for interrupt
637 * control and can emulate it for non-PCI 2.3 devices.
638 */
639 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);
640
641 /* Virtualize capability list, we might want to skip/disable */
642 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);
643
644 /* No harm to write */
645 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
646 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
647 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);
648
649 /* Virtualize all bars, can't touch the real ones */
650 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
651 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);
652 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
653 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);
654 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);
655 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);
656 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
657
658 /* Allow us to adjust capability chain */
659 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);
660
661 /* Sometimes used by sw, just virtualize */
662 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
663
664 /* Virtualize interrupt pin to allow hiding INTx */
665 p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE);
666
667 return 0;
668 }
669
vfio_pm_config_write(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 val)670 static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos,
671 int count, struct perm_bits *perm,
672 int offset, __le32 val)
673 {
674 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
675 if (count < 0)
676 return count;
677
678 if (offset == PCI_PM_CTRL) {
679 pci_power_t state;
680
681 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) {
682 case 0:
683 state = PCI_D0;
684 break;
685 case 1:
686 state = PCI_D1;
687 break;
688 case 2:
689 state = PCI_D2;
690 break;
691 case 3:
692 state = PCI_D3hot;
693 break;
694 }
695
696 pci_set_power_state(vdev->pdev, state);
697 }
698
699 return count;
700 }
701
702 /* Permissions for the Power Management capability */
init_pci_cap_pm_perm(struct perm_bits * perm)703 static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
704 {
705 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))
706 return -ENOMEM;
707
708 perm->writefn = vfio_pm_config_write;
709
710 /*
711 * We always virtualize the next field so we can remove
712 * capabilities from the chain if we want to.
713 */
714 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
715
716 /*
717 * Power management is defined *per function*, so we can let
718 * the user change power state, but we trap and initiate the
719 * change ourselves, so the state bits are read-only.
720 */
721 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK);
722 return 0;
723 }
724
vfio_vpd_config_write(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 val)725 static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos,
726 int count, struct perm_bits *perm,
727 int offset, __le32 val)
728 {
729 struct pci_dev *pdev = vdev->pdev;
730 __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR);
731 __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA);
732 u16 addr;
733 u32 data;
734
735 /*
736 * Write through to emulation. If the write includes the upper byte
737 * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we
738 * have work to do.
739 */
740 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
741 if (count < 0 || offset > PCI_VPD_ADDR + 1 ||
742 offset + count <= PCI_VPD_ADDR + 1)
743 return count;
744
745 addr = le16_to_cpu(*paddr);
746
747 if (addr & PCI_VPD_ADDR_F) {
748 data = le32_to_cpu(*pdata);
749 if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4)
750 return count;
751 } else {
752 data = 0;
753 if (pci_read_vpd(pdev, addr, 4, &data) < 0)
754 return count;
755 *pdata = cpu_to_le32(data);
756 }
757
758 /*
759 * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to
760 * signal completion. If an error occurs above, we assume that not
761 * toggling this bit will induce a driver timeout.
762 */
763 addr ^= PCI_VPD_ADDR_F;
764 *paddr = cpu_to_le16(addr);
765
766 return count;
767 }
768
769 /* Permissions for Vital Product Data capability */
init_pci_cap_vpd_perm(struct perm_bits * perm)770 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
771 {
772 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
773 return -ENOMEM;
774
775 perm->writefn = vfio_vpd_config_write;
776
777 /*
778 * We always virtualize the next field so we can remove
779 * capabilities from the chain if we want to.
780 */
781 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
782
783 /*
784 * Both the address and data registers are virtualized to
785 * enable access through the pci_vpd_read/write functions
786 */
787 p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
788 p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
789
790 return 0;
791 }
792
793 /* Permissions for PCI-X capability */
init_pci_cap_pcix_perm(struct perm_bits * perm)794 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
795 {
796 /* Alloc 24, but only 8 are used in v0 */
797 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))
798 return -ENOMEM;
799
800 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
801
802 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);
803 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);
804 return 0;
805 }
806
vfio_exp_config_write(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 val)807 static int vfio_exp_config_write(struct vfio_pci_device *vdev, int pos,
808 int count, struct perm_bits *perm,
809 int offset, __le32 val)
810 {
811 __le16 *ctrl = (__le16 *)(vdev->vconfig + pos -
812 offset + PCI_EXP_DEVCTL);
813 int readrq = le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ;
814
815 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
816 if (count < 0)
817 return count;
818
819 /*
820 * The FLR bit is virtualized, if set and the device supports PCIe
821 * FLR, issue a reset_function. Regardless, clear the bit, the spec
822 * requires it to be always read as zero. NB, reset_function might
823 * not use a PCIe FLR, we don't have that level of granularity.
824 */
825 if (*ctrl & cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR)) {
826 u32 cap;
827 int ret;
828
829 *ctrl &= ~cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR);
830
831 ret = pci_user_read_config_dword(vdev->pdev,
832 pos - offset + PCI_EXP_DEVCAP,
833 &cap);
834
835 if (!ret && (cap & PCI_EXP_DEVCAP_FLR))
836 pci_try_reset_function(vdev->pdev);
837 }
838
839 /*
840 * MPS is virtualized to the user, writes do not change the physical
841 * register since determining a proper MPS value requires a system wide
842 * device view. The MRRS is largely independent of MPS, but since the
843 * user does not have that system-wide view, they might set a safe, but
844 * inefficiently low value. Here we allow writes through to hardware,
845 * but we set the floor to the physical device MPS setting, so that
846 * we can at least use full TLPs, as defined by the MPS value.
847 *
848 * NB, if any devices actually depend on an artificially low MRRS
849 * setting, this will need to be revisited, perhaps with a quirk
850 * though pcie_set_readrq().
851 */
852 if (readrq != (le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ)) {
853 readrq = 128 <<
854 ((le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ) >> 12);
855 readrq = max(readrq, pcie_get_mps(vdev->pdev));
856
857 pcie_set_readrq(vdev->pdev, readrq);
858 }
859
860 return count;
861 }
862
863 /* Permissions for PCI Express capability */
init_pci_cap_exp_perm(struct perm_bits * perm)864 static int __init init_pci_cap_exp_perm(struct perm_bits *perm)
865 {
866 /* Alloc larger of two possible sizes */
867 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))
868 return -ENOMEM;
869
870 perm->writefn = vfio_exp_config_write;
871
872 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
873
874 /*
875 * Allow writes to device control fields, except devctl_phantom,
876 * which could confuse IOMMU, MPS, which can break communication
877 * with other physical devices, and the ARI bit in devctl2, which
878 * is set at probe time. FLR and MRRS get virtualized via our
879 * writefn.
880 */
881 p_setw(perm, PCI_EXP_DEVCTL,
882 PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_PAYLOAD |
883 PCI_EXP_DEVCTL_READRQ, ~PCI_EXP_DEVCTL_PHANTOM);
884 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
885 return 0;
886 }
887
vfio_af_config_write(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 val)888 static int vfio_af_config_write(struct vfio_pci_device *vdev, int pos,
889 int count, struct perm_bits *perm,
890 int offset, __le32 val)
891 {
892 u8 *ctrl = vdev->vconfig + pos - offset + PCI_AF_CTRL;
893
894 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
895 if (count < 0)
896 return count;
897
898 /*
899 * The FLR bit is virtualized, if set and the device supports AF
900 * FLR, issue a reset_function. Regardless, clear the bit, the spec
901 * requires it to be always read as zero. NB, reset_function might
902 * not use an AF FLR, we don't have that level of granularity.
903 */
904 if (*ctrl & PCI_AF_CTRL_FLR) {
905 u8 cap;
906 int ret;
907
908 *ctrl &= ~PCI_AF_CTRL_FLR;
909
910 ret = pci_user_read_config_byte(vdev->pdev,
911 pos - offset + PCI_AF_CAP,
912 &cap);
913
914 if (!ret && (cap & PCI_AF_CAP_FLR) && (cap & PCI_AF_CAP_TP))
915 pci_try_reset_function(vdev->pdev);
916 }
917
918 return count;
919 }
920
921 /* Permissions for Advanced Function capability */
init_pci_cap_af_perm(struct perm_bits * perm)922 static int __init init_pci_cap_af_perm(struct perm_bits *perm)
923 {
924 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))
925 return -ENOMEM;
926
927 perm->writefn = vfio_af_config_write;
928
929 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
930 p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR);
931 return 0;
932 }
933
934 /* Permissions for Advanced Error Reporting extended capability */
init_pci_ext_cap_err_perm(struct perm_bits * perm)935 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
936 {
937 u32 mask;
938
939 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))
940 return -ENOMEM;
941
942 /*
943 * Virtualize the first dword of all express capabilities
944 * because it includes the next pointer. This lets us later
945 * remove capabilities from the chain if we need to.
946 */
947 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
948
949 /* Writable bits mask */
950 mask = PCI_ERR_UNC_UND | /* Undefined */
951 PCI_ERR_UNC_DLP | /* Data Link Protocol */
952 PCI_ERR_UNC_SURPDN | /* Surprise Down */
953 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */
954 PCI_ERR_UNC_FCP | /* Flow Control Protocol */
955 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */
956 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */
957 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */
958 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */
959 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */
960 PCI_ERR_UNC_ECRC | /* ECRC Error Status */
961 PCI_ERR_UNC_UNSUP | /* Unsupported Request */
962 PCI_ERR_UNC_ACSV | /* ACS Violation */
963 PCI_ERR_UNC_INTN | /* internal error */
964 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */
965 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */
966 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */
967 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);
968 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);
969 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);
970
971 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */
972 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */
973 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */
974 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */
975 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */
976 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */
977 PCI_ERR_COR_INTERNAL | /* Corrected Internal */
978 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */
979 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);
980 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);
981
982 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */
983 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */
984 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);
985 return 0;
986 }
987
988 /* Permissions for Power Budgeting extended capability */
init_pci_ext_cap_pwr_perm(struct perm_bits * perm)989 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)
990 {
991 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))
992 return -ENOMEM;
993
994 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
995
996 /* Writing the data selector is OK, the info is still read-only */
997 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);
998 return 0;
999 }
1000
1001 /*
1002 * Initialize the shared permission tables
1003 */
vfio_pci_uninit_perm_bits(void)1004 void vfio_pci_uninit_perm_bits(void)
1005 {
1006 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]);
1007
1008 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]);
1009 free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]);
1010 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]);
1011 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]);
1012 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]);
1013
1014 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
1015 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
1016 }
1017
vfio_pci_init_perm_bits(void)1018 int __init vfio_pci_init_perm_bits(void)
1019 {
1020 int ret;
1021
1022 /* Basic config space */
1023 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]);
1024
1025 /* Capabilities */
1026 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]);
1027 ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]);
1028 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]);
1029 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write;
1030 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]);
1031 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]);
1032
1033 /* Extended capabilities */
1034 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
1035 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
1036 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write;
1037
1038 if (ret)
1039 vfio_pci_uninit_perm_bits();
1040
1041 return ret;
1042 }
1043
vfio_find_cap_start(struct vfio_pci_device * vdev,int pos)1044 static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos)
1045 {
1046 u8 cap;
1047 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE :
1048 PCI_STD_HEADER_SIZEOF;
1049 cap = vdev->pci_config_map[pos];
1050
1051 if (cap == PCI_CAP_ID_BASIC)
1052 return 0;
1053
1054 /* XXX Can we have to abutting capabilities of the same type? */
1055 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap)
1056 pos--;
1057
1058 return pos;
1059 }
1060
vfio_msi_config_read(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 * val)1061 static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos,
1062 int count, struct perm_bits *perm,
1063 int offset, __le32 *val)
1064 {
1065 /* Update max available queue size from msi_qmax */
1066 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1067 __le16 *flags;
1068 int start;
1069
1070 start = vfio_find_cap_start(vdev, pos);
1071
1072 flags = (__le16 *)&vdev->vconfig[start];
1073
1074 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK);
1075 *flags |= cpu_to_le16(vdev->msi_qmax << 1);
1076 }
1077
1078 return vfio_default_config_read(vdev, pos, count, perm, offset, val);
1079 }
1080
vfio_msi_config_write(struct vfio_pci_device * vdev,int pos,int count,struct perm_bits * perm,int offset,__le32 val)1081 static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos,
1082 int count, struct perm_bits *perm,
1083 int offset, __le32 val)
1084 {
1085 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
1086 if (count < 0)
1087 return count;
1088
1089 /* Fixup and write configured queue size and enable to hardware */
1090 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1091 __le16 *pflags;
1092 u16 flags;
1093 int start, ret;
1094
1095 start = vfio_find_cap_start(vdev, pos);
1096
1097 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS];
1098
1099 flags = le16_to_cpu(*pflags);
1100
1101 /* MSI is enabled via ioctl */
1102 if (!is_msi(vdev))
1103 flags &= ~PCI_MSI_FLAGS_ENABLE;
1104
1105 /* Check queue size */
1106 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) {
1107 flags &= ~PCI_MSI_FLAGS_QSIZE;
1108 flags |= vdev->msi_qmax << 4;
1109 }
1110
1111 /* Write back to virt and to hardware */
1112 *pflags = cpu_to_le16(flags);
1113 ret = pci_user_write_config_word(vdev->pdev,
1114 start + PCI_MSI_FLAGS,
1115 flags);
1116 if (ret)
1117 return pcibios_err_to_errno(ret);
1118 }
1119
1120 return count;
1121 }
1122
1123 /*
1124 * MSI determination is per-device, so this routine gets used beyond
1125 * initialization time. Don't add __init
1126 */
init_pci_cap_msi_perm(struct perm_bits * perm,int len,u16 flags)1127 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)
1128 {
1129 if (alloc_perm_bits(perm, len))
1130 return -ENOMEM;
1131
1132 perm->readfn = vfio_msi_config_read;
1133 perm->writefn = vfio_msi_config_write;
1134
1135 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
1136
1137 /*
1138 * The upper byte of the control register is reserved,
1139 * just setup the lower byte.
1140 */
1141 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);
1142 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);
1143 if (flags & PCI_MSI_FLAGS_64BIT) {
1144 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);
1145 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);
1146 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1147 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);
1148 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);
1149 }
1150 } else {
1151 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);
1152 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1153 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);
1154 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);
1155 }
1156 }
1157 return 0;
1158 }
1159
1160 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
vfio_msi_cap_len(struct vfio_pci_device * vdev,u8 pos)1161 static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos)
1162 {
1163 struct pci_dev *pdev = vdev->pdev;
1164 int len, ret;
1165 u16 flags;
1166
1167 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags);
1168 if (ret)
1169 return pcibios_err_to_errno(ret);
1170
1171 len = 10; /* Minimum size */
1172 if (flags & PCI_MSI_FLAGS_64BIT)
1173 len += 4;
1174 if (flags & PCI_MSI_FLAGS_MASKBIT)
1175 len += 10;
1176
1177 if (vdev->msi_perm)
1178 return len;
1179
1180 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL);
1181 if (!vdev->msi_perm)
1182 return -ENOMEM;
1183
1184 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);
1185 if (ret)
1186 return ret;
1187
1188 return len;
1189 }
1190
1191 /* Determine extended capability length for VC (2 & 9) and MFVC */
vfio_vc_cap_len(struct vfio_pci_device * vdev,u16 pos)1192 static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos)
1193 {
1194 struct pci_dev *pdev = vdev->pdev;
1195 u32 tmp;
1196 int ret, evcc, phases, vc_arb;
1197 int len = PCI_CAP_VC_BASE_SIZEOF;
1198
1199 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp);
1200 if (ret)
1201 return pcibios_err_to_errno(ret);
1202
1203 evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */
1204 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp);
1205 if (ret)
1206 return pcibios_err_to_errno(ret);
1207
1208 if (tmp & PCI_VC_CAP2_128_PHASE)
1209 phases = 128;
1210 else if (tmp & PCI_VC_CAP2_64_PHASE)
1211 phases = 64;
1212 else if (tmp & PCI_VC_CAP2_32_PHASE)
1213 phases = 32;
1214 else
1215 phases = 0;
1216
1217 vc_arb = phases * 4;
1218
1219 /*
1220 * Port arbitration tables are root & switch only;
1221 * function arbitration tables are function 0 only.
1222 * In either case, we'll never let user write them so
1223 * we don't care how big they are
1224 */
1225 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF;
1226 if (vc_arb) {
1227 len = round_up(len, 16);
1228 len += vc_arb / 8;
1229 }
1230 return len;
1231 }
1232
vfio_cap_len(struct vfio_pci_device * vdev,u8 cap,u8 pos)1233 static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos)
1234 {
1235 struct pci_dev *pdev = vdev->pdev;
1236 u32 dword;
1237 u16 word;
1238 u8 byte;
1239 int ret;
1240
1241 switch (cap) {
1242 case PCI_CAP_ID_MSI:
1243 return vfio_msi_cap_len(vdev, pos);
1244 case PCI_CAP_ID_PCIX:
1245 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word);
1246 if (ret)
1247 return pcibios_err_to_errno(ret);
1248
1249 if (PCI_X_CMD_VERSION(word)) {
1250 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
1251 /* Test for extended capabilities */
1252 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE,
1253 &dword);
1254 vdev->extended_caps = (dword != 0);
1255 }
1256 return PCI_CAP_PCIX_SIZEOF_V2;
1257 } else
1258 return PCI_CAP_PCIX_SIZEOF_V0;
1259 case PCI_CAP_ID_VNDR:
1260 /* length follows next field */
1261 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte);
1262 if (ret)
1263 return pcibios_err_to_errno(ret);
1264
1265 return byte;
1266 case PCI_CAP_ID_EXP:
1267 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
1268 /* Test for extended capabilities */
1269 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
1270 vdev->extended_caps = (dword != 0);
1271 }
1272
1273 /* length based on version */
1274 if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1)
1275 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1;
1276 else
1277 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2;
1278 case PCI_CAP_ID_HT:
1279 ret = pci_read_config_byte(pdev, pos + 3, &byte);
1280 if (ret)
1281 return pcibios_err_to_errno(ret);
1282
1283 return (byte & HT_3BIT_CAP_MASK) ?
1284 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG;
1285 case PCI_CAP_ID_SATA:
1286 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte);
1287 if (ret)
1288 return pcibios_err_to_errno(ret);
1289
1290 byte &= PCI_SATA_REGS_MASK;
1291 if (byte == PCI_SATA_REGS_INLINE)
1292 return PCI_SATA_SIZEOF_LONG;
1293 else
1294 return PCI_SATA_SIZEOF_SHORT;
1295 default:
1296 pr_warn("%s: %s unknown length for pci cap 0x%x@0x%x\n",
1297 dev_name(&pdev->dev), __func__, cap, pos);
1298 }
1299
1300 return 0;
1301 }
1302
vfio_ext_cap_len(struct vfio_pci_device * vdev,u16 ecap,u16 epos)1303 static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos)
1304 {
1305 struct pci_dev *pdev = vdev->pdev;
1306 u8 byte;
1307 u32 dword;
1308 int ret;
1309
1310 switch (ecap) {
1311 case PCI_EXT_CAP_ID_VNDR:
1312 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword);
1313 if (ret)
1314 return pcibios_err_to_errno(ret);
1315
1316 return dword >> PCI_VSEC_HDR_LEN_SHIFT;
1317 case PCI_EXT_CAP_ID_VC:
1318 case PCI_EXT_CAP_ID_VC9:
1319 case PCI_EXT_CAP_ID_MFVC:
1320 return vfio_vc_cap_len(vdev, epos);
1321 case PCI_EXT_CAP_ID_ACS:
1322 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte);
1323 if (ret)
1324 return pcibios_err_to_errno(ret);
1325
1326 if (byte & PCI_ACS_EC) {
1327 int bits;
1328
1329 ret = pci_read_config_byte(pdev,
1330 epos + PCI_ACS_EGRESS_BITS,
1331 &byte);
1332 if (ret)
1333 return pcibios_err_to_errno(ret);
1334
1335 bits = byte ? round_up(byte, 32) : 256;
1336 return 8 + (bits / 8);
1337 }
1338 return 8;
1339
1340 case PCI_EXT_CAP_ID_REBAR:
1341 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte);
1342 if (ret)
1343 return pcibios_err_to_errno(ret);
1344
1345 byte &= PCI_REBAR_CTRL_NBAR_MASK;
1346 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT;
1347
1348 return 4 + (byte * 8);
1349 case PCI_EXT_CAP_ID_DPA:
1350 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte);
1351 if (ret)
1352 return pcibios_err_to_errno(ret);
1353
1354 byte &= PCI_DPA_CAP_SUBSTATE_MASK;
1355 return PCI_DPA_BASE_SIZEOF + byte + 1;
1356 case PCI_EXT_CAP_ID_TPH:
1357 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword);
1358 if (ret)
1359 return pcibios_err_to_errno(ret);
1360
1361 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) {
1362 int sts;
1363
1364 sts = dword & PCI_TPH_CAP_ST_MASK;
1365 sts >>= PCI_TPH_CAP_ST_SHIFT;
1366 return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2;
1367 }
1368 return PCI_TPH_BASE_SIZEOF;
1369 default:
1370 pr_warn("%s: %s unknown length for pci ecap 0x%x@0x%x\n",
1371 dev_name(&pdev->dev), __func__, ecap, epos);
1372 }
1373
1374 return 0;
1375 }
1376
vfio_fill_vconfig_bytes(struct vfio_pci_device * vdev,int offset,int size)1377 static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev,
1378 int offset, int size)
1379 {
1380 struct pci_dev *pdev = vdev->pdev;
1381 int ret = 0;
1382
1383 /*
1384 * We try to read physical config space in the largest chunks
1385 * we can, assuming that all of the fields support dword access.
1386 * pci_save_state() makes this same assumption and seems to do ok.
1387 */
1388 while (size) {
1389 int filled;
1390
1391 if (size >= 4 && !(offset % 4)) {
1392 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset];
1393 u32 dword;
1394
1395 ret = pci_read_config_dword(pdev, offset, &dword);
1396 if (ret)
1397 return ret;
1398 *dwordp = cpu_to_le32(dword);
1399 filled = 4;
1400 } else if (size >= 2 && !(offset % 2)) {
1401 __le16 *wordp = (__le16 *)&vdev->vconfig[offset];
1402 u16 word;
1403
1404 ret = pci_read_config_word(pdev, offset, &word);
1405 if (ret)
1406 return ret;
1407 *wordp = cpu_to_le16(word);
1408 filled = 2;
1409 } else {
1410 u8 *byte = &vdev->vconfig[offset];
1411 ret = pci_read_config_byte(pdev, offset, byte);
1412 if (ret)
1413 return ret;
1414 filled = 1;
1415 }
1416
1417 offset += filled;
1418 size -= filled;
1419 }
1420
1421 return ret;
1422 }
1423
vfio_cap_init(struct vfio_pci_device * vdev)1424 static int vfio_cap_init(struct vfio_pci_device *vdev)
1425 {
1426 struct pci_dev *pdev = vdev->pdev;
1427 u8 *map = vdev->pci_config_map;
1428 u16 status;
1429 u8 pos, *prev, cap;
1430 int loops, ret, caps = 0;
1431
1432 /* Any capabilities? */
1433 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
1434 if (ret)
1435 return ret;
1436
1437 if (!(status & PCI_STATUS_CAP_LIST))
1438 return 0; /* Done */
1439
1440 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
1441 if (ret)
1442 return ret;
1443
1444 /* Mark the previous position in case we want to skip a capability */
1445 prev = &vdev->vconfig[PCI_CAPABILITY_LIST];
1446
1447 /* We can bound our loop, capabilities are dword aligned */
1448 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;
1449 while (pos && loops--) {
1450 u8 next;
1451 int i, len = 0;
1452
1453 ret = pci_read_config_byte(pdev, pos, &cap);
1454 if (ret)
1455 return ret;
1456
1457 ret = pci_read_config_byte(pdev,
1458 pos + PCI_CAP_LIST_NEXT, &next);
1459 if (ret)
1460 return ret;
1461
1462 if (cap <= PCI_CAP_ID_MAX) {
1463 len = pci_cap_length[cap];
1464 if (len == 0xFF) { /* Variable length */
1465 len = vfio_cap_len(vdev, cap, pos);
1466 if (len < 0)
1467 return len;
1468 }
1469 }
1470
1471 if (!len) {
1472 pr_info("%s: %s hiding cap 0x%x\n",
1473 __func__, dev_name(&pdev->dev), cap);
1474 *prev = next;
1475 pos = next;
1476 continue;
1477 }
1478
1479 /* Sanity check, do we overlap other capabilities? */
1480 for (i = 0; i < len; i++) {
1481 if (likely(map[pos + i] == PCI_CAP_ID_INVALID))
1482 continue;
1483
1484 pr_warn("%s: %s pci config conflict @0x%x, was cap 0x%x now cap 0x%x\n",
1485 __func__, dev_name(&pdev->dev),
1486 pos + i, map[pos + i], cap);
1487 }
1488
1489 BUILD_BUG_ON(PCI_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1490
1491 memset(map + pos, cap, len);
1492 ret = vfio_fill_vconfig_bytes(vdev, pos, len);
1493 if (ret)
1494 return ret;
1495
1496 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT];
1497 pos = next;
1498 caps++;
1499 }
1500
1501 /* If we didn't fill any capabilities, clear the status flag */
1502 if (!caps) {
1503 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS];
1504 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST);
1505 }
1506
1507 return 0;
1508 }
1509
vfio_ecap_init(struct vfio_pci_device * vdev)1510 static int vfio_ecap_init(struct vfio_pci_device *vdev)
1511 {
1512 struct pci_dev *pdev = vdev->pdev;
1513 u8 *map = vdev->pci_config_map;
1514 u16 epos;
1515 __le32 *prev = NULL;
1516 int loops, ret, ecaps = 0;
1517
1518 if (!vdev->extended_caps)
1519 return 0;
1520
1521 epos = PCI_CFG_SPACE_SIZE;
1522
1523 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF;
1524
1525 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) {
1526 u32 header;
1527 u16 ecap;
1528 int i, len = 0;
1529 bool hidden = false;
1530
1531 ret = pci_read_config_dword(pdev, epos, &header);
1532 if (ret)
1533 return ret;
1534
1535 ecap = PCI_EXT_CAP_ID(header);
1536
1537 if (ecap <= PCI_EXT_CAP_ID_MAX) {
1538 len = pci_ext_cap_length[ecap];
1539 if (len == 0xFF) {
1540 len = vfio_ext_cap_len(vdev, ecap, epos);
1541 if (len < 0)
1542 return ret;
1543 }
1544 }
1545
1546 if (!len) {
1547 pr_info("%s: %s hiding ecap 0x%x@0x%x\n",
1548 __func__, dev_name(&pdev->dev), ecap, epos);
1549
1550 /* If not the first in the chain, we can skip over it */
1551 if (prev) {
1552 u32 val = epos = PCI_EXT_CAP_NEXT(header);
1553 *prev &= cpu_to_le32(~(0xffcU << 20));
1554 *prev |= cpu_to_le32(val << 20);
1555 continue;
1556 }
1557
1558 /*
1559 * Otherwise, fill in a placeholder, the direct
1560 * readfn will virtualize this automatically
1561 */
1562 len = PCI_CAP_SIZEOF;
1563 hidden = true;
1564 }
1565
1566 for (i = 0; i < len; i++) {
1567 if (likely(map[epos + i] == PCI_CAP_ID_INVALID))
1568 continue;
1569
1570 pr_warn("%s: %s pci config conflict @0x%x, was ecap 0x%x now ecap 0x%x\n",
1571 __func__, dev_name(&pdev->dev),
1572 epos + i, map[epos + i], ecap);
1573 }
1574
1575 /*
1576 * Even though ecap is 2 bytes, we're currently a long way
1577 * from exceeding 1 byte capabilities. If we ever make it
1578 * up to 0xFE we'll need to up this to a two-byte, byte map.
1579 */
1580 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1581
1582 memset(map + epos, ecap, len);
1583 ret = vfio_fill_vconfig_bytes(vdev, epos, len);
1584 if (ret)
1585 return ret;
1586
1587 /*
1588 * If we're just using this capability to anchor the list,
1589 * hide the real ID. Only count real ecaps. XXX PCI spec
1590 * indicates to use cap id = 0, version = 0, next = 0 if
1591 * ecaps are absent, hope users check all the way to next.
1592 */
1593 if (hidden)
1594 *(__le32 *)&vdev->vconfig[epos] &=
1595 cpu_to_le32((0xffcU << 20));
1596 else
1597 ecaps++;
1598
1599 prev = (__le32 *)&vdev->vconfig[epos];
1600 epos = PCI_EXT_CAP_NEXT(header);
1601 }
1602
1603 if (!ecaps)
1604 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;
1605
1606 return 0;
1607 }
1608
1609 /*
1610 * For each device we allocate a pci_config_map that indicates the
1611 * capability occupying each dword and thus the struct perm_bits we
1612 * use for read and write. We also allocate a virtualized config
1613 * space which tracks reads and writes to bits that we emulate for
1614 * the user. Initial values filled from device.
1615 *
1616 * Using shared struct perm_bits between all vfio-pci devices saves
1617 * us from allocating cfg_size buffers for virt and write for every
1618 * device. We could remove vconfig and allocate individual buffers
1619 * for each area requiring emulated bits, but the array of pointers
1620 * would be comparable in size (at least for standard config space).
1621 */
vfio_config_init(struct vfio_pci_device * vdev)1622 int vfio_config_init(struct vfio_pci_device *vdev)
1623 {
1624 struct pci_dev *pdev = vdev->pdev;
1625 u8 *map, *vconfig;
1626 int ret;
1627
1628 /*
1629 * Config space, caps and ecaps are all dword aligned, so we could
1630 * use one byte per dword to record the type. However, there are
1631 * no requiremenst on the length of a capability, so the gap between
1632 * capabilities needs byte granularity.
1633 */
1634 map = kmalloc(pdev->cfg_size, GFP_KERNEL);
1635 if (!map)
1636 return -ENOMEM;
1637
1638 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL);
1639 if (!vconfig) {
1640 kfree(map);
1641 return -ENOMEM;
1642 }
1643
1644 vdev->pci_config_map = map;
1645 vdev->vconfig = vconfig;
1646
1647 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF);
1648 memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID,
1649 pdev->cfg_size - PCI_STD_HEADER_SIZEOF);
1650
1651 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF);
1652 if (ret)
1653 goto out;
1654
1655 vdev->bardirty = true;
1656
1657 /*
1658 * XXX can we just pci_load_saved_state/pci_restore_state?
1659 * may need to rebuild vconfig after that
1660 */
1661
1662 /* For restore after reset */
1663 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
1664 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]);
1665 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);
1666 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]);
1667 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]);
1668 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]);
1669 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);
1670
1671 if (pdev->is_virtfn) {
1672 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);
1673 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
1674 }
1675
1676 if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx)
1677 vconfig[PCI_INTERRUPT_PIN] = 0;
1678
1679 ret = vfio_cap_init(vdev);
1680 if (ret)
1681 goto out;
1682
1683 ret = vfio_ecap_init(vdev);
1684 if (ret)
1685 goto out;
1686
1687 return 0;
1688
1689 out:
1690 kfree(map);
1691 vdev->pci_config_map = NULL;
1692 kfree(vconfig);
1693 vdev->vconfig = NULL;
1694 return pcibios_err_to_errno(ret);
1695 }
1696
vfio_config_free(struct vfio_pci_device * vdev)1697 void vfio_config_free(struct vfio_pci_device *vdev)
1698 {
1699 kfree(vdev->vconfig);
1700 vdev->vconfig = NULL;
1701 kfree(vdev->pci_config_map);
1702 vdev->pci_config_map = NULL;
1703 kfree(vdev->msi_perm);
1704 vdev->msi_perm = NULL;
1705 }
1706
1707 /*
1708 * Find the remaining number of bytes in a dword that match the given
1709 * position. Stop at either the end of the capability or the dword boundary.
1710 */
vfio_pci_cap_remaining_dword(struct vfio_pci_device * vdev,loff_t pos)1711 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev,
1712 loff_t pos)
1713 {
1714 u8 cap = vdev->pci_config_map[pos];
1715 size_t i;
1716
1717 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++)
1718 /* nop */;
1719
1720 return i;
1721 }
1722
vfio_config_do_rw(struct vfio_pci_device * vdev,char __user * buf,size_t count,loff_t * ppos,bool iswrite)1723 static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf,
1724 size_t count, loff_t *ppos, bool iswrite)
1725 {
1726 struct pci_dev *pdev = vdev->pdev;
1727 struct perm_bits *perm;
1728 __le32 val = 0;
1729 int cap_start = 0, offset;
1730 u8 cap_id;
1731 ssize_t ret;
1732
1733 if (*ppos < 0 || *ppos >= pdev->cfg_size ||
1734 *ppos + count > pdev->cfg_size)
1735 return -EFAULT;
1736
1737 /*
1738 * Chop accesses into aligned chunks containing no more than a
1739 * single capability. Caller increments to the next chunk.
1740 */
1741 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos));
1742 if (count >= 4 && !(*ppos % 4))
1743 count = 4;
1744 else if (count >= 2 && !(*ppos % 2))
1745 count = 2;
1746 else
1747 count = 1;
1748
1749 ret = count;
1750
1751 cap_id = vdev->pci_config_map[*ppos];
1752
1753 if (cap_id == PCI_CAP_ID_INVALID) {
1754 perm = &unassigned_perms;
1755 cap_start = *ppos;
1756 } else if (cap_id == PCI_CAP_ID_INVALID_VIRT) {
1757 perm = &virt_perms;
1758 cap_start = *ppos;
1759 } else {
1760 if (*ppos >= PCI_CFG_SPACE_SIZE) {
1761 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX);
1762
1763 perm = &ecap_perms[cap_id];
1764 cap_start = vfio_find_cap_start(vdev, *ppos);
1765 } else {
1766 WARN_ON(cap_id > PCI_CAP_ID_MAX);
1767
1768 perm = &cap_perms[cap_id];
1769
1770 if (cap_id == PCI_CAP_ID_MSI)
1771 perm = vdev->msi_perm;
1772
1773 if (cap_id > PCI_CAP_ID_BASIC)
1774 cap_start = vfio_find_cap_start(vdev, *ppos);
1775 }
1776 }
1777
1778 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC);
1779 WARN_ON(cap_start > *ppos);
1780
1781 offset = *ppos - cap_start;
1782
1783 if (iswrite) {
1784 if (!perm->writefn)
1785 return ret;
1786
1787 if (copy_from_user(&val, buf, count))
1788 return -EFAULT;
1789
1790 ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
1791 } else {
1792 if (perm->readfn) {
1793 ret = perm->readfn(vdev, *ppos, count,
1794 perm, offset, &val);
1795 if (ret < 0)
1796 return ret;
1797 }
1798
1799 if (copy_to_user(buf, &val, count))
1800 return -EFAULT;
1801 }
1802
1803 return ret;
1804 }
1805
vfio_pci_config_rw(struct vfio_pci_device * vdev,char __user * buf,size_t count,loff_t * ppos,bool iswrite)1806 ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf,
1807 size_t count, loff_t *ppos, bool iswrite)
1808 {
1809 size_t done = 0;
1810 int ret = 0;
1811 loff_t pos = *ppos;
1812
1813 pos &= VFIO_PCI_OFFSET_MASK;
1814
1815 while (count) {
1816 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite);
1817 if (ret < 0)
1818 return ret;
1819
1820 count -= ret;
1821 done += ret;
1822 buf += ret;
1823 pos += ret;
1824 }
1825
1826 *ppos += done;
1827
1828 return done;
1829 }
1830