1 /*
2 * vsp1_rpf.c -- R-Car VSP1 Read Pixel Formatter
3 *
4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
5 *
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/device.h>
15
16 #include <media/v4l2-subdev.h>
17
18 #include "vsp1.h"
19 #include "vsp1_dl.h"
20 #include "vsp1_pipe.h"
21 #include "vsp1_rwpf.h"
22 #include "vsp1_video.h"
23
24 #define RPF_MAX_WIDTH 8190
25 #define RPF_MAX_HEIGHT 8190
26
27 /* -----------------------------------------------------------------------------
28 * Device Access
29 */
30
vsp1_rpf_write(struct vsp1_rwpf * rpf,struct vsp1_dl_list * dl,u32 reg,u32 data)31 static inline void vsp1_rpf_write(struct vsp1_rwpf *rpf,
32 struct vsp1_dl_list *dl, u32 reg, u32 data)
33 {
34 vsp1_dl_list_write(dl, reg + rpf->entity.index * VI6_RPF_OFFSET, data);
35 }
36
37 /* -----------------------------------------------------------------------------
38 * V4L2 Subdevice Operations
39 */
40
41 static const struct v4l2_subdev_ops rpf_ops = {
42 .pad = &vsp1_rwpf_pad_ops,
43 };
44
45 /* -----------------------------------------------------------------------------
46 * VSP1 Entity Operations
47 */
48
rpf_configure(struct vsp1_entity * entity,struct vsp1_pipeline * pipe,struct vsp1_dl_list * dl,enum vsp1_entity_params params)49 static void rpf_configure(struct vsp1_entity *entity,
50 struct vsp1_pipeline *pipe,
51 struct vsp1_dl_list *dl,
52 enum vsp1_entity_params params)
53 {
54 struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev);
55 const struct vsp1_format_info *fmtinfo = rpf->fmtinfo;
56 const struct v4l2_pix_format_mplane *format = &rpf->format;
57 const struct v4l2_mbus_framefmt *source_format;
58 const struct v4l2_mbus_framefmt *sink_format;
59 unsigned int left = 0;
60 unsigned int top = 0;
61 u32 pstride;
62 u32 infmt;
63
64 if (params == VSP1_ENTITY_PARAMS_RUNTIME) {
65 vsp1_rpf_write(rpf, dl, VI6_RPF_VRTCOL_SET,
66 rpf->alpha << VI6_RPF_VRTCOL_SET_LAYA_SHIFT);
67 vsp1_rpf_write(rpf, dl, VI6_RPF_MULT_ALPHA, rpf->mult_alpha |
68 (rpf->alpha << VI6_RPF_MULT_ALPHA_RATIO_SHIFT));
69
70 vsp1_pipeline_propagate_alpha(pipe, dl, rpf->alpha);
71 return;
72 }
73
74 if (params == VSP1_ENTITY_PARAMS_PARTITION) {
75 unsigned int offsets[2];
76 struct v4l2_rect crop;
77
78 /*
79 * Source size and crop offsets.
80 *
81 * The crop offsets correspond to the location of the crop
82 * rectangle top left corner in the plane buffer. Only two
83 * offsets are needed, as planes 2 and 3 always have identical
84 * strides.
85 */
86 crop = *vsp1_rwpf_get_crop(rpf, rpf->entity.config);
87
88 /*
89 * Partition Algorithm Control
90 *
91 * The partition algorithm can split this frame into multiple
92 * slices. We must scale our partition window based on the pipe
93 * configuration to match the destination partition window.
94 * To achieve this, we adjust our crop to provide a 'sub-crop'
95 * matching the expected partition window. Only 'left' and
96 * 'width' need to be adjusted.
97 */
98 if (pipe->partitions > 1) {
99 const struct v4l2_mbus_framefmt *output;
100 struct vsp1_entity *wpf = &pipe->output->entity;
101 unsigned int input_width = crop.width;
102
103 /*
104 * Scale the partition window based on the configuration
105 * of the pipeline.
106 */
107 output = vsp1_entity_get_pad_format(wpf, wpf->config,
108 RWPF_PAD_SOURCE);
109
110 crop.width = pipe->partition.width * input_width
111 / output->width;
112 crop.left += pipe->partition.left * input_width
113 / output->width;
114 }
115
116 vsp1_rpf_write(rpf, dl, VI6_RPF_SRC_BSIZE,
117 (crop.width << VI6_RPF_SRC_BSIZE_BHSIZE_SHIFT) |
118 (crop.height << VI6_RPF_SRC_BSIZE_BVSIZE_SHIFT));
119 vsp1_rpf_write(rpf, dl, VI6_RPF_SRC_ESIZE,
120 (crop.width << VI6_RPF_SRC_ESIZE_EHSIZE_SHIFT) |
121 (crop.height << VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT));
122
123 offsets[0] = crop.top * format->plane_fmt[0].bytesperline
124 + crop.left * fmtinfo->bpp[0] / 8;
125
126 if (format->num_planes > 1)
127 offsets[1] = crop.top * format->plane_fmt[1].bytesperline
128 + crop.left / fmtinfo->hsub
129 * fmtinfo->bpp[1] / 8;
130 else
131 offsets[1] = 0;
132
133 vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_Y,
134 rpf->mem.addr[0] + offsets[0]);
135 vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_C0,
136 rpf->mem.addr[1] + offsets[1]);
137 vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_C1,
138 rpf->mem.addr[2] + offsets[1]);
139 return;
140 }
141
142 /* Stride */
143 pstride = format->plane_fmt[0].bytesperline
144 << VI6_RPF_SRCM_PSTRIDE_Y_SHIFT;
145 if (format->num_planes > 1)
146 pstride |= format->plane_fmt[1].bytesperline
147 << VI6_RPF_SRCM_PSTRIDE_C_SHIFT;
148
149 vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_PSTRIDE, pstride);
150
151 /* Format */
152 sink_format = vsp1_entity_get_pad_format(&rpf->entity,
153 rpf->entity.config,
154 RWPF_PAD_SINK);
155 source_format = vsp1_entity_get_pad_format(&rpf->entity,
156 rpf->entity.config,
157 RWPF_PAD_SOURCE);
158
159 infmt = VI6_RPF_INFMT_CIPM
160 | (fmtinfo->hwfmt << VI6_RPF_INFMT_RDFMT_SHIFT);
161
162 if (fmtinfo->swap_yc)
163 infmt |= VI6_RPF_INFMT_SPYCS;
164 if (fmtinfo->swap_uv)
165 infmt |= VI6_RPF_INFMT_SPUVS;
166
167 if (sink_format->code != source_format->code)
168 infmt |= VI6_RPF_INFMT_CSC;
169
170 vsp1_rpf_write(rpf, dl, VI6_RPF_INFMT, infmt);
171 vsp1_rpf_write(rpf, dl, VI6_RPF_DSWAP, fmtinfo->swap);
172
173 /* Output location */
174 if (pipe->bru) {
175 const struct v4l2_rect *compose;
176
177 compose = vsp1_entity_get_pad_selection(pipe->bru,
178 pipe->bru->config,
179 rpf->bru_input,
180 V4L2_SEL_TGT_COMPOSE);
181 left = compose->left;
182 top = compose->top;
183 }
184
185 vsp1_rpf_write(rpf, dl, VI6_RPF_LOC,
186 (left << VI6_RPF_LOC_HCOORD_SHIFT) |
187 (top << VI6_RPF_LOC_VCOORD_SHIFT));
188
189 /* On Gen2 use the alpha channel (extended to 8 bits) when available or
190 * a fixed alpha value set through the V4L2_CID_ALPHA_COMPONENT control
191 * otherwise.
192 *
193 * The Gen3 RPF has extended alpha capability and can both multiply the
194 * alpha channel by a fixed global alpha value, and multiply the pixel
195 * components to convert the input to premultiplied alpha.
196 *
197 * As alpha premultiplication is available in the BRU for both Gen2 and
198 * Gen3 we handle it there and use the Gen3 alpha multiplier for global
199 * alpha multiplication only. This however prevents conversion to
200 * premultiplied alpha if no BRU is present in the pipeline. If that use
201 * case turns out to be useful we will revisit the implementation (for
202 * Gen3 only).
203 *
204 * We enable alpha multiplication on Gen3 using the fixed alpha value
205 * set through the V4L2_CID_ALPHA_COMPONENT control when the input
206 * contains an alpha channel. On Gen2 the global alpha is ignored in
207 * that case.
208 *
209 * In all cases, disable color keying.
210 */
211 vsp1_rpf_write(rpf, dl, VI6_RPF_ALPH_SEL, VI6_RPF_ALPH_SEL_AEXT_EXT |
212 (fmtinfo->alpha ? VI6_RPF_ALPH_SEL_ASEL_PACKED
213 : VI6_RPF_ALPH_SEL_ASEL_FIXED));
214
215 if (entity->vsp1->info->gen == 3) {
216 u32 mult;
217
218 if (fmtinfo->alpha) {
219 /* When the input contains an alpha channel enable the
220 * alpha multiplier. If the input is premultiplied we
221 * need to multiply both the alpha channel and the pixel
222 * components by the global alpha value to keep them
223 * premultiplied. Otherwise multiply the alpha channel
224 * only.
225 */
226 bool premultiplied = format->flags
227 & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA;
228
229 mult = VI6_RPF_MULT_ALPHA_A_MMD_RATIO
230 | (premultiplied ?
231 VI6_RPF_MULT_ALPHA_P_MMD_RATIO :
232 VI6_RPF_MULT_ALPHA_P_MMD_NONE);
233 } else {
234 /* When the input doesn't contain an alpha channel the
235 * global alpha value is applied in the unpacking unit,
236 * the alpha multiplier isn't needed and must be
237 * disabled.
238 */
239 mult = VI6_RPF_MULT_ALPHA_A_MMD_NONE
240 | VI6_RPF_MULT_ALPHA_P_MMD_NONE;
241 }
242
243 rpf->mult_alpha = mult;
244 }
245
246 vsp1_rpf_write(rpf, dl, VI6_RPF_MSK_CTRL, 0);
247 vsp1_rpf_write(rpf, dl, VI6_RPF_CKEY_CTRL, 0);
248
249 }
250
251 static const struct vsp1_entity_operations rpf_entity_ops = {
252 .configure = rpf_configure,
253 };
254
255 /* -----------------------------------------------------------------------------
256 * Initialization and Cleanup
257 */
258
vsp1_rpf_create(struct vsp1_device * vsp1,unsigned int index)259 struct vsp1_rwpf *vsp1_rpf_create(struct vsp1_device *vsp1, unsigned int index)
260 {
261 struct vsp1_rwpf *rpf;
262 char name[6];
263 int ret;
264
265 rpf = devm_kzalloc(vsp1->dev, sizeof(*rpf), GFP_KERNEL);
266 if (rpf == NULL)
267 return ERR_PTR(-ENOMEM);
268
269 rpf->max_width = RPF_MAX_WIDTH;
270 rpf->max_height = RPF_MAX_HEIGHT;
271
272 rpf->entity.ops = &rpf_entity_ops;
273 rpf->entity.type = VSP1_ENTITY_RPF;
274 rpf->entity.index = index;
275
276 sprintf(name, "rpf.%u", index);
277 ret = vsp1_entity_init(vsp1, &rpf->entity, name, 2, &rpf_ops,
278 MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER);
279 if (ret < 0)
280 return ERR_PTR(ret);
281
282 /* Initialize the control handler. */
283 ret = vsp1_rwpf_init_ctrls(rpf, 0);
284 if (ret < 0) {
285 dev_err(vsp1->dev, "rpf%u: failed to initialize controls\n",
286 index);
287 goto error;
288 }
289
290 v4l2_ctrl_handler_setup(&rpf->ctrls);
291
292 return rpf;
293
294 error:
295 vsp1_entity_destroy(&rpf->entity);
296 return ERR_PTR(ret);
297 }
298