1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* Forward declaration, a strange C thing */
7 struct task_struct;
8 struct mm_struct;
9 struct vm86;
10
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <uapi/asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeatures.h>
17 #include <asm/page.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
20 #include <asm/msr.h>
21 #include <asm/desc_defs.h>
22 #include <asm/nops.h>
23 #include <asm/special_insns.h>
24 #include <asm/fpu/types.h>
25
26 #include <linux/personality.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/err.h>
31 #include <linux/irqflags.h>
32
33 /*
34 * We handle most unaligned accesses in hardware. On the other hand
35 * unaligned DMA can be quite expensive on some Nehalem processors.
36 *
37 * Based on this we disable the IP header alignment in network drivers.
38 */
39 #define NET_IP_ALIGN 0
40
41 #define HBP_NUM 4
42 /*
43 * Default implementation of macro that returns current
44 * instruction pointer ("program counter").
45 */
current_text_addr(void)46 static inline void *current_text_addr(void)
47 {
48 void *pc;
49
50 asm volatile("mov $1f, %0; 1:":"=r" (pc));
51
52 return pc;
53 }
54
55 /*
56 * These alignment constraints are for performance in the vSMP case,
57 * but in the task_struct case we must also meet hardware imposed
58 * alignment requirements of the FPU state:
59 */
60 #ifdef CONFIG_X86_VSMP
61 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
62 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
63 #else
64 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
65 # define ARCH_MIN_MMSTRUCT_ALIGN 0
66 #endif
67
68 enum tlb_infos {
69 ENTRIES,
70 NR_INFO
71 };
72
73 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
74 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
75 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
76 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
77 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
78 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
79 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
80
81 /*
82 * CPU type and hardware bug flags. Kept separately for each CPU.
83 * Members of this structure are referenced in head.S, so think twice
84 * before touching them. [mj]
85 */
86
87 struct cpuinfo_x86 {
88 __u8 x86; /* CPU family */
89 __u8 x86_vendor; /* CPU vendor */
90 __u8 x86_model;
91 __u8 x86_stepping;
92 #ifdef CONFIG_X86_32
93 char wp_works_ok; /* It doesn't on 386's */
94
95 /* Problems on some 486Dx4's and old 386's: */
96 char rfu;
97 char pad0;
98 char pad1;
99 #else
100 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
101 int x86_tlbsize;
102 #endif
103 __u8 x86_virt_bits;
104 __u8 x86_phys_bits;
105 /* CPUID returned core id bits: */
106 __u8 x86_coreid_bits;
107 __u8 cu_id;
108 /* Max extended CPUID function supported: */
109 __u32 extended_cpuid_level;
110 /* Maximum supported CPUID level, -1=no CPUID: */
111 int cpuid_level;
112 __u32 x86_capability[NCAPINTS + NBUGINTS];
113 char x86_vendor_id[16];
114 char x86_model_id[64];
115 /* in KB - valid for CPUS which support this call: */
116 unsigned int x86_cache_size;
117 int x86_cache_alignment; /* In bytes */
118 /* Cache QoS architectural values: */
119 int x86_cache_max_rmid; /* max index */
120 int x86_cache_occ_scale; /* scale to bytes */
121 int x86_power;
122 unsigned long loops_per_jiffy;
123 /* cpuid returned max cores value: */
124 u16 x86_max_cores;
125 u16 apicid;
126 u16 initial_apicid;
127 u16 x86_clflush_size;
128 /* number of cores as seen by the OS: */
129 u16 booted_cores;
130 /* Physical processor id: */
131 u16 phys_proc_id;
132 /* Logical processor id: */
133 u16 logical_proc_id;
134 /* Core id: */
135 u16 cpu_core_id;
136 /* Index into per_cpu list: */
137 u16 cpu_index;
138 u32 microcode;
139 };
140
141 #define X86_VENDOR_INTEL 0
142 #define X86_VENDOR_CYRIX 1
143 #define X86_VENDOR_AMD 2
144 #define X86_VENDOR_UMC 3
145 #define X86_VENDOR_CENTAUR 5
146 #define X86_VENDOR_TRANSMETA 7
147 #define X86_VENDOR_NSC 8
148 #define X86_VENDOR_NUM 9
149
150 #define X86_VENDOR_UNKNOWN 0xff
151
152 /*
153 * capabilities of CPUs
154 */
155 extern struct cpuinfo_x86 boot_cpu_data;
156 extern struct cpuinfo_x86 new_cpu_data;
157
158 extern struct tss_struct doublefault_tss;
159 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
160 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
161
162 #ifdef CONFIG_SMP
163 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
164 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
165 #else
166 #define cpu_info boot_cpu_data
167 #define cpu_data(cpu) boot_cpu_data
168 #endif
169
170 extern const struct seq_operations cpuinfo_op;
171
172 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
173
174 extern void cpu_detect(struct cpuinfo_x86 *c);
175
176 extern void early_cpu_init(void);
177 extern void identify_boot_cpu(void);
178 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
179 extern void print_cpu_info(struct cpuinfo_x86 *);
180 void print_cpu_msr(struct cpuinfo_x86 *);
181 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
182 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
183 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
184
185 extern void detect_extended_topology(struct cpuinfo_x86 *c);
186 extern void detect_ht(struct cpuinfo_x86 *c);
187
188 #ifdef CONFIG_X86_32
189 extern int have_cpuid_p(void);
190 #else
have_cpuid_p(void)191 static inline int have_cpuid_p(void)
192 {
193 return 1;
194 }
195 #endif
native_cpuid(unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)196 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
197 unsigned int *ecx, unsigned int *edx)
198 {
199 /* ecx is often an input as well as an output. */
200 asm volatile("cpuid"
201 : "=a" (*eax),
202 "=b" (*ebx),
203 "=c" (*ecx),
204 "=d" (*edx)
205 : "0" (*eax), "2" (*ecx)
206 : "memory");
207 }
208
load_cr3(pgd_t * pgdir)209 static inline void load_cr3(pgd_t *pgdir)
210 {
211 write_cr3(__pa(pgdir));
212 }
213
214 #ifdef CONFIG_X86_32
215 /* This is the TSS defined by the hardware. */
216 struct x86_hw_tss {
217 unsigned short back_link, __blh;
218 unsigned long sp0;
219 unsigned short ss0, __ss0h;
220 unsigned long sp1;
221
222 /*
223 * We don't use ring 1, so ss1 is a convenient scratch space in
224 * the same cacheline as sp0. We use ss1 to cache the value in
225 * MSR_IA32_SYSENTER_CS. When we context switch
226 * MSR_IA32_SYSENTER_CS, we first check if the new value being
227 * written matches ss1, and, if it's not, then we wrmsr the new
228 * value and update ss1.
229 *
230 * The only reason we context switch MSR_IA32_SYSENTER_CS is
231 * that we set it to zero in vm86 tasks to avoid corrupting the
232 * stack if we were to go through the sysenter path from vm86
233 * mode.
234 */
235 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
236
237 unsigned short __ss1h;
238 unsigned long sp2;
239 unsigned short ss2, __ss2h;
240 unsigned long __cr3;
241 unsigned long ip;
242 unsigned long flags;
243 unsigned long ax;
244 unsigned long cx;
245 unsigned long dx;
246 unsigned long bx;
247 unsigned long sp;
248 unsigned long bp;
249 unsigned long si;
250 unsigned long di;
251 unsigned short es, __esh;
252 unsigned short cs, __csh;
253 unsigned short ss, __ssh;
254 unsigned short ds, __dsh;
255 unsigned short fs, __fsh;
256 unsigned short gs, __gsh;
257 unsigned short ldt, __ldth;
258 unsigned short trace;
259 unsigned short io_bitmap_base;
260
261 } __attribute__((packed));
262 #else
263 struct x86_hw_tss {
264 u32 reserved1;
265 u64 sp0;
266 u64 sp1;
267 u64 sp2;
268 u64 reserved2;
269 u64 ist[7];
270 u32 reserved3;
271 u32 reserved4;
272 u16 reserved5;
273 u16 io_bitmap_base;
274
275 } __attribute__((packed)) ____cacheline_aligned;
276 #endif
277
278 /*
279 * IO-bitmap sizes:
280 */
281 #define IO_BITMAP_BITS 65536
282 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
283 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
284 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
285 #define INVALID_IO_BITMAP_OFFSET 0x8000
286
287 struct tss_struct {
288 /*
289 * The hardware state:
290 */
291 struct x86_hw_tss x86_tss;
292
293 /*
294 * The extra 1 is there because the CPU will access an
295 * additional byte beyond the end of the IO permission
296 * bitmap. The extra byte must be all 1 bits, and must
297 * be within the limit.
298 */
299 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
300
301 #ifdef CONFIG_X86_32
302 /*
303 * Space for the temporary SYSENTER stack.
304 */
305 unsigned long SYSENTER_stack_canary;
306 unsigned long SYSENTER_stack[64];
307 #endif
308
309 } ____cacheline_aligned;
310
311 DECLARE_PER_CPU_SHARED_ALIGNED_USER_MAPPED(struct tss_struct, cpu_tss);
312
313 #ifdef CONFIG_X86_32
314 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
315 #endif
316
317 /*
318 * Save the original ist values for checking stack pointers during debugging
319 */
320 struct orig_ist {
321 unsigned long ist[7];
322 };
323
324 #ifdef CONFIG_X86_64
325 DECLARE_PER_CPU(struct orig_ist, orig_ist);
326
327 union irq_stack_union {
328 char irq_stack[IRQ_STACK_SIZE];
329 /*
330 * GCC hardcodes the stack canary as %gs:40. Since the
331 * irq_stack is the object at %gs:0, we reserve the bottom
332 * 48 bytes of the irq stack for the canary.
333 */
334 struct {
335 char gs_base[40];
336 unsigned long stack_canary;
337 };
338 };
339
340 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
341 DECLARE_INIT_PER_CPU(irq_stack_union);
342
343 DECLARE_PER_CPU(char *, irq_stack_ptr);
344 DECLARE_PER_CPU(unsigned int, irq_count);
345 extern asmlinkage void ignore_sysret(void);
346 #else /* X86_64 */
347 #ifdef CONFIG_CC_STACKPROTECTOR
348 /*
349 * Make sure stack canary segment base is cached-aligned:
350 * "For Intel Atom processors, avoid non zero segment base address
351 * that is not aligned to cache line boundary at all cost."
352 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
353 */
354 struct stack_canary {
355 char __pad[20]; /* canary at %gs:20 */
356 unsigned long canary;
357 };
358 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
359 #endif
360 /*
361 * per-CPU IRQ handling stacks
362 */
363 struct irq_stack {
364 u32 stack[THREAD_SIZE/sizeof(u32)];
365 } __aligned(THREAD_SIZE);
366
367 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
368 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
369 #endif /* X86_64 */
370
371 extern unsigned int fpu_kernel_xstate_size;
372 extern unsigned int fpu_user_xstate_size;
373
374 struct perf_event;
375
376 typedef struct {
377 unsigned long seg;
378 } mm_segment_t;
379
380 struct thread_struct {
381 /* Cached TLS descriptors: */
382 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
383 unsigned long sp0;
384 unsigned long sp;
385 #ifdef CONFIG_X86_32
386 unsigned long sysenter_cs;
387 #else
388 unsigned short es;
389 unsigned short ds;
390 unsigned short fsindex;
391 unsigned short gsindex;
392 #endif
393
394 #ifdef CONFIG_X86_64
395 unsigned long fsbase;
396 unsigned long gsbase;
397 #else
398 /*
399 * XXX: this could presumably be unsigned short. Alternatively,
400 * 32-bit kernels could be taught to use fsindex instead.
401 */
402 unsigned long fs;
403 unsigned long gs;
404 #endif
405
406 /* Save middle states of ptrace breakpoints */
407 struct perf_event *ptrace_bps[HBP_NUM];
408 /* Debug status used for traps, single steps, etc... */
409 unsigned long debugreg6;
410 /* Keep track of the exact dr7 value set by the user */
411 unsigned long ptrace_dr7;
412 /* Fault info: */
413 unsigned long cr2;
414 unsigned long trap_nr;
415 unsigned long error_code;
416 #ifdef CONFIG_VM86
417 /* Virtual 86 mode info */
418 struct vm86 *vm86;
419 #endif
420 /* IO permissions: */
421 unsigned long *io_bitmap_ptr;
422 unsigned long iopl;
423 /* Max allowed port in the bitmap, in bytes: */
424 unsigned io_bitmap_max;
425
426 mm_segment_t addr_limit;
427
428 unsigned int sig_on_uaccess_err:1;
429 unsigned int uaccess_err:1; /* uaccess failed */
430
431 /* Floating point and extended processor state */
432 struct fpu fpu;
433 /*
434 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
435 * the end.
436 */
437 };
438
439 /*
440 * Thread-synchronous status.
441 *
442 * This is different from the flags in that nobody else
443 * ever touches our thread-synchronous status, so we don't
444 * have to worry about atomic accesses.
445 */
446 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
447
448 /*
449 * Set IOPL bits in EFLAGS from given mask
450 */
native_set_iopl_mask(unsigned mask)451 static inline void native_set_iopl_mask(unsigned mask)
452 {
453 #ifdef CONFIG_X86_32
454 unsigned int reg;
455
456 asm volatile ("pushfl;"
457 "popl %0;"
458 "andl %1, %0;"
459 "orl %2, %0;"
460 "pushl %0;"
461 "popfl"
462 : "=&r" (reg)
463 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
464 #endif
465 }
466
467 static inline void
native_load_sp0(struct tss_struct * tss,struct thread_struct * thread)468 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
469 {
470 tss->x86_tss.sp0 = thread->sp0;
471 #ifdef CONFIG_X86_32
472 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
473 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
474 tss->x86_tss.ss1 = thread->sysenter_cs;
475 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
476 }
477 #endif
478 }
479
native_swapgs(void)480 static inline void native_swapgs(void)
481 {
482 #ifdef CONFIG_X86_64
483 asm volatile("swapgs" ::: "memory");
484 #endif
485 }
486
current_top_of_stack(void)487 static inline unsigned long current_top_of_stack(void)
488 {
489 #ifdef CONFIG_X86_64
490 return this_cpu_read_stable(cpu_tss.x86_tss.sp0);
491 #else
492 /* sp0 on x86_32 is special in and around vm86 mode. */
493 return this_cpu_read_stable(cpu_current_top_of_stack);
494 #endif
495 }
496
497 #ifdef CONFIG_PARAVIRT
498 #include <asm/paravirt.h>
499 #else
500 #define __cpuid native_cpuid
501
load_sp0(struct tss_struct * tss,struct thread_struct * thread)502 static inline void load_sp0(struct tss_struct *tss,
503 struct thread_struct *thread)
504 {
505 native_load_sp0(tss, thread);
506 }
507
508 #define set_iopl_mask native_set_iopl_mask
509 #endif /* CONFIG_PARAVIRT */
510
511 /* Free all resources held by a thread. */
512 extern void release_thread(struct task_struct *);
513
514 unsigned long get_wchan(struct task_struct *p);
515
516 /*
517 * Generic CPUID function
518 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
519 * resulting in stale register contents being returned.
520 */
cpuid(unsigned int op,unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)521 static inline void cpuid(unsigned int op,
522 unsigned int *eax, unsigned int *ebx,
523 unsigned int *ecx, unsigned int *edx)
524 {
525 *eax = op;
526 *ecx = 0;
527 __cpuid(eax, ebx, ecx, edx);
528 }
529
530 /* Some CPUID calls want 'count' to be placed in ecx */
cpuid_count(unsigned int op,int count,unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)531 static inline void cpuid_count(unsigned int op, int count,
532 unsigned int *eax, unsigned int *ebx,
533 unsigned int *ecx, unsigned int *edx)
534 {
535 *eax = op;
536 *ecx = count;
537 __cpuid(eax, ebx, ecx, edx);
538 }
539
540 /*
541 * CPUID functions returning a single datum
542 */
cpuid_eax(unsigned int op)543 static inline unsigned int cpuid_eax(unsigned int op)
544 {
545 unsigned int eax, ebx, ecx, edx;
546
547 cpuid(op, &eax, &ebx, &ecx, &edx);
548
549 return eax;
550 }
551
cpuid_ebx(unsigned int op)552 static inline unsigned int cpuid_ebx(unsigned int op)
553 {
554 unsigned int eax, ebx, ecx, edx;
555
556 cpuid(op, &eax, &ebx, &ecx, &edx);
557
558 return ebx;
559 }
560
cpuid_ecx(unsigned int op)561 static inline unsigned int cpuid_ecx(unsigned int op)
562 {
563 unsigned int eax, ebx, ecx, edx;
564
565 cpuid(op, &eax, &ebx, &ecx, &edx);
566
567 return ecx;
568 }
569
cpuid_edx(unsigned int op)570 static inline unsigned int cpuid_edx(unsigned int op)
571 {
572 unsigned int eax, ebx, ecx, edx;
573
574 cpuid(op, &eax, &ebx, &ecx, &edx);
575
576 return edx;
577 }
578
579 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
rep_nop(void)580 static __always_inline void rep_nop(void)
581 {
582 asm volatile("rep; nop" ::: "memory");
583 }
584
cpu_relax(void)585 static __always_inline void cpu_relax(void)
586 {
587 rep_nop();
588 }
589
590 #define cpu_relax_lowlatency() cpu_relax()
591
592 /* Stop speculative execution and prefetching of modified code. */
sync_core(void)593 static inline void sync_core(void)
594 {
595 int tmp;
596
597 #ifdef CONFIG_X86_32
598 /*
599 * Do a CPUID if available, otherwise do a jump. The jump
600 * can conveniently enough be the jump around CPUID.
601 */
602 asm volatile("cmpl %2,%1\n\t"
603 "jl 1f\n\t"
604 "cpuid\n"
605 "1:"
606 : "=a" (tmp)
607 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
608 : "ebx", "ecx", "edx", "memory");
609 #else
610 /*
611 * CPUID is a barrier to speculative execution.
612 * Prefetched instructions are automatically
613 * invalidated when modified.
614 */
615 asm volatile("cpuid"
616 : "=a" (tmp)
617 : "0" (1)
618 : "ebx", "ecx", "edx", "memory");
619 #endif
620 }
621
622 extern void select_idle_routine(const struct cpuinfo_x86 *c);
623 extern void init_amd_e400_c1e_mask(void);
624
625 extern unsigned long boot_option_idle_override;
626 extern bool amd_e400_c1e_detected;
627
628 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
629 IDLE_POLL};
630
631 extern void enable_sep_cpu(void);
632 extern int sysenter_setup(void);
633
634 extern void early_trap_init(void);
635 void early_trap_pf_init(void);
636
637 /* Defined in head.S */
638 extern struct desc_ptr early_gdt_descr;
639
640 extern void cpu_set_gdt(int);
641 extern void switch_to_new_gdt(int);
642 extern void load_percpu_segment(int);
643 extern void cpu_init(void);
644
get_debugctlmsr(void)645 static inline unsigned long get_debugctlmsr(void)
646 {
647 unsigned long debugctlmsr = 0;
648
649 #ifndef CONFIG_X86_DEBUGCTLMSR
650 if (boot_cpu_data.x86 < 6)
651 return 0;
652 #endif
653 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
654
655 return debugctlmsr;
656 }
657
update_debugctlmsr(unsigned long debugctlmsr)658 static inline void update_debugctlmsr(unsigned long debugctlmsr)
659 {
660 #ifndef CONFIG_X86_DEBUGCTLMSR
661 if (boot_cpu_data.x86 < 6)
662 return;
663 #endif
664 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
665 }
666
667 extern void set_task_blockstep(struct task_struct *task, bool on);
668
669 /* Boot loader type from the setup header: */
670 extern int bootloader_type;
671 extern int bootloader_version;
672
673 extern char ignore_fpu_irq;
674
675 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
676 #define ARCH_HAS_PREFETCHW
677 #define ARCH_HAS_SPINLOCK_PREFETCH
678
679 #ifdef CONFIG_X86_32
680 # define BASE_PREFETCH ""
681 # define ARCH_HAS_PREFETCH
682 #else
683 # define BASE_PREFETCH "prefetcht0 %P1"
684 #endif
685
686 /*
687 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
688 *
689 * It's not worth to care about 3dnow prefetches for the K6
690 * because they are microcoded there and very slow.
691 */
prefetch(const void * x)692 static inline void prefetch(const void *x)
693 {
694 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
695 X86_FEATURE_XMM,
696 "m" (*(const char *)x));
697 }
698
699 /*
700 * 3dnow prefetch to get an exclusive cache line.
701 * Useful for spinlocks to avoid one state transition in the
702 * cache coherency protocol:
703 */
prefetchw(const void * x)704 static inline void prefetchw(const void *x)
705 {
706 alternative_input(BASE_PREFETCH, "prefetchw %P1",
707 X86_FEATURE_3DNOWPREFETCH,
708 "m" (*(const char *)x));
709 }
710
spin_lock_prefetch(const void * x)711 static inline void spin_lock_prefetch(const void *x)
712 {
713 prefetchw(x);
714 }
715
716 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
717 TOP_OF_KERNEL_STACK_PADDING)
718
719 #ifdef CONFIG_X86_32
720 /*
721 * User space process size: 3GB (default).
722 */
723 #define TASK_SIZE PAGE_OFFSET
724 #define TASK_SIZE_MAX TASK_SIZE
725 #define STACK_TOP TASK_SIZE
726 #define STACK_TOP_MAX STACK_TOP
727
728 #define INIT_THREAD { \
729 .sp0 = TOP_OF_INIT_STACK, \
730 .sysenter_cs = __KERNEL_CS, \
731 .io_bitmap_ptr = NULL, \
732 .addr_limit = KERNEL_DS, \
733 }
734
735 /*
736 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack.
737 * This is necessary to guarantee that the entire "struct pt_regs"
738 * is accessible even if the CPU haven't stored the SS/ESP registers
739 * on the stack (interrupt gate does not save these registers
740 * when switching to the same priv ring).
741 * Therefore beware: accessing the ss/esp fields of the
742 * "struct pt_regs" is possible, but they may contain the
743 * completely wrong values.
744 */
745 #define task_pt_regs(task) \
746 ({ \
747 unsigned long __ptr = (unsigned long)task_stack_page(task); \
748 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
749 ((struct pt_regs *)__ptr) - 1; \
750 })
751
752 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
753
754 #else
755 /*
756 * User space process size. 47bits minus one guard page. The guard
757 * page is necessary on Intel CPUs: if a SYSCALL instruction is at
758 * the highest possible canonical userspace address, then that
759 * syscall will enter the kernel with a non-canonical return
760 * address, and SYSRET will explode dangerously. We avoid this
761 * particular problem by preventing anything from being mapped
762 * at the maximum canonical address.
763 */
764 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
765
766 /* This decides where the kernel will search for a free chunk of vm
767 * space during mmap's.
768 */
769 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
770 0xc0000000 : 0xFFFFe000)
771
772 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
773 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
774 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
775 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
776
777 #define STACK_TOP TASK_SIZE
778 #define STACK_TOP_MAX TASK_SIZE_MAX
779
780 #define INIT_THREAD { \
781 .sp0 = TOP_OF_INIT_STACK, \
782 .addr_limit = KERNEL_DS, \
783 }
784
785 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
786 extern unsigned long KSTK_ESP(struct task_struct *task);
787
788 #endif /* CONFIG_X86_64 */
789
790 extern unsigned long thread_saved_pc(struct task_struct *tsk);
791
792 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
793 unsigned long new_sp);
794
795 /*
796 * This decides where the kernel will search for a free chunk of vm
797 * space during mmap's.
798 */
799 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
800
801 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
802
803 /* Get/set a process' ability to use the timestamp counter instruction */
804 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
805 #define SET_TSC_CTL(val) set_tsc_mode((val))
806
807 extern int get_tsc_mode(unsigned long adr);
808 extern int set_tsc_mode(unsigned int val);
809
810 /* Register/unregister a process' MPX related resource */
811 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
812 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
813
814 #ifdef CONFIG_X86_INTEL_MPX
815 extern int mpx_enable_management(void);
816 extern int mpx_disable_management(void);
817 #else
mpx_enable_management(void)818 static inline int mpx_enable_management(void)
819 {
820 return -EINVAL;
821 }
mpx_disable_management(void)822 static inline int mpx_disable_management(void)
823 {
824 return -EINVAL;
825 }
826 #endif /* CONFIG_X86_INTEL_MPX */
827
828 extern u16 amd_get_nb_id(int cpu);
829 extern u32 amd_get_nodes_per_socket(void);
830
hypervisor_cpuid_base(const char * sig,uint32_t leaves)831 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
832 {
833 uint32_t base, eax, signature[3];
834
835 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
836 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
837
838 if (!memcmp(sig, signature, 12) &&
839 (leaves == 0 || ((eax - base) >= leaves)))
840 return base;
841 }
842
843 return 0;
844 }
845
846 extern unsigned long arch_align_stack(unsigned long sp);
847 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
848
849 void default_idle(void);
850 #ifdef CONFIG_XEN
851 bool xen_set_default_idle(void);
852 #else
853 #define xen_set_default_idle 0
854 #endif
855
856 void stop_this_cpu(void *dummy);
857 void df_debug(struct pt_regs *regs, long error_code);
858 #endif /* _ASM_X86_PROCESSOR_H */
859