1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
25 #include <asm/kvm_emulate.h>
26 #include <linux/stringify.h>
27 #include <asm/debugreg.h>
28 #include <asm/nospec-branch.h>
29
30 #include "x86.h"
31 #include "tss.h"
32
33 /*
34 * Operand types
35 */
36 #define OpNone 0ull
37 #define OpImplicit 1ull /* No generic decode */
38 #define OpReg 2ull /* Register */
39 #define OpMem 3ull /* Memory */
40 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
41 #define OpDI 5ull /* ES:DI/EDI/RDI */
42 #define OpMem64 6ull /* Memory, 64-bit */
43 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
44 #define OpDX 8ull /* DX register */
45 #define OpCL 9ull /* CL register (for shifts) */
46 #define OpImmByte 10ull /* 8-bit sign extended immediate */
47 #define OpOne 11ull /* Implied 1 */
48 #define OpImm 12ull /* Sign extended up to 32-bit immediate */
49 #define OpMem16 13ull /* Memory operand (16-bit). */
50 #define OpMem32 14ull /* Memory operand (32-bit). */
51 #define OpImmU 15ull /* Immediate operand, zero extended */
52 #define OpSI 16ull /* SI/ESI/RSI */
53 #define OpImmFAddr 17ull /* Immediate far address */
54 #define OpMemFAddr 18ull /* Far address in memory */
55 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
56 #define OpES 20ull /* ES */
57 #define OpCS 21ull /* CS */
58 #define OpSS 22ull /* SS */
59 #define OpDS 23ull /* DS */
60 #define OpFS 24ull /* FS */
61 #define OpGS 25ull /* GS */
62 #define OpMem8 26ull /* 8-bit zero extended memory operand */
63 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
64 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
65 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
66 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
67
68 #define OpBits 5 /* Width of operand field */
69 #define OpMask ((1ull << OpBits) - 1)
70
71 /*
72 * Opcode effective-address decode tables.
73 * Note that we only emulate instructions that have at least one memory
74 * operand (excluding implicit stack references). We assume that stack
75 * references and instruction fetches will never occur in special memory
76 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
77 * not be handled.
78 */
79
80 /* Operand sizes: 8-bit operands or specified/overridden size. */
81 #define ByteOp (1<<0) /* 8-bit operands. */
82 /* Destination operand type. */
83 #define DstShift 1
84 #define ImplicitOps (OpImplicit << DstShift)
85 #define DstReg (OpReg << DstShift)
86 #define DstMem (OpMem << DstShift)
87 #define DstAcc (OpAcc << DstShift)
88 #define DstDI (OpDI << DstShift)
89 #define DstMem64 (OpMem64 << DstShift)
90 #define DstMem16 (OpMem16 << DstShift)
91 #define DstImmUByte (OpImmUByte << DstShift)
92 #define DstDX (OpDX << DstShift)
93 #define DstAccLo (OpAccLo << DstShift)
94 #define DstMask (OpMask << DstShift)
95 /* Source operand type. */
96 #define SrcShift 6
97 #define SrcNone (OpNone << SrcShift)
98 #define SrcReg (OpReg << SrcShift)
99 #define SrcMem (OpMem << SrcShift)
100 #define SrcMem16 (OpMem16 << SrcShift)
101 #define SrcMem32 (OpMem32 << SrcShift)
102 #define SrcImm (OpImm << SrcShift)
103 #define SrcImmByte (OpImmByte << SrcShift)
104 #define SrcOne (OpOne << SrcShift)
105 #define SrcImmUByte (OpImmUByte << SrcShift)
106 #define SrcImmU (OpImmU << SrcShift)
107 #define SrcSI (OpSI << SrcShift)
108 #define SrcXLat (OpXLat << SrcShift)
109 #define SrcImmFAddr (OpImmFAddr << SrcShift)
110 #define SrcMemFAddr (OpMemFAddr << SrcShift)
111 #define SrcAcc (OpAcc << SrcShift)
112 #define SrcImmU16 (OpImmU16 << SrcShift)
113 #define SrcImm64 (OpImm64 << SrcShift)
114 #define SrcDX (OpDX << SrcShift)
115 #define SrcMem8 (OpMem8 << SrcShift)
116 #define SrcAccHi (OpAccHi << SrcShift)
117 #define SrcMask (OpMask << SrcShift)
118 #define BitOp (1<<11)
119 #define MemAbs (1<<12) /* Memory operand is absolute displacement */
120 #define String (1<<13) /* String instruction (rep capable) */
121 #define Stack (1<<14) /* Stack instruction (push/pop) */
122 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
123 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
124 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
125 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
126 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
127 #define Escape (5<<15) /* Escape to coprocessor instruction */
128 #define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
129 #define ModeDual (7<<15) /* Different instruction for 32/64 bit */
130 #define Sse (1<<18) /* SSE Vector instruction */
131 /* Generic ModRM decode. */
132 #define ModRM (1<<19)
133 /* Destination is only written; never read. */
134 #define Mov (1<<20)
135 /* Misc flags */
136 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
137 #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
138 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
139 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
140 #define Undefined (1<<25) /* No Such Instruction */
141 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
142 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
143 #define No64 (1<<28)
144 #define PageTable (1 << 29) /* instruction used to write page table */
145 #define NotImpl (1 << 30) /* instruction is not implemented */
146 /* Source 2 operand type */
147 #define Src2Shift (31)
148 #define Src2None (OpNone << Src2Shift)
149 #define Src2Mem (OpMem << Src2Shift)
150 #define Src2CL (OpCL << Src2Shift)
151 #define Src2ImmByte (OpImmByte << Src2Shift)
152 #define Src2One (OpOne << Src2Shift)
153 #define Src2Imm (OpImm << Src2Shift)
154 #define Src2ES (OpES << Src2Shift)
155 #define Src2CS (OpCS << Src2Shift)
156 #define Src2SS (OpSS << Src2Shift)
157 #define Src2DS (OpDS << Src2Shift)
158 #define Src2FS (OpFS << Src2Shift)
159 #define Src2GS (OpGS << Src2Shift)
160 #define Src2Mask (OpMask << Src2Shift)
161 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */
162 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
163 #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
164 #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
165 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
166 #define NoWrite ((u64)1 << 45) /* No writeback */
167 #define SrcWrite ((u64)1 << 46) /* Write back src operand */
168 #define NoMod ((u64)1 << 47) /* Mod field is ignored */
169 #define Intercept ((u64)1 << 48) /* Has valid intercept field */
170 #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
171 #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
172 #define NearBranch ((u64)1 << 52) /* Near branches */
173 #define No16 ((u64)1 << 53) /* No 16 bit operand */
174 #define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
175 #define Aligned16 ((u64)1 << 55) /* Aligned to 16 byte boundary (e.g. FXSAVE) */
176
177 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
178
179 #define X2(x...) x, x
180 #define X3(x...) X2(x), x
181 #define X4(x...) X2(x), X2(x)
182 #define X5(x...) X4(x), x
183 #define X6(x...) X4(x), X2(x)
184 #define X7(x...) X4(x), X3(x)
185 #define X8(x...) X4(x), X4(x)
186 #define X16(x...) X8(x), X8(x)
187
188 #define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
189 #define FASTOP_SIZE 8
190
191 /*
192 * fastop functions have a special calling convention:
193 *
194 * dst: rax (in/out)
195 * src: rdx (in/out)
196 * src2: rcx (in)
197 * flags: rflags (in/out)
198 * ex: rsi (in:fastop pointer, out:zero if exception)
199 *
200 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
201 * different operand sizes can be reached by calculation, rather than a jump
202 * table (which would be bigger than the code).
203 *
204 * fastop functions are declared as taking a never-defined fastop parameter,
205 * so they can't be called from C directly.
206 */
207
208 struct fastop;
209
210 struct opcode {
211 u64 flags : 56;
212 u64 intercept : 8;
213 union {
214 int (*execute)(struct x86_emulate_ctxt *ctxt);
215 const struct opcode *group;
216 const struct group_dual *gdual;
217 const struct gprefix *gprefix;
218 const struct escape *esc;
219 const struct instr_dual *idual;
220 const struct mode_dual *mdual;
221 void (*fastop)(struct fastop *fake);
222 } u;
223 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
224 };
225
226 struct group_dual {
227 struct opcode mod012[8];
228 struct opcode mod3[8];
229 };
230
231 struct gprefix {
232 struct opcode pfx_no;
233 struct opcode pfx_66;
234 struct opcode pfx_f2;
235 struct opcode pfx_f3;
236 };
237
238 struct escape {
239 struct opcode op[8];
240 struct opcode high[64];
241 };
242
243 struct instr_dual {
244 struct opcode mod012;
245 struct opcode mod3;
246 };
247
248 struct mode_dual {
249 struct opcode mode32;
250 struct opcode mode64;
251 };
252
253 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
254
255 enum x86_transfer_type {
256 X86_TRANSFER_NONE,
257 X86_TRANSFER_CALL_JMP,
258 X86_TRANSFER_RET,
259 X86_TRANSFER_TASK_SWITCH,
260 };
261
reg_read(struct x86_emulate_ctxt * ctxt,unsigned nr)262 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
263 {
264 if (!(ctxt->regs_valid & (1 << nr))) {
265 ctxt->regs_valid |= 1 << nr;
266 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
267 }
268 return ctxt->_regs[nr];
269 }
270
reg_write(struct x86_emulate_ctxt * ctxt,unsigned nr)271 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
272 {
273 ctxt->regs_valid |= 1 << nr;
274 ctxt->regs_dirty |= 1 << nr;
275 return &ctxt->_regs[nr];
276 }
277
reg_rmw(struct x86_emulate_ctxt * ctxt,unsigned nr)278 static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
279 {
280 reg_read(ctxt, nr);
281 return reg_write(ctxt, nr);
282 }
283
writeback_registers(struct x86_emulate_ctxt * ctxt)284 static void writeback_registers(struct x86_emulate_ctxt *ctxt)
285 {
286 unsigned reg;
287
288 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
289 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
290 }
291
invalidate_registers(struct x86_emulate_ctxt * ctxt)292 static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
293 {
294 ctxt->regs_dirty = 0;
295 ctxt->regs_valid = 0;
296 }
297
298 /*
299 * These EFLAGS bits are restored from saved value during emulation, and
300 * any changes are written back to the saved value after emulation.
301 */
302 #define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
303 X86_EFLAGS_PF|X86_EFLAGS_CF)
304
305 #ifdef CONFIG_X86_64
306 #define ON64(x) x
307 #else
308 #define ON64(x)
309 #endif
310
311 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
312
313 #define FOP_FUNC(name) \
314 ".align " __stringify(FASTOP_SIZE) " \n\t" \
315 ".type " name ", @function \n\t" \
316 name ":\n\t"
317
318 #define FOP_RET "ret \n\t"
319
320 #define FOP_START(op) \
321 extern void em_##op(struct fastop *fake); \
322 asm(".pushsection .text, \"ax\" \n\t" \
323 ".global em_" #op " \n\t" \
324 FOP_FUNC("em_" #op)
325
326 #define FOP_END \
327 ".popsection")
328
329 #define FOPNOP() \
330 FOP_FUNC(__stringify(__UNIQUE_ID(nop))) \
331 FOP_RET
332
333 #define FOP1E(op, dst) \
334 FOP_FUNC(#op "_" #dst) \
335 "10: " #op " %" #dst " \n\t" FOP_RET
336
337 #define FOP1EEX(op, dst) \
338 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
339
340 #define FASTOP1(op) \
341 FOP_START(op) \
342 FOP1E(op##b, al) \
343 FOP1E(op##w, ax) \
344 FOP1E(op##l, eax) \
345 ON64(FOP1E(op##q, rax)) \
346 FOP_END
347
348 /* 1-operand, using src2 (for MUL/DIV r/m) */
349 #define FASTOP1SRC2(op, name) \
350 FOP_START(name) \
351 FOP1E(op, cl) \
352 FOP1E(op, cx) \
353 FOP1E(op, ecx) \
354 ON64(FOP1E(op, rcx)) \
355 FOP_END
356
357 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
358 #define FASTOP1SRC2EX(op, name) \
359 FOP_START(name) \
360 FOP1EEX(op, cl) \
361 FOP1EEX(op, cx) \
362 FOP1EEX(op, ecx) \
363 ON64(FOP1EEX(op, rcx)) \
364 FOP_END
365
366 #define FOP2E(op, dst, src) \
367 FOP_FUNC(#op "_" #dst "_" #src) \
368 #op " %" #src ", %" #dst " \n\t" FOP_RET
369
370 #define FASTOP2(op) \
371 FOP_START(op) \
372 FOP2E(op##b, al, dl) \
373 FOP2E(op##w, ax, dx) \
374 FOP2E(op##l, eax, edx) \
375 ON64(FOP2E(op##q, rax, rdx)) \
376 FOP_END
377
378 /* 2 operand, word only */
379 #define FASTOP2W(op) \
380 FOP_START(op) \
381 FOPNOP() \
382 FOP2E(op##w, ax, dx) \
383 FOP2E(op##l, eax, edx) \
384 ON64(FOP2E(op##q, rax, rdx)) \
385 FOP_END
386
387 /* 2 operand, src is CL */
388 #define FASTOP2CL(op) \
389 FOP_START(op) \
390 FOP2E(op##b, al, cl) \
391 FOP2E(op##w, ax, cl) \
392 FOP2E(op##l, eax, cl) \
393 ON64(FOP2E(op##q, rax, cl)) \
394 FOP_END
395
396 /* 2 operand, src and dest are reversed */
397 #define FASTOP2R(op, name) \
398 FOP_START(name) \
399 FOP2E(op##b, dl, al) \
400 FOP2E(op##w, dx, ax) \
401 FOP2E(op##l, edx, eax) \
402 ON64(FOP2E(op##q, rdx, rax)) \
403 FOP_END
404
405 #define FOP3E(op, dst, src, src2) \
406 FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \
407 #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
408
409 /* 3-operand, word-only, src2=cl */
410 #define FASTOP3WCL(op) \
411 FOP_START(op) \
412 FOPNOP() \
413 FOP3E(op##w, ax, dx, cl) \
414 FOP3E(op##l, eax, edx, cl) \
415 ON64(FOP3E(op##q, rax, rdx, cl)) \
416 FOP_END
417
418 /* Special case for SETcc - 1 instruction per cc */
419 #define FOP_SETCC(op) \
420 ".align 4 \n\t" \
421 ".type " #op ", @function \n\t" \
422 #op ": \n\t" \
423 #op " %al \n\t" \
424 FOP_RET
425
426 asm(".global kvm_fastop_exception \n"
427 "kvm_fastop_exception: xor %esi, %esi; ret");
428
429 FOP_START(setcc)
430 FOP_SETCC(seto)
431 FOP_SETCC(setno)
432 FOP_SETCC(setc)
433 FOP_SETCC(setnc)
434 FOP_SETCC(setz)
435 FOP_SETCC(setnz)
436 FOP_SETCC(setbe)
437 FOP_SETCC(setnbe)
438 FOP_SETCC(sets)
439 FOP_SETCC(setns)
440 FOP_SETCC(setp)
441 FOP_SETCC(setnp)
442 FOP_SETCC(setl)
443 FOP_SETCC(setnl)
444 FOP_SETCC(setle)
445 FOP_SETCC(setnle)
446 FOP_END;
447
448 FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
449 FOP_END;
450
451 /*
452 * XXX: inoutclob user must know where the argument is being expanded.
453 * Relying on CC_HAVE_ASM_GOTO would allow us to remove _fault.
454 */
455 #define asm_safe(insn, inoutclob...) \
456 ({ \
457 int _fault = 0; \
458 \
459 asm volatile("1:" insn "\n" \
460 "2:\n" \
461 ".pushsection .fixup, \"ax\"\n" \
462 "3: movl $1, %[_fault]\n" \
463 " jmp 2b\n" \
464 ".popsection\n" \
465 _ASM_EXTABLE(1b, 3b) \
466 : [_fault] "+qm"(_fault) inoutclob ); \
467 \
468 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \
469 })
470
emulator_check_intercept(struct x86_emulate_ctxt * ctxt,enum x86_intercept intercept,enum x86_intercept_stage stage)471 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
472 enum x86_intercept intercept,
473 enum x86_intercept_stage stage)
474 {
475 struct x86_instruction_info info = {
476 .intercept = intercept,
477 .rep_prefix = ctxt->rep_prefix,
478 .modrm_mod = ctxt->modrm_mod,
479 .modrm_reg = ctxt->modrm_reg,
480 .modrm_rm = ctxt->modrm_rm,
481 .src_val = ctxt->src.val64,
482 .dst_val = ctxt->dst.val64,
483 .src_bytes = ctxt->src.bytes,
484 .dst_bytes = ctxt->dst.bytes,
485 .ad_bytes = ctxt->ad_bytes,
486 .next_rip = ctxt->eip,
487 };
488
489 return ctxt->ops->intercept(ctxt, &info, stage);
490 }
491
assign_masked(ulong * dest,ulong src,ulong mask)492 static void assign_masked(ulong *dest, ulong src, ulong mask)
493 {
494 *dest = (*dest & ~mask) | (src & mask);
495 }
496
assign_register(unsigned long * reg,u64 val,int bytes)497 static void assign_register(unsigned long *reg, u64 val, int bytes)
498 {
499 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
500 switch (bytes) {
501 case 1:
502 *(u8 *)reg = (u8)val;
503 break;
504 case 2:
505 *(u16 *)reg = (u16)val;
506 break;
507 case 4:
508 *reg = (u32)val;
509 break; /* 64b: zero-extend */
510 case 8:
511 *reg = val;
512 break;
513 }
514 }
515
ad_mask(struct x86_emulate_ctxt * ctxt)516 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
517 {
518 return (1UL << (ctxt->ad_bytes << 3)) - 1;
519 }
520
stack_mask(struct x86_emulate_ctxt * ctxt)521 static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
522 {
523 u16 sel;
524 struct desc_struct ss;
525
526 if (ctxt->mode == X86EMUL_MODE_PROT64)
527 return ~0UL;
528 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
529 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
530 }
531
stack_size(struct x86_emulate_ctxt * ctxt)532 static int stack_size(struct x86_emulate_ctxt *ctxt)
533 {
534 return (__fls(stack_mask(ctxt)) + 1) >> 3;
535 }
536
537 /* Access/update address held in a register, based on addressing mode. */
538 static inline unsigned long
address_mask(struct x86_emulate_ctxt * ctxt,unsigned long reg)539 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
540 {
541 if (ctxt->ad_bytes == sizeof(unsigned long))
542 return reg;
543 else
544 return reg & ad_mask(ctxt);
545 }
546
547 static inline unsigned long
register_address(struct x86_emulate_ctxt * ctxt,int reg)548 register_address(struct x86_emulate_ctxt *ctxt, int reg)
549 {
550 return address_mask(ctxt, reg_read(ctxt, reg));
551 }
552
masked_increment(ulong * reg,ulong mask,int inc)553 static void masked_increment(ulong *reg, ulong mask, int inc)
554 {
555 assign_masked(reg, *reg + inc, mask);
556 }
557
558 static inline void
register_address_increment(struct x86_emulate_ctxt * ctxt,int reg,int inc)559 register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
560 {
561 ulong *preg = reg_rmw(ctxt, reg);
562
563 assign_register(preg, *preg + inc, ctxt->ad_bytes);
564 }
565
rsp_increment(struct x86_emulate_ctxt * ctxt,int inc)566 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
567 {
568 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
569 }
570
desc_limit_scaled(struct desc_struct * desc)571 static u32 desc_limit_scaled(struct desc_struct *desc)
572 {
573 u32 limit = get_desc_limit(desc);
574
575 return desc->g ? (limit << 12) | 0xfff : limit;
576 }
577
seg_base(struct x86_emulate_ctxt * ctxt,int seg)578 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
579 {
580 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
581 return 0;
582
583 return ctxt->ops->get_cached_segment_base(ctxt, seg);
584 }
585
emulate_exception(struct x86_emulate_ctxt * ctxt,int vec,u32 error,bool valid)586 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
587 u32 error, bool valid)
588 {
589 WARN_ON(vec > 0x1f);
590 ctxt->exception.vector = vec;
591 ctxt->exception.error_code = error;
592 ctxt->exception.error_code_valid = valid;
593 return X86EMUL_PROPAGATE_FAULT;
594 }
595
emulate_db(struct x86_emulate_ctxt * ctxt)596 static int emulate_db(struct x86_emulate_ctxt *ctxt)
597 {
598 return emulate_exception(ctxt, DB_VECTOR, 0, false);
599 }
600
emulate_gp(struct x86_emulate_ctxt * ctxt,int err)601 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
602 {
603 return emulate_exception(ctxt, GP_VECTOR, err, true);
604 }
605
emulate_ss(struct x86_emulate_ctxt * ctxt,int err)606 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
607 {
608 return emulate_exception(ctxt, SS_VECTOR, err, true);
609 }
610
emulate_ud(struct x86_emulate_ctxt * ctxt)611 static int emulate_ud(struct x86_emulate_ctxt *ctxt)
612 {
613 return emulate_exception(ctxt, UD_VECTOR, 0, false);
614 }
615
emulate_ts(struct x86_emulate_ctxt * ctxt,int err)616 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
617 {
618 return emulate_exception(ctxt, TS_VECTOR, err, true);
619 }
620
emulate_de(struct x86_emulate_ctxt * ctxt)621 static int emulate_de(struct x86_emulate_ctxt *ctxt)
622 {
623 return emulate_exception(ctxt, DE_VECTOR, 0, false);
624 }
625
emulate_nm(struct x86_emulate_ctxt * ctxt)626 static int emulate_nm(struct x86_emulate_ctxt *ctxt)
627 {
628 return emulate_exception(ctxt, NM_VECTOR, 0, false);
629 }
630
get_segment_selector(struct x86_emulate_ctxt * ctxt,unsigned seg)631 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
632 {
633 u16 selector;
634 struct desc_struct desc;
635
636 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
637 return selector;
638 }
639
set_segment_selector(struct x86_emulate_ctxt * ctxt,u16 selector,unsigned seg)640 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
641 unsigned seg)
642 {
643 u16 dummy;
644 u32 base3;
645 struct desc_struct desc;
646
647 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
648 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
649 }
650
651 /*
652 * x86 defines three classes of vector instructions: explicitly
653 * aligned, explicitly unaligned, and the rest, which change behaviour
654 * depending on whether they're AVX encoded or not.
655 *
656 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
657 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their
658 * 512 bytes of data must be aligned to a 16 byte boundary.
659 */
insn_alignment(struct x86_emulate_ctxt * ctxt,unsigned size)660 static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size)
661 {
662 if (likely(size < 16))
663 return 1;
664
665 if (ctxt->d & Aligned)
666 return size;
667 else if (ctxt->d & Unaligned)
668 return 1;
669 else if (ctxt->d & Avx)
670 return 1;
671 else if (ctxt->d & Aligned16)
672 return 16;
673 else
674 return size;
675 }
676
__linearize(struct x86_emulate_ctxt * ctxt,struct segmented_address addr,unsigned * max_size,unsigned size,bool write,bool fetch,enum x86emul_mode mode,ulong * linear)677 static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
678 struct segmented_address addr,
679 unsigned *max_size, unsigned size,
680 bool write, bool fetch,
681 enum x86emul_mode mode, ulong *linear)
682 {
683 struct desc_struct desc;
684 bool usable;
685 ulong la;
686 u32 lim;
687 u16 sel;
688
689 la = seg_base(ctxt, addr.seg) + addr.ea;
690 *max_size = 0;
691 switch (mode) {
692 case X86EMUL_MODE_PROT64:
693 *linear = la;
694 if (is_noncanonical_address(la))
695 goto bad;
696
697 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
698 if (size > *max_size)
699 goto bad;
700 break;
701 default:
702 *linear = la = (u32)la;
703 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
704 addr.seg);
705 if (!usable)
706 goto bad;
707 /* code segment in protected mode or read-only data segment */
708 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
709 || !(desc.type & 2)) && write)
710 goto bad;
711 /* unreadable code segment */
712 if (!fetch && (desc.type & 8) && !(desc.type & 2))
713 goto bad;
714 lim = desc_limit_scaled(&desc);
715 if (!(desc.type & 8) && (desc.type & 4)) {
716 /* expand-down segment */
717 if (addr.ea <= lim)
718 goto bad;
719 lim = desc.d ? 0xffffffff : 0xffff;
720 }
721 if (addr.ea > lim)
722 goto bad;
723 if (lim == 0xffffffff)
724 *max_size = ~0u;
725 else {
726 *max_size = (u64)lim + 1 - addr.ea;
727 if (size > *max_size)
728 goto bad;
729 }
730 break;
731 }
732 if (la & (insn_alignment(ctxt, size) - 1))
733 return emulate_gp(ctxt, 0);
734 return X86EMUL_CONTINUE;
735 bad:
736 if (addr.seg == VCPU_SREG_SS)
737 return emulate_ss(ctxt, 0);
738 else
739 return emulate_gp(ctxt, 0);
740 }
741
linearize(struct x86_emulate_ctxt * ctxt,struct segmented_address addr,unsigned size,bool write,ulong * linear)742 static int linearize(struct x86_emulate_ctxt *ctxt,
743 struct segmented_address addr,
744 unsigned size, bool write,
745 ulong *linear)
746 {
747 unsigned max_size;
748 return __linearize(ctxt, addr, &max_size, size, write, false,
749 ctxt->mode, linear);
750 }
751
assign_eip(struct x86_emulate_ctxt * ctxt,ulong dst,enum x86emul_mode mode)752 static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
753 enum x86emul_mode mode)
754 {
755 ulong linear;
756 int rc;
757 unsigned max_size;
758 struct segmented_address addr = { .seg = VCPU_SREG_CS,
759 .ea = dst };
760
761 if (ctxt->op_bytes != sizeof(unsigned long))
762 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
763 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
764 if (rc == X86EMUL_CONTINUE)
765 ctxt->_eip = addr.ea;
766 return rc;
767 }
768
assign_eip_near(struct x86_emulate_ctxt * ctxt,ulong dst)769 static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
770 {
771 return assign_eip(ctxt, dst, ctxt->mode);
772 }
773
assign_eip_far(struct x86_emulate_ctxt * ctxt,ulong dst,const struct desc_struct * cs_desc)774 static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
775 const struct desc_struct *cs_desc)
776 {
777 enum x86emul_mode mode = ctxt->mode;
778 int rc;
779
780 #ifdef CONFIG_X86_64
781 if (ctxt->mode >= X86EMUL_MODE_PROT16) {
782 if (cs_desc->l) {
783 u64 efer = 0;
784
785 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
786 if (efer & EFER_LMA)
787 mode = X86EMUL_MODE_PROT64;
788 } else
789 mode = X86EMUL_MODE_PROT32; /* temporary value */
790 }
791 #endif
792 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
793 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
794 rc = assign_eip(ctxt, dst, mode);
795 if (rc == X86EMUL_CONTINUE)
796 ctxt->mode = mode;
797 return rc;
798 }
799
jmp_rel(struct x86_emulate_ctxt * ctxt,int rel)800 static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
801 {
802 return assign_eip_near(ctxt, ctxt->_eip + rel);
803 }
804
segmented_read_std(struct x86_emulate_ctxt * ctxt,struct segmented_address addr,void * data,unsigned size)805 static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
806 struct segmented_address addr,
807 void *data,
808 unsigned size)
809 {
810 int rc;
811 ulong linear;
812
813 rc = linearize(ctxt, addr, size, false, &linear);
814 if (rc != X86EMUL_CONTINUE)
815 return rc;
816 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
817 }
818
segmented_write_std(struct x86_emulate_ctxt * ctxt,struct segmented_address addr,void * data,unsigned int size)819 static int segmented_write_std(struct x86_emulate_ctxt *ctxt,
820 struct segmented_address addr,
821 void *data,
822 unsigned int size)
823 {
824 int rc;
825 ulong linear;
826
827 rc = linearize(ctxt, addr, size, true, &linear);
828 if (rc != X86EMUL_CONTINUE)
829 return rc;
830 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception);
831 }
832
833 /*
834 * Prefetch the remaining bytes of the instruction without crossing page
835 * boundary if they are not in fetch_cache yet.
836 */
__do_insn_fetch_bytes(struct x86_emulate_ctxt * ctxt,int op_size)837 static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
838 {
839 int rc;
840 unsigned size, max_size;
841 unsigned long linear;
842 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
843 struct segmented_address addr = { .seg = VCPU_SREG_CS,
844 .ea = ctxt->eip + cur_size };
845
846 /*
847 * We do not know exactly how many bytes will be needed, and
848 * __linearize is expensive, so fetch as much as possible. We
849 * just have to avoid going beyond the 15 byte limit, the end
850 * of the segment, or the end of the page.
851 *
852 * __linearize is called with size 0 so that it does not do any
853 * boundary check itself. Instead, we use max_size to check
854 * against op_size.
855 */
856 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
857 &linear);
858 if (unlikely(rc != X86EMUL_CONTINUE))
859 return rc;
860
861 size = min_t(unsigned, 15UL ^ cur_size, max_size);
862 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
863
864 /*
865 * One instruction can only straddle two pages,
866 * and one has been loaded at the beginning of
867 * x86_decode_insn. So, if not enough bytes
868 * still, we must have hit the 15-byte boundary.
869 */
870 if (unlikely(size < op_size))
871 return emulate_gp(ctxt, 0);
872
873 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
874 size, &ctxt->exception);
875 if (unlikely(rc != X86EMUL_CONTINUE))
876 return rc;
877 ctxt->fetch.end += size;
878 return X86EMUL_CONTINUE;
879 }
880
do_insn_fetch_bytes(struct x86_emulate_ctxt * ctxt,unsigned size)881 static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
882 unsigned size)
883 {
884 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
885
886 if (unlikely(done_size < size))
887 return __do_insn_fetch_bytes(ctxt, size - done_size);
888 else
889 return X86EMUL_CONTINUE;
890 }
891
892 /* Fetch next part of the instruction being emulated. */
893 #define insn_fetch(_type, _ctxt) \
894 ({ _type _x; \
895 \
896 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
897 if (rc != X86EMUL_CONTINUE) \
898 goto done; \
899 ctxt->_eip += sizeof(_type); \
900 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
901 ctxt->fetch.ptr += sizeof(_type); \
902 _x; \
903 })
904
905 #define insn_fetch_arr(_arr, _size, _ctxt) \
906 ({ \
907 rc = do_insn_fetch_bytes(_ctxt, _size); \
908 if (rc != X86EMUL_CONTINUE) \
909 goto done; \
910 ctxt->_eip += (_size); \
911 memcpy(_arr, ctxt->fetch.ptr, _size); \
912 ctxt->fetch.ptr += (_size); \
913 })
914
915 /*
916 * Given the 'reg' portion of a ModRM byte, and a register block, return a
917 * pointer into the block that addresses the relevant register.
918 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
919 */
decode_register(struct x86_emulate_ctxt * ctxt,u8 modrm_reg,int byteop)920 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
921 int byteop)
922 {
923 void *p;
924 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
925
926 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
927 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
928 else
929 p = reg_rmw(ctxt, modrm_reg);
930 return p;
931 }
932
read_descriptor(struct x86_emulate_ctxt * ctxt,struct segmented_address addr,u16 * size,unsigned long * address,int op_bytes)933 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
934 struct segmented_address addr,
935 u16 *size, unsigned long *address, int op_bytes)
936 {
937 int rc;
938
939 if (op_bytes == 2)
940 op_bytes = 3;
941 *address = 0;
942 rc = segmented_read_std(ctxt, addr, size, 2);
943 if (rc != X86EMUL_CONTINUE)
944 return rc;
945 addr.ea += 2;
946 rc = segmented_read_std(ctxt, addr, address, op_bytes);
947 return rc;
948 }
949
950 FASTOP2(add);
951 FASTOP2(or);
952 FASTOP2(adc);
953 FASTOP2(sbb);
954 FASTOP2(and);
955 FASTOP2(sub);
956 FASTOP2(xor);
957 FASTOP2(cmp);
958 FASTOP2(test);
959
960 FASTOP1SRC2(mul, mul_ex);
961 FASTOP1SRC2(imul, imul_ex);
962 FASTOP1SRC2EX(div, div_ex);
963 FASTOP1SRC2EX(idiv, idiv_ex);
964
965 FASTOP3WCL(shld);
966 FASTOP3WCL(shrd);
967
968 FASTOP2W(imul);
969
970 FASTOP1(not);
971 FASTOP1(neg);
972 FASTOP1(inc);
973 FASTOP1(dec);
974
975 FASTOP2CL(rol);
976 FASTOP2CL(ror);
977 FASTOP2CL(rcl);
978 FASTOP2CL(rcr);
979 FASTOP2CL(shl);
980 FASTOP2CL(shr);
981 FASTOP2CL(sar);
982
983 FASTOP2W(bsf);
984 FASTOP2W(bsr);
985 FASTOP2W(bt);
986 FASTOP2W(bts);
987 FASTOP2W(btr);
988 FASTOP2W(btc);
989
990 FASTOP2(xadd);
991
992 FASTOP2R(cmp, cmp_r);
993
em_bsf_c(struct x86_emulate_ctxt * ctxt)994 static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
995 {
996 /* If src is zero, do not writeback, but update flags */
997 if (ctxt->src.val == 0)
998 ctxt->dst.type = OP_NONE;
999 return fastop(ctxt, em_bsf);
1000 }
1001
em_bsr_c(struct x86_emulate_ctxt * ctxt)1002 static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
1003 {
1004 /* If src is zero, do not writeback, but update flags */
1005 if (ctxt->src.val == 0)
1006 ctxt->dst.type = OP_NONE;
1007 return fastop(ctxt, em_bsr);
1008 }
1009
test_cc(unsigned int condition,unsigned long flags)1010 static __always_inline u8 test_cc(unsigned int condition, unsigned long flags)
1011 {
1012 u8 rc;
1013 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
1014
1015 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
1016 asm("push %[flags]; popf; " CALL_NOSPEC
1017 : "=a"(rc) : [thunk_target]"r"(fop), [flags]"r"(flags));
1018 return rc;
1019 }
1020
fetch_register_operand(struct operand * op)1021 static void fetch_register_operand(struct operand *op)
1022 {
1023 switch (op->bytes) {
1024 case 1:
1025 op->val = *(u8 *)op->addr.reg;
1026 break;
1027 case 2:
1028 op->val = *(u16 *)op->addr.reg;
1029 break;
1030 case 4:
1031 op->val = *(u32 *)op->addr.reg;
1032 break;
1033 case 8:
1034 op->val = *(u64 *)op->addr.reg;
1035 break;
1036 }
1037 }
1038
read_sse_reg(struct x86_emulate_ctxt * ctxt,sse128_t * data,int reg)1039 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1040 {
1041 ctxt->ops->get_fpu(ctxt);
1042 switch (reg) {
1043 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1044 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1045 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1046 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1047 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1048 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1049 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1050 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1051 #ifdef CONFIG_X86_64
1052 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1053 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1054 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1055 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1056 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1057 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1058 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1059 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1060 #endif
1061 default: BUG();
1062 }
1063 ctxt->ops->put_fpu(ctxt);
1064 }
1065
write_sse_reg(struct x86_emulate_ctxt * ctxt,sse128_t * data,int reg)1066 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1067 int reg)
1068 {
1069 ctxt->ops->get_fpu(ctxt);
1070 switch (reg) {
1071 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1072 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1073 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1074 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1075 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1076 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1077 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1078 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1079 #ifdef CONFIG_X86_64
1080 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1081 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1082 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1083 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1084 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1085 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1086 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1087 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1088 #endif
1089 default: BUG();
1090 }
1091 ctxt->ops->put_fpu(ctxt);
1092 }
1093
read_mmx_reg(struct x86_emulate_ctxt * ctxt,u64 * data,int reg)1094 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1095 {
1096 ctxt->ops->get_fpu(ctxt);
1097 switch (reg) {
1098 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1099 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1100 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1101 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1102 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1103 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1104 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1105 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1106 default: BUG();
1107 }
1108 ctxt->ops->put_fpu(ctxt);
1109 }
1110
write_mmx_reg(struct x86_emulate_ctxt * ctxt,u64 * data,int reg)1111 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1112 {
1113 ctxt->ops->get_fpu(ctxt);
1114 switch (reg) {
1115 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1116 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1117 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1118 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1119 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1120 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1121 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1122 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1123 default: BUG();
1124 }
1125 ctxt->ops->put_fpu(ctxt);
1126 }
1127
em_fninit(struct x86_emulate_ctxt * ctxt)1128 static int em_fninit(struct x86_emulate_ctxt *ctxt)
1129 {
1130 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1131 return emulate_nm(ctxt);
1132
1133 ctxt->ops->get_fpu(ctxt);
1134 asm volatile("fninit");
1135 ctxt->ops->put_fpu(ctxt);
1136 return X86EMUL_CONTINUE;
1137 }
1138
em_fnstcw(struct x86_emulate_ctxt * ctxt)1139 static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1140 {
1141 u16 fcw;
1142
1143 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1144 return emulate_nm(ctxt);
1145
1146 ctxt->ops->get_fpu(ctxt);
1147 asm volatile("fnstcw %0": "+m"(fcw));
1148 ctxt->ops->put_fpu(ctxt);
1149
1150 ctxt->dst.val = fcw;
1151
1152 return X86EMUL_CONTINUE;
1153 }
1154
em_fnstsw(struct x86_emulate_ctxt * ctxt)1155 static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1156 {
1157 u16 fsw;
1158
1159 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1160 return emulate_nm(ctxt);
1161
1162 ctxt->ops->get_fpu(ctxt);
1163 asm volatile("fnstsw %0": "+m"(fsw));
1164 ctxt->ops->put_fpu(ctxt);
1165
1166 ctxt->dst.val = fsw;
1167
1168 return X86EMUL_CONTINUE;
1169 }
1170
decode_register_operand(struct x86_emulate_ctxt * ctxt,struct operand * op)1171 static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
1172 struct operand *op)
1173 {
1174 unsigned reg = ctxt->modrm_reg;
1175
1176 if (!(ctxt->d & ModRM))
1177 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1178
1179 if (ctxt->d & Sse) {
1180 op->type = OP_XMM;
1181 op->bytes = 16;
1182 op->addr.xmm = reg;
1183 read_sse_reg(ctxt, &op->vec_val, reg);
1184 return;
1185 }
1186 if (ctxt->d & Mmx) {
1187 reg &= 7;
1188 op->type = OP_MM;
1189 op->bytes = 8;
1190 op->addr.mm = reg;
1191 return;
1192 }
1193
1194 op->type = OP_REG;
1195 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1196 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1197
1198 fetch_register_operand(op);
1199 op->orig_val = op->val;
1200 }
1201
adjust_modrm_seg(struct x86_emulate_ctxt * ctxt,int base_reg)1202 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1203 {
1204 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1205 ctxt->modrm_seg = VCPU_SREG_SS;
1206 }
1207
decode_modrm(struct x86_emulate_ctxt * ctxt,struct operand * op)1208 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
1209 struct operand *op)
1210 {
1211 u8 sib;
1212 int index_reg, base_reg, scale;
1213 int rc = X86EMUL_CONTINUE;
1214 ulong modrm_ea = 0;
1215
1216 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1217 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1218 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1219
1220 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
1221 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1222 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
1223 ctxt->modrm_seg = VCPU_SREG_DS;
1224
1225 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
1226 op->type = OP_REG;
1227 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1228 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
1229 ctxt->d & ByteOp);
1230 if (ctxt->d & Sse) {
1231 op->type = OP_XMM;
1232 op->bytes = 16;
1233 op->addr.xmm = ctxt->modrm_rm;
1234 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1235 return rc;
1236 }
1237 if (ctxt->d & Mmx) {
1238 op->type = OP_MM;
1239 op->bytes = 8;
1240 op->addr.mm = ctxt->modrm_rm & 7;
1241 return rc;
1242 }
1243 fetch_register_operand(op);
1244 return rc;
1245 }
1246
1247 op->type = OP_MEM;
1248
1249 if (ctxt->ad_bytes == 2) {
1250 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1251 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1252 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1253 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1254
1255 /* 16-bit ModR/M decode. */
1256 switch (ctxt->modrm_mod) {
1257 case 0:
1258 if (ctxt->modrm_rm == 6)
1259 modrm_ea += insn_fetch(u16, ctxt);
1260 break;
1261 case 1:
1262 modrm_ea += insn_fetch(s8, ctxt);
1263 break;
1264 case 2:
1265 modrm_ea += insn_fetch(u16, ctxt);
1266 break;
1267 }
1268 switch (ctxt->modrm_rm) {
1269 case 0:
1270 modrm_ea += bx + si;
1271 break;
1272 case 1:
1273 modrm_ea += bx + di;
1274 break;
1275 case 2:
1276 modrm_ea += bp + si;
1277 break;
1278 case 3:
1279 modrm_ea += bp + di;
1280 break;
1281 case 4:
1282 modrm_ea += si;
1283 break;
1284 case 5:
1285 modrm_ea += di;
1286 break;
1287 case 6:
1288 if (ctxt->modrm_mod != 0)
1289 modrm_ea += bp;
1290 break;
1291 case 7:
1292 modrm_ea += bx;
1293 break;
1294 }
1295 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1296 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1297 ctxt->modrm_seg = VCPU_SREG_SS;
1298 modrm_ea = (u16)modrm_ea;
1299 } else {
1300 /* 32/64-bit ModR/M decode. */
1301 if ((ctxt->modrm_rm & 7) == 4) {
1302 sib = insn_fetch(u8, ctxt);
1303 index_reg |= (sib >> 3) & 7;
1304 base_reg |= sib & 7;
1305 scale = sib >> 6;
1306
1307 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1308 modrm_ea += insn_fetch(s32, ctxt);
1309 else {
1310 modrm_ea += reg_read(ctxt, base_reg);
1311 adjust_modrm_seg(ctxt, base_reg);
1312 /* Increment ESP on POP [ESP] */
1313 if ((ctxt->d & IncSP) &&
1314 base_reg == VCPU_REGS_RSP)
1315 modrm_ea += ctxt->op_bytes;
1316 }
1317 if (index_reg != 4)
1318 modrm_ea += reg_read(ctxt, index_reg) << scale;
1319 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1320 modrm_ea += insn_fetch(s32, ctxt);
1321 if (ctxt->mode == X86EMUL_MODE_PROT64)
1322 ctxt->rip_relative = 1;
1323 } else {
1324 base_reg = ctxt->modrm_rm;
1325 modrm_ea += reg_read(ctxt, base_reg);
1326 adjust_modrm_seg(ctxt, base_reg);
1327 }
1328 switch (ctxt->modrm_mod) {
1329 case 1:
1330 modrm_ea += insn_fetch(s8, ctxt);
1331 break;
1332 case 2:
1333 modrm_ea += insn_fetch(s32, ctxt);
1334 break;
1335 }
1336 }
1337 op->addr.mem.ea = modrm_ea;
1338 if (ctxt->ad_bytes != 8)
1339 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1340
1341 done:
1342 return rc;
1343 }
1344
decode_abs(struct x86_emulate_ctxt * ctxt,struct operand * op)1345 static int decode_abs(struct x86_emulate_ctxt *ctxt,
1346 struct operand *op)
1347 {
1348 int rc = X86EMUL_CONTINUE;
1349
1350 op->type = OP_MEM;
1351 switch (ctxt->ad_bytes) {
1352 case 2:
1353 op->addr.mem.ea = insn_fetch(u16, ctxt);
1354 break;
1355 case 4:
1356 op->addr.mem.ea = insn_fetch(u32, ctxt);
1357 break;
1358 case 8:
1359 op->addr.mem.ea = insn_fetch(u64, ctxt);
1360 break;
1361 }
1362 done:
1363 return rc;
1364 }
1365
fetch_bit_operand(struct x86_emulate_ctxt * ctxt)1366 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1367 {
1368 long sv = 0, mask;
1369
1370 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1371 mask = ~((long)ctxt->dst.bytes * 8 - 1);
1372
1373 if (ctxt->src.bytes == 2)
1374 sv = (s16)ctxt->src.val & (s16)mask;
1375 else if (ctxt->src.bytes == 4)
1376 sv = (s32)ctxt->src.val & (s32)mask;
1377 else
1378 sv = (s64)ctxt->src.val & (s64)mask;
1379
1380 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1381 ctxt->dst.addr.mem.ea + (sv >> 3));
1382 }
1383
1384 /* only subword offset */
1385 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1386 }
1387
read_emulated(struct x86_emulate_ctxt * ctxt,unsigned long addr,void * dest,unsigned size)1388 static int read_emulated(struct x86_emulate_ctxt *ctxt,
1389 unsigned long addr, void *dest, unsigned size)
1390 {
1391 int rc;
1392 struct read_cache *mc = &ctxt->mem_read;
1393
1394 if (mc->pos < mc->end)
1395 goto read_cached;
1396
1397 WARN_ON((mc->end + size) >= sizeof(mc->data));
1398
1399 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1400 &ctxt->exception);
1401 if (rc != X86EMUL_CONTINUE)
1402 return rc;
1403
1404 mc->end += size;
1405
1406 read_cached:
1407 memcpy(dest, mc->data + mc->pos, size);
1408 mc->pos += size;
1409 return X86EMUL_CONTINUE;
1410 }
1411
segmented_read(struct x86_emulate_ctxt * ctxt,struct segmented_address addr,void * data,unsigned size)1412 static int segmented_read(struct x86_emulate_ctxt *ctxt,
1413 struct segmented_address addr,
1414 void *data,
1415 unsigned size)
1416 {
1417 int rc;
1418 ulong linear;
1419
1420 rc = linearize(ctxt, addr, size, false, &linear);
1421 if (rc != X86EMUL_CONTINUE)
1422 return rc;
1423 return read_emulated(ctxt, linear, data, size);
1424 }
1425
segmented_write(struct x86_emulate_ctxt * ctxt,struct segmented_address addr,const void * data,unsigned size)1426 static int segmented_write(struct x86_emulate_ctxt *ctxt,
1427 struct segmented_address addr,
1428 const void *data,
1429 unsigned size)
1430 {
1431 int rc;
1432 ulong linear;
1433
1434 rc = linearize(ctxt, addr, size, true, &linear);
1435 if (rc != X86EMUL_CONTINUE)
1436 return rc;
1437 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1438 &ctxt->exception);
1439 }
1440
segmented_cmpxchg(struct x86_emulate_ctxt * ctxt,struct segmented_address addr,const void * orig_data,const void * data,unsigned size)1441 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1442 struct segmented_address addr,
1443 const void *orig_data, const void *data,
1444 unsigned size)
1445 {
1446 int rc;
1447 ulong linear;
1448
1449 rc = linearize(ctxt, addr, size, true, &linear);
1450 if (rc != X86EMUL_CONTINUE)
1451 return rc;
1452 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1453 size, &ctxt->exception);
1454 }
1455
pio_in_emulated(struct x86_emulate_ctxt * ctxt,unsigned int size,unsigned short port,void * dest)1456 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1457 unsigned int size, unsigned short port,
1458 void *dest)
1459 {
1460 struct read_cache *rc = &ctxt->io_read;
1461
1462 if (rc->pos == rc->end) { /* refill pio read ahead */
1463 unsigned int in_page, n;
1464 unsigned int count = ctxt->rep_prefix ?
1465 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
1466 in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
1467 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1468 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
1469 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
1470 if (n == 0)
1471 n = 1;
1472 rc->pos = rc->end = 0;
1473 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1474 return 0;
1475 rc->end = n * size;
1476 }
1477
1478 if (ctxt->rep_prefix && (ctxt->d & String) &&
1479 !(ctxt->eflags & X86_EFLAGS_DF)) {
1480 ctxt->dst.data = rc->data + rc->pos;
1481 ctxt->dst.type = OP_MEM_STR;
1482 ctxt->dst.count = (rc->end - rc->pos) / size;
1483 rc->pos = rc->end;
1484 } else {
1485 memcpy(dest, rc->data + rc->pos, size);
1486 rc->pos += size;
1487 }
1488 return 1;
1489 }
1490
read_interrupt_descriptor(struct x86_emulate_ctxt * ctxt,u16 index,struct desc_struct * desc)1491 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1492 u16 index, struct desc_struct *desc)
1493 {
1494 struct desc_ptr dt;
1495 ulong addr;
1496
1497 ctxt->ops->get_idt(ctxt, &dt);
1498
1499 if (dt.size < index * 8 + 7)
1500 return emulate_gp(ctxt, index << 3 | 0x2);
1501
1502 addr = dt.address + index * 8;
1503 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1504 &ctxt->exception);
1505 }
1506
get_descriptor_table_ptr(struct x86_emulate_ctxt * ctxt,u16 selector,struct desc_ptr * dt)1507 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1508 u16 selector, struct desc_ptr *dt)
1509 {
1510 const struct x86_emulate_ops *ops = ctxt->ops;
1511 u32 base3 = 0;
1512
1513 if (selector & 1 << 2) {
1514 struct desc_struct desc;
1515 u16 sel;
1516
1517 memset (dt, 0, sizeof *dt);
1518 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1519 VCPU_SREG_LDTR))
1520 return;
1521
1522 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1523 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
1524 } else
1525 ops->get_gdt(ctxt, dt);
1526 }
1527
get_descriptor_ptr(struct x86_emulate_ctxt * ctxt,u16 selector,ulong * desc_addr_p)1528 static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1529 u16 selector, ulong *desc_addr_p)
1530 {
1531 struct desc_ptr dt;
1532 u16 index = selector >> 3;
1533 ulong addr;
1534
1535 get_descriptor_table_ptr(ctxt, selector, &dt);
1536
1537 if (dt.size < index * 8 + 7)
1538 return emulate_gp(ctxt, selector & 0xfffc);
1539
1540 addr = dt.address + index * 8;
1541
1542 #ifdef CONFIG_X86_64
1543 if (addr >> 32 != 0) {
1544 u64 efer = 0;
1545
1546 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1547 if (!(efer & EFER_LMA))
1548 addr &= (u32)-1;
1549 }
1550 #endif
1551
1552 *desc_addr_p = addr;
1553 return X86EMUL_CONTINUE;
1554 }
1555
1556 /* allowed just for 8 bytes segments */
read_segment_descriptor(struct x86_emulate_ctxt * ctxt,u16 selector,struct desc_struct * desc,ulong * desc_addr_p)1557 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1558 u16 selector, struct desc_struct *desc,
1559 ulong *desc_addr_p)
1560 {
1561 int rc;
1562
1563 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1564 if (rc != X86EMUL_CONTINUE)
1565 return rc;
1566
1567 return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
1568 &ctxt->exception);
1569 }
1570
1571 /* allowed just for 8 bytes segments */
write_segment_descriptor(struct x86_emulate_ctxt * ctxt,u16 selector,struct desc_struct * desc)1572 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1573 u16 selector, struct desc_struct *desc)
1574 {
1575 int rc;
1576 ulong addr;
1577
1578 rc = get_descriptor_ptr(ctxt, selector, &addr);
1579 if (rc != X86EMUL_CONTINUE)
1580 return rc;
1581
1582 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1583 &ctxt->exception);
1584 }
1585
__load_segment_descriptor(struct x86_emulate_ctxt * ctxt,u16 selector,int seg,u8 cpl,enum x86_transfer_type transfer,struct desc_struct * desc)1586 static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1587 u16 selector, int seg, u8 cpl,
1588 enum x86_transfer_type transfer,
1589 struct desc_struct *desc)
1590 {
1591 struct desc_struct seg_desc, old_desc;
1592 u8 dpl, rpl;
1593 unsigned err_vec = GP_VECTOR;
1594 u32 err_code = 0;
1595 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1596 ulong desc_addr;
1597 int ret;
1598 u16 dummy;
1599 u32 base3 = 0;
1600
1601 memset(&seg_desc, 0, sizeof seg_desc);
1602
1603 if (ctxt->mode == X86EMUL_MODE_REAL) {
1604 /* set real mode segment descriptor (keep limit etc. for
1605 * unreal mode) */
1606 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
1607 set_desc_base(&seg_desc, selector << 4);
1608 goto load;
1609 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1610 /* VM86 needs a clean new segment descriptor */
1611 set_desc_base(&seg_desc, selector << 4);
1612 set_desc_limit(&seg_desc, 0xffff);
1613 seg_desc.type = 3;
1614 seg_desc.p = 1;
1615 seg_desc.s = 1;
1616 seg_desc.dpl = 3;
1617 goto load;
1618 }
1619
1620 rpl = selector & 3;
1621
1622 /* TR should be in GDT only */
1623 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1624 goto exception;
1625
1626 /* NULL selector is not valid for TR, CS and (except for long mode) SS */
1627 if (null_selector) {
1628 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR)
1629 goto exception;
1630
1631 if (seg == VCPU_SREG_SS) {
1632 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)
1633 goto exception;
1634
1635 /*
1636 * ctxt->ops->set_segment expects the CPL to be in
1637 * SS.DPL, so fake an expand-up 32-bit data segment.
1638 */
1639 seg_desc.type = 3;
1640 seg_desc.p = 1;
1641 seg_desc.s = 1;
1642 seg_desc.dpl = cpl;
1643 seg_desc.d = 1;
1644 seg_desc.g = 1;
1645 }
1646
1647 /* Skip all following checks */
1648 goto load;
1649 }
1650
1651 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
1652 if (ret != X86EMUL_CONTINUE)
1653 return ret;
1654
1655 err_code = selector & 0xfffc;
1656 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1657 GP_VECTOR;
1658
1659 /* can't load system descriptor into segment selector */
1660 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1661 if (transfer == X86_TRANSFER_CALL_JMP)
1662 return X86EMUL_UNHANDLEABLE;
1663 goto exception;
1664 }
1665
1666 if (!seg_desc.p) {
1667 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1668 goto exception;
1669 }
1670
1671 dpl = seg_desc.dpl;
1672
1673 switch (seg) {
1674 case VCPU_SREG_SS:
1675 /*
1676 * segment is not a writable data segment or segment
1677 * selector's RPL != CPL or segment selector's RPL != CPL
1678 */
1679 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1680 goto exception;
1681 break;
1682 case VCPU_SREG_CS:
1683 if (!(seg_desc.type & 8))
1684 goto exception;
1685
1686 if (seg_desc.type & 4) {
1687 /* conforming */
1688 if (dpl > cpl)
1689 goto exception;
1690 } else {
1691 /* nonconforming */
1692 if (rpl > cpl || dpl != cpl)
1693 goto exception;
1694 }
1695 /* in long-mode d/b must be clear if l is set */
1696 if (seg_desc.d && seg_desc.l) {
1697 u64 efer = 0;
1698
1699 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1700 if (efer & EFER_LMA)
1701 goto exception;
1702 }
1703
1704 /* CS(RPL) <- CPL */
1705 selector = (selector & 0xfffc) | cpl;
1706 break;
1707 case VCPU_SREG_TR:
1708 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1709 goto exception;
1710 old_desc = seg_desc;
1711 seg_desc.type |= 2; /* busy */
1712 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1713 sizeof(seg_desc), &ctxt->exception);
1714 if (ret != X86EMUL_CONTINUE)
1715 return ret;
1716 break;
1717 case VCPU_SREG_LDTR:
1718 if (seg_desc.s || seg_desc.type != 2)
1719 goto exception;
1720 break;
1721 default: /* DS, ES, FS, or GS */
1722 /*
1723 * segment is not a data or readable code segment or
1724 * ((segment is a data or nonconforming code segment)
1725 * and (both RPL and CPL > DPL))
1726 */
1727 if ((seg_desc.type & 0xa) == 0x8 ||
1728 (((seg_desc.type & 0xc) != 0xc) &&
1729 (rpl > dpl && cpl > dpl)))
1730 goto exception;
1731 break;
1732 }
1733
1734 if (seg_desc.s) {
1735 /* mark segment as accessed */
1736 if (!(seg_desc.type & 1)) {
1737 seg_desc.type |= 1;
1738 ret = write_segment_descriptor(ctxt, selector,
1739 &seg_desc);
1740 if (ret != X86EMUL_CONTINUE)
1741 return ret;
1742 }
1743 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1744 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1745 sizeof(base3), &ctxt->exception);
1746 if (ret != X86EMUL_CONTINUE)
1747 return ret;
1748 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1749 ((u64)base3 << 32)))
1750 return emulate_gp(ctxt, 0);
1751 }
1752 load:
1753 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
1754 if (desc)
1755 *desc = seg_desc;
1756 return X86EMUL_CONTINUE;
1757 exception:
1758 return emulate_exception(ctxt, err_vec, err_code, true);
1759 }
1760
load_segment_descriptor(struct x86_emulate_ctxt * ctxt,u16 selector,int seg)1761 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1762 u16 selector, int seg)
1763 {
1764 u8 cpl = ctxt->ops->cpl(ctxt);
1765
1766 /*
1767 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but
1768 * they can load it at CPL<3 (Intel's manual says only LSS can,
1769 * but it's wrong).
1770 *
1771 * However, the Intel manual says that putting IST=1/DPL=3 in
1772 * an interrupt gate will result in SS=3 (the AMD manual instead
1773 * says it doesn't), so allow SS=3 in __load_segment_descriptor
1774 * and only forbid it here.
1775 */
1776 if (seg == VCPU_SREG_SS && selector == 3 &&
1777 ctxt->mode == X86EMUL_MODE_PROT64)
1778 return emulate_exception(ctxt, GP_VECTOR, 0, true);
1779
1780 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1781 X86_TRANSFER_NONE, NULL);
1782 }
1783
write_register_operand(struct operand * op)1784 static void write_register_operand(struct operand *op)
1785 {
1786 return assign_register(op->addr.reg, op->val, op->bytes);
1787 }
1788
writeback(struct x86_emulate_ctxt * ctxt,struct operand * op)1789 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
1790 {
1791 switch (op->type) {
1792 case OP_REG:
1793 write_register_operand(op);
1794 break;
1795 case OP_MEM:
1796 if (ctxt->lock_prefix)
1797 return segmented_cmpxchg(ctxt,
1798 op->addr.mem,
1799 &op->orig_val,
1800 &op->val,
1801 op->bytes);
1802 else
1803 return segmented_write(ctxt,
1804 op->addr.mem,
1805 &op->val,
1806 op->bytes);
1807 break;
1808 case OP_MEM_STR:
1809 return segmented_write(ctxt,
1810 op->addr.mem,
1811 op->data,
1812 op->bytes * op->count);
1813 break;
1814 case OP_XMM:
1815 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1816 break;
1817 case OP_MM:
1818 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
1819 break;
1820 case OP_NONE:
1821 /* no writeback */
1822 break;
1823 default:
1824 break;
1825 }
1826 return X86EMUL_CONTINUE;
1827 }
1828
push(struct x86_emulate_ctxt * ctxt,void * data,int bytes)1829 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
1830 {
1831 struct segmented_address addr;
1832
1833 rsp_increment(ctxt, -bytes);
1834 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1835 addr.seg = VCPU_SREG_SS;
1836
1837 return segmented_write(ctxt, addr, data, bytes);
1838 }
1839
em_push(struct x86_emulate_ctxt * ctxt)1840 static int em_push(struct x86_emulate_ctxt *ctxt)
1841 {
1842 /* Disable writeback. */
1843 ctxt->dst.type = OP_NONE;
1844 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
1845 }
1846
emulate_pop(struct x86_emulate_ctxt * ctxt,void * dest,int len)1847 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1848 void *dest, int len)
1849 {
1850 int rc;
1851 struct segmented_address addr;
1852
1853 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1854 addr.seg = VCPU_SREG_SS;
1855 rc = segmented_read(ctxt, addr, dest, len);
1856 if (rc != X86EMUL_CONTINUE)
1857 return rc;
1858
1859 rsp_increment(ctxt, len);
1860 return rc;
1861 }
1862
em_pop(struct x86_emulate_ctxt * ctxt)1863 static int em_pop(struct x86_emulate_ctxt *ctxt)
1864 {
1865 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1866 }
1867
emulate_popf(struct x86_emulate_ctxt * ctxt,void * dest,int len)1868 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1869 void *dest, int len)
1870 {
1871 int rc;
1872 unsigned long val, change_mask;
1873 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
1874 int cpl = ctxt->ops->cpl(ctxt);
1875
1876 rc = emulate_pop(ctxt, &val, len);
1877 if (rc != X86EMUL_CONTINUE)
1878 return rc;
1879
1880 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
1881 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
1882 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
1883 X86_EFLAGS_AC | X86_EFLAGS_ID;
1884
1885 switch(ctxt->mode) {
1886 case X86EMUL_MODE_PROT64:
1887 case X86EMUL_MODE_PROT32:
1888 case X86EMUL_MODE_PROT16:
1889 if (cpl == 0)
1890 change_mask |= X86_EFLAGS_IOPL;
1891 if (cpl <= iopl)
1892 change_mask |= X86_EFLAGS_IF;
1893 break;
1894 case X86EMUL_MODE_VM86:
1895 if (iopl < 3)
1896 return emulate_gp(ctxt, 0);
1897 change_mask |= X86_EFLAGS_IF;
1898 break;
1899 default: /* real mode */
1900 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
1901 break;
1902 }
1903
1904 *(unsigned long *)dest =
1905 (ctxt->eflags & ~change_mask) | (val & change_mask);
1906
1907 return rc;
1908 }
1909
em_popf(struct x86_emulate_ctxt * ctxt)1910 static int em_popf(struct x86_emulate_ctxt *ctxt)
1911 {
1912 ctxt->dst.type = OP_REG;
1913 ctxt->dst.addr.reg = &ctxt->eflags;
1914 ctxt->dst.bytes = ctxt->op_bytes;
1915 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1916 }
1917
em_enter(struct x86_emulate_ctxt * ctxt)1918 static int em_enter(struct x86_emulate_ctxt *ctxt)
1919 {
1920 int rc;
1921 unsigned frame_size = ctxt->src.val;
1922 unsigned nesting_level = ctxt->src2.val & 31;
1923 ulong rbp;
1924
1925 if (nesting_level)
1926 return X86EMUL_UNHANDLEABLE;
1927
1928 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1929 rc = push(ctxt, &rbp, stack_size(ctxt));
1930 if (rc != X86EMUL_CONTINUE)
1931 return rc;
1932 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
1933 stack_mask(ctxt));
1934 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1935 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
1936 stack_mask(ctxt));
1937 return X86EMUL_CONTINUE;
1938 }
1939
em_leave(struct x86_emulate_ctxt * ctxt)1940 static int em_leave(struct x86_emulate_ctxt *ctxt)
1941 {
1942 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
1943 stack_mask(ctxt));
1944 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
1945 }
1946
em_push_sreg(struct x86_emulate_ctxt * ctxt)1947 static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1948 {
1949 int seg = ctxt->src2.val;
1950
1951 ctxt->src.val = get_segment_selector(ctxt, seg);
1952 if (ctxt->op_bytes == 4) {
1953 rsp_increment(ctxt, -2);
1954 ctxt->op_bytes = 2;
1955 }
1956
1957 return em_push(ctxt);
1958 }
1959
em_pop_sreg(struct x86_emulate_ctxt * ctxt)1960 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1961 {
1962 int seg = ctxt->src2.val;
1963 unsigned long selector;
1964 int rc;
1965
1966 rc = emulate_pop(ctxt, &selector, 2);
1967 if (rc != X86EMUL_CONTINUE)
1968 return rc;
1969
1970 if (ctxt->modrm_reg == VCPU_SREG_SS)
1971 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1972 if (ctxt->op_bytes > 2)
1973 rsp_increment(ctxt, ctxt->op_bytes - 2);
1974
1975 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1976 return rc;
1977 }
1978
em_pusha(struct x86_emulate_ctxt * ctxt)1979 static int em_pusha(struct x86_emulate_ctxt *ctxt)
1980 {
1981 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
1982 int rc = X86EMUL_CONTINUE;
1983 int reg = VCPU_REGS_RAX;
1984
1985 while (reg <= VCPU_REGS_RDI) {
1986 (reg == VCPU_REGS_RSP) ?
1987 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
1988
1989 rc = em_push(ctxt);
1990 if (rc != X86EMUL_CONTINUE)
1991 return rc;
1992
1993 ++reg;
1994 }
1995
1996 return rc;
1997 }
1998
em_pushf(struct x86_emulate_ctxt * ctxt)1999 static int em_pushf(struct x86_emulate_ctxt *ctxt)
2000 {
2001 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
2002 return em_push(ctxt);
2003 }
2004
em_popa(struct x86_emulate_ctxt * ctxt)2005 static int em_popa(struct x86_emulate_ctxt *ctxt)
2006 {
2007 int rc = X86EMUL_CONTINUE;
2008 int reg = VCPU_REGS_RDI;
2009 u32 val;
2010
2011 while (reg >= VCPU_REGS_RAX) {
2012 if (reg == VCPU_REGS_RSP) {
2013 rsp_increment(ctxt, ctxt->op_bytes);
2014 --reg;
2015 }
2016
2017 rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
2018 if (rc != X86EMUL_CONTINUE)
2019 break;
2020 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
2021 --reg;
2022 }
2023 return rc;
2024 }
2025
__emulate_int_real(struct x86_emulate_ctxt * ctxt,int irq)2026 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2027 {
2028 const struct x86_emulate_ops *ops = ctxt->ops;
2029 int rc;
2030 struct desc_ptr dt;
2031 gva_t cs_addr;
2032 gva_t eip_addr;
2033 u16 cs, eip;
2034
2035 /* TODO: Add limit checks */
2036 ctxt->src.val = ctxt->eflags;
2037 rc = em_push(ctxt);
2038 if (rc != X86EMUL_CONTINUE)
2039 return rc;
2040
2041 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
2042
2043 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
2044 rc = em_push(ctxt);
2045 if (rc != X86EMUL_CONTINUE)
2046 return rc;
2047
2048 ctxt->src.val = ctxt->_eip;
2049 rc = em_push(ctxt);
2050 if (rc != X86EMUL_CONTINUE)
2051 return rc;
2052
2053 ops->get_idt(ctxt, &dt);
2054
2055 eip_addr = dt.address + (irq << 2);
2056 cs_addr = dt.address + (irq << 2) + 2;
2057
2058 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
2059 if (rc != X86EMUL_CONTINUE)
2060 return rc;
2061
2062 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
2063 if (rc != X86EMUL_CONTINUE)
2064 return rc;
2065
2066 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
2067 if (rc != X86EMUL_CONTINUE)
2068 return rc;
2069
2070 ctxt->_eip = eip;
2071
2072 return rc;
2073 }
2074
emulate_int_real(struct x86_emulate_ctxt * ctxt,int irq)2075 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2076 {
2077 int rc;
2078
2079 invalidate_registers(ctxt);
2080 rc = __emulate_int_real(ctxt, irq);
2081 if (rc == X86EMUL_CONTINUE)
2082 writeback_registers(ctxt);
2083 return rc;
2084 }
2085
emulate_int(struct x86_emulate_ctxt * ctxt,int irq)2086 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
2087 {
2088 switch(ctxt->mode) {
2089 case X86EMUL_MODE_REAL:
2090 return __emulate_int_real(ctxt, irq);
2091 case X86EMUL_MODE_VM86:
2092 case X86EMUL_MODE_PROT16:
2093 case X86EMUL_MODE_PROT32:
2094 case X86EMUL_MODE_PROT64:
2095 default:
2096 /* Protected mode interrupts unimplemented yet */
2097 return X86EMUL_UNHANDLEABLE;
2098 }
2099 }
2100
emulate_iret_real(struct x86_emulate_ctxt * ctxt)2101 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
2102 {
2103 int rc = X86EMUL_CONTINUE;
2104 unsigned long temp_eip = 0;
2105 unsigned long temp_eflags = 0;
2106 unsigned long cs = 0;
2107 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
2108 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
2109 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
2110 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
2111 X86_EFLAGS_AC | X86_EFLAGS_ID |
2112 X86_EFLAGS_FIXED;
2113 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
2114 X86_EFLAGS_VIP;
2115
2116 /* TODO: Add stack limit check */
2117
2118 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
2119
2120 if (rc != X86EMUL_CONTINUE)
2121 return rc;
2122
2123 if (temp_eip & ~0xffff)
2124 return emulate_gp(ctxt, 0);
2125
2126 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2127
2128 if (rc != X86EMUL_CONTINUE)
2129 return rc;
2130
2131 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
2132
2133 if (rc != X86EMUL_CONTINUE)
2134 return rc;
2135
2136 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
2137
2138 if (rc != X86EMUL_CONTINUE)
2139 return rc;
2140
2141 ctxt->_eip = temp_eip;
2142
2143 if (ctxt->op_bytes == 4)
2144 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
2145 else if (ctxt->op_bytes == 2) {
2146 ctxt->eflags &= ~0xffff;
2147 ctxt->eflags |= temp_eflags;
2148 }
2149
2150 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2151 ctxt->eflags |= X86_EFLAGS_FIXED;
2152 ctxt->ops->set_nmi_mask(ctxt, false);
2153
2154 return rc;
2155 }
2156
em_iret(struct x86_emulate_ctxt * ctxt)2157 static int em_iret(struct x86_emulate_ctxt *ctxt)
2158 {
2159 switch(ctxt->mode) {
2160 case X86EMUL_MODE_REAL:
2161 return emulate_iret_real(ctxt);
2162 case X86EMUL_MODE_VM86:
2163 case X86EMUL_MODE_PROT16:
2164 case X86EMUL_MODE_PROT32:
2165 case X86EMUL_MODE_PROT64:
2166 default:
2167 /* iret from protected mode unimplemented yet */
2168 return X86EMUL_UNHANDLEABLE;
2169 }
2170 }
2171
em_jmp_far(struct x86_emulate_ctxt * ctxt)2172 static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2173 {
2174 int rc;
2175 unsigned short sel;
2176 struct desc_struct new_desc;
2177 u8 cpl = ctxt->ops->cpl(ctxt);
2178
2179 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2180
2181 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2182 X86_TRANSFER_CALL_JMP,
2183 &new_desc);
2184 if (rc != X86EMUL_CONTINUE)
2185 return rc;
2186
2187 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
2188 /* Error handling is not implemented. */
2189 if (rc != X86EMUL_CONTINUE)
2190 return X86EMUL_UNHANDLEABLE;
2191
2192 return rc;
2193 }
2194
em_jmp_abs(struct x86_emulate_ctxt * ctxt)2195 static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
2196 {
2197 return assign_eip_near(ctxt, ctxt->src.val);
2198 }
2199
em_call_near_abs(struct x86_emulate_ctxt * ctxt)2200 static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2201 {
2202 int rc;
2203 long int old_eip;
2204
2205 old_eip = ctxt->_eip;
2206 rc = assign_eip_near(ctxt, ctxt->src.val);
2207 if (rc != X86EMUL_CONTINUE)
2208 return rc;
2209 ctxt->src.val = old_eip;
2210 rc = em_push(ctxt);
2211 return rc;
2212 }
2213
em_cmpxchg8b(struct x86_emulate_ctxt * ctxt)2214 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
2215 {
2216 u64 old = ctxt->dst.orig_val64;
2217
2218 if (ctxt->dst.bytes == 16)
2219 return X86EMUL_UNHANDLEABLE;
2220
2221 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2222 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2223 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2224 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
2225 ctxt->eflags &= ~X86_EFLAGS_ZF;
2226 } else {
2227 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2228 (u32) reg_read(ctxt, VCPU_REGS_RBX);
2229
2230 ctxt->eflags |= X86_EFLAGS_ZF;
2231 }
2232 return X86EMUL_CONTINUE;
2233 }
2234
em_ret(struct x86_emulate_ctxt * ctxt)2235 static int em_ret(struct x86_emulate_ctxt *ctxt)
2236 {
2237 int rc;
2238 unsigned long eip;
2239
2240 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2241 if (rc != X86EMUL_CONTINUE)
2242 return rc;
2243
2244 return assign_eip_near(ctxt, eip);
2245 }
2246
em_ret_far(struct x86_emulate_ctxt * ctxt)2247 static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2248 {
2249 int rc;
2250 unsigned long eip, cs;
2251 int cpl = ctxt->ops->cpl(ctxt);
2252 struct desc_struct new_desc;
2253
2254 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2255 if (rc != X86EMUL_CONTINUE)
2256 return rc;
2257 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2258 if (rc != X86EMUL_CONTINUE)
2259 return rc;
2260 /* Outer-privilege level return is not implemented */
2261 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2262 return X86EMUL_UNHANDLEABLE;
2263 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2264 X86_TRANSFER_RET,
2265 &new_desc);
2266 if (rc != X86EMUL_CONTINUE)
2267 return rc;
2268 rc = assign_eip_far(ctxt, eip, &new_desc);
2269 /* Error handling is not implemented. */
2270 if (rc != X86EMUL_CONTINUE)
2271 return X86EMUL_UNHANDLEABLE;
2272
2273 return rc;
2274 }
2275
em_ret_far_imm(struct x86_emulate_ctxt * ctxt)2276 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2277 {
2278 int rc;
2279
2280 rc = em_ret_far(ctxt);
2281 if (rc != X86EMUL_CONTINUE)
2282 return rc;
2283 rsp_increment(ctxt, ctxt->src.val);
2284 return X86EMUL_CONTINUE;
2285 }
2286
em_cmpxchg(struct x86_emulate_ctxt * ctxt)2287 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2288 {
2289 /* Save real source value, then compare EAX against destination. */
2290 ctxt->dst.orig_val = ctxt->dst.val;
2291 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
2292 ctxt->src.orig_val = ctxt->src.val;
2293 ctxt->src.val = ctxt->dst.orig_val;
2294 fastop(ctxt, em_cmp);
2295
2296 if (ctxt->eflags & X86_EFLAGS_ZF) {
2297 /* Success: write back to memory; no update of EAX */
2298 ctxt->src.type = OP_NONE;
2299 ctxt->dst.val = ctxt->src.orig_val;
2300 } else {
2301 /* Failure: write the value we saw to EAX. */
2302 ctxt->src.type = OP_REG;
2303 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2304 ctxt->src.val = ctxt->dst.orig_val;
2305 /* Create write-cycle to dest by writing the same value */
2306 ctxt->dst.val = ctxt->dst.orig_val;
2307 }
2308 return X86EMUL_CONTINUE;
2309 }
2310
em_lseg(struct x86_emulate_ctxt * ctxt)2311 static int em_lseg(struct x86_emulate_ctxt *ctxt)
2312 {
2313 int seg = ctxt->src2.val;
2314 unsigned short sel;
2315 int rc;
2316
2317 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2318
2319 rc = load_segment_descriptor(ctxt, sel, seg);
2320 if (rc != X86EMUL_CONTINUE)
2321 return rc;
2322
2323 ctxt->dst.val = ctxt->src.val;
2324 return rc;
2325 }
2326
emulator_has_longmode(struct x86_emulate_ctxt * ctxt)2327 static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt)
2328 {
2329 u32 eax, ebx, ecx, edx;
2330
2331 eax = 0x80000001;
2332 ecx = 0;
2333 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2334 return edx & bit(X86_FEATURE_LM);
2335 }
2336
2337 #define GET_SMSTATE(type, smbase, offset) \
2338 ({ \
2339 type __val; \
2340 int r = ctxt->ops->read_phys(ctxt, smbase + offset, &__val, \
2341 sizeof(__val)); \
2342 if (r != X86EMUL_CONTINUE) \
2343 return X86EMUL_UNHANDLEABLE; \
2344 __val; \
2345 })
2346
rsm_set_desc_flags(struct desc_struct * desc,u32 flags)2347 static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags)
2348 {
2349 desc->g = (flags >> 23) & 1;
2350 desc->d = (flags >> 22) & 1;
2351 desc->l = (flags >> 21) & 1;
2352 desc->avl = (flags >> 20) & 1;
2353 desc->p = (flags >> 15) & 1;
2354 desc->dpl = (flags >> 13) & 3;
2355 desc->s = (flags >> 12) & 1;
2356 desc->type = (flags >> 8) & 15;
2357 }
2358
rsm_load_seg_32(struct x86_emulate_ctxt * ctxt,u64 smbase,int n)2359 static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
2360 {
2361 struct desc_struct desc;
2362 int offset;
2363 u16 selector;
2364
2365 selector = GET_SMSTATE(u32, smbase, 0x7fa8 + n * 4);
2366
2367 if (n < 3)
2368 offset = 0x7f84 + n * 12;
2369 else
2370 offset = 0x7f2c + (n - 3) * 12;
2371
2372 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8));
2373 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4));
2374 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, offset));
2375 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n);
2376 return X86EMUL_CONTINUE;
2377 }
2378
rsm_load_seg_64(struct x86_emulate_ctxt * ctxt,u64 smbase,int n)2379 static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
2380 {
2381 struct desc_struct desc;
2382 int offset;
2383 u16 selector;
2384 u32 base3;
2385
2386 offset = 0x7e00 + n * 16;
2387
2388 selector = GET_SMSTATE(u16, smbase, offset);
2389 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smbase, offset + 2) << 8);
2390 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4));
2391 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8));
2392 base3 = GET_SMSTATE(u32, smbase, offset + 12);
2393
2394 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n);
2395 return X86EMUL_CONTINUE;
2396 }
2397
rsm_enter_protected_mode(struct x86_emulate_ctxt * ctxt,u64 cr0,u64 cr3,u64 cr4)2398 static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt,
2399 u64 cr0, u64 cr3, u64 cr4)
2400 {
2401 int bad;
2402 u64 pcid;
2403
2404 /* In order to later set CR4.PCIDE, CR3[11:0] must be zero. */
2405 pcid = 0;
2406 if (cr4 & X86_CR4_PCIDE) {
2407 pcid = cr3 & 0xfff;
2408 cr3 &= ~0xfff;
2409 }
2410
2411 bad = ctxt->ops->set_cr(ctxt, 3, cr3);
2412 if (bad)
2413 return X86EMUL_UNHANDLEABLE;
2414
2415 /*
2416 * First enable PAE, long mode needs it before CR0.PG = 1 is set.
2417 * Then enable protected mode. However, PCID cannot be enabled
2418 * if EFER.LMA=0, so set it separately.
2419 */
2420 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2421 if (bad)
2422 return X86EMUL_UNHANDLEABLE;
2423
2424 bad = ctxt->ops->set_cr(ctxt, 0, cr0);
2425 if (bad)
2426 return X86EMUL_UNHANDLEABLE;
2427
2428 if (cr4 & X86_CR4_PCIDE) {
2429 bad = ctxt->ops->set_cr(ctxt, 4, cr4);
2430 if (bad)
2431 return X86EMUL_UNHANDLEABLE;
2432 if (pcid) {
2433 bad = ctxt->ops->set_cr(ctxt, 3, cr3 | pcid);
2434 if (bad)
2435 return X86EMUL_UNHANDLEABLE;
2436 }
2437
2438 }
2439
2440 return X86EMUL_CONTINUE;
2441 }
2442
rsm_load_state_32(struct x86_emulate_ctxt * ctxt,u64 smbase)2443 static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, u64 smbase)
2444 {
2445 struct desc_struct desc;
2446 struct desc_ptr dt;
2447 u16 selector;
2448 u32 val, cr0, cr3, cr4;
2449 int i;
2450
2451 cr0 = GET_SMSTATE(u32, smbase, 0x7ffc);
2452 cr3 = GET_SMSTATE(u32, smbase, 0x7ff8);
2453 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7ff4) | X86_EFLAGS_FIXED;
2454 ctxt->_eip = GET_SMSTATE(u32, smbase, 0x7ff0);
2455
2456 for (i = 0; i < 8; i++)
2457 *reg_write(ctxt, i) = GET_SMSTATE(u32, smbase, 0x7fd0 + i * 4);
2458
2459 val = GET_SMSTATE(u32, smbase, 0x7fcc);
2460 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
2461 val = GET_SMSTATE(u32, smbase, 0x7fc8);
2462 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2463
2464 selector = GET_SMSTATE(u32, smbase, 0x7fc4);
2465 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f64));
2466 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f60));
2467 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f5c));
2468 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR);
2469
2470 selector = GET_SMSTATE(u32, smbase, 0x7fc0);
2471 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f80));
2472 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f7c));
2473 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f78));
2474 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR);
2475
2476 dt.address = GET_SMSTATE(u32, smbase, 0x7f74);
2477 dt.size = GET_SMSTATE(u32, smbase, 0x7f70);
2478 ctxt->ops->set_gdt(ctxt, &dt);
2479
2480 dt.address = GET_SMSTATE(u32, smbase, 0x7f58);
2481 dt.size = GET_SMSTATE(u32, smbase, 0x7f54);
2482 ctxt->ops->set_idt(ctxt, &dt);
2483
2484 for (i = 0; i < 6; i++) {
2485 int r = rsm_load_seg_32(ctxt, smbase, i);
2486 if (r != X86EMUL_CONTINUE)
2487 return r;
2488 }
2489
2490 cr4 = GET_SMSTATE(u32, smbase, 0x7f14);
2491
2492 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7ef8));
2493
2494 return rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
2495 }
2496
rsm_load_state_64(struct x86_emulate_ctxt * ctxt,u64 smbase)2497 static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, u64 smbase)
2498 {
2499 struct desc_struct desc;
2500 struct desc_ptr dt;
2501 u64 val, cr0, cr3, cr4;
2502 u32 base3;
2503 u16 selector;
2504 int i, r;
2505
2506 for (i = 0; i < 16; i++)
2507 *reg_write(ctxt, i) = GET_SMSTATE(u64, smbase, 0x7ff8 - i * 8);
2508
2509 ctxt->_eip = GET_SMSTATE(u64, smbase, 0x7f78);
2510 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7f70) | X86_EFLAGS_FIXED;
2511
2512 val = GET_SMSTATE(u32, smbase, 0x7f68);
2513 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
2514 val = GET_SMSTATE(u32, smbase, 0x7f60);
2515 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2516
2517 cr0 = GET_SMSTATE(u64, smbase, 0x7f58);
2518 cr3 = GET_SMSTATE(u64, smbase, 0x7f50);
2519 cr4 = GET_SMSTATE(u64, smbase, 0x7f48);
2520 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7f00));
2521 val = GET_SMSTATE(u64, smbase, 0x7ed0);
2522 ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA);
2523
2524 selector = GET_SMSTATE(u32, smbase, 0x7e90);
2525 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e92) << 8);
2526 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e94));
2527 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e98));
2528 base3 = GET_SMSTATE(u32, smbase, 0x7e9c);
2529 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR);
2530
2531 dt.size = GET_SMSTATE(u32, smbase, 0x7e84);
2532 dt.address = GET_SMSTATE(u64, smbase, 0x7e88);
2533 ctxt->ops->set_idt(ctxt, &dt);
2534
2535 selector = GET_SMSTATE(u32, smbase, 0x7e70);
2536 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e72) << 8);
2537 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e74));
2538 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e78));
2539 base3 = GET_SMSTATE(u32, smbase, 0x7e7c);
2540 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR);
2541
2542 dt.size = GET_SMSTATE(u32, smbase, 0x7e64);
2543 dt.address = GET_SMSTATE(u64, smbase, 0x7e68);
2544 ctxt->ops->set_gdt(ctxt, &dt);
2545
2546 r = rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
2547 if (r != X86EMUL_CONTINUE)
2548 return r;
2549
2550 for (i = 0; i < 6; i++) {
2551 r = rsm_load_seg_64(ctxt, smbase, i);
2552 if (r != X86EMUL_CONTINUE)
2553 return r;
2554 }
2555
2556 return X86EMUL_CONTINUE;
2557 }
2558
em_rsm(struct x86_emulate_ctxt * ctxt)2559 static int em_rsm(struct x86_emulate_ctxt *ctxt)
2560 {
2561 unsigned long cr0, cr4, efer;
2562 u64 smbase;
2563 int ret;
2564
2565 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0)
2566 return emulate_ud(ctxt);
2567
2568 /*
2569 * Get back to real mode, to prepare a safe state in which to load
2570 * CR0/CR3/CR4/EFER. It's all a bit more complicated if the vCPU
2571 * supports long mode.
2572 */
2573 cr4 = ctxt->ops->get_cr(ctxt, 4);
2574 if (emulator_has_longmode(ctxt)) {
2575 struct desc_struct cs_desc;
2576
2577 /* Zero CR4.PCIDE before CR0.PG. */
2578 if (cr4 & X86_CR4_PCIDE) {
2579 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2580 cr4 &= ~X86_CR4_PCIDE;
2581 }
2582
2583 /* A 32-bit code segment is required to clear EFER.LMA. */
2584 memset(&cs_desc, 0, sizeof(cs_desc));
2585 cs_desc.type = 0xb;
2586 cs_desc.s = cs_desc.g = cs_desc.p = 1;
2587 ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS);
2588 }
2589
2590 /* For the 64-bit case, this will clear EFER.LMA. */
2591 cr0 = ctxt->ops->get_cr(ctxt, 0);
2592 if (cr0 & X86_CR0_PE)
2593 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE));
2594
2595 /* Now clear CR4.PAE (which must be done before clearing EFER.LME). */
2596 if (cr4 & X86_CR4_PAE)
2597 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE);
2598
2599 /* And finally go back to 32-bit mode. */
2600 efer = 0;
2601 ctxt->ops->set_msr(ctxt, MSR_EFER, efer);
2602
2603 smbase = ctxt->ops->get_smbase(ctxt);
2604 if (emulator_has_longmode(ctxt))
2605 ret = rsm_load_state_64(ctxt, smbase + 0x8000);
2606 else
2607 ret = rsm_load_state_32(ctxt, smbase + 0x8000);
2608
2609 if (ret != X86EMUL_CONTINUE) {
2610 /* FIXME: should triple fault */
2611 return X86EMUL_UNHANDLEABLE;
2612 }
2613
2614 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_INSIDE_NMI_MASK) == 0)
2615 ctxt->ops->set_nmi_mask(ctxt, false);
2616
2617 ctxt->ops->set_hflags(ctxt, ctxt->ops->get_hflags(ctxt) &
2618 ~(X86EMUL_SMM_INSIDE_NMI_MASK | X86EMUL_SMM_MASK));
2619 return X86EMUL_CONTINUE;
2620 }
2621
2622 static void
setup_syscalls_segments(struct x86_emulate_ctxt * ctxt,struct desc_struct * cs,struct desc_struct * ss)2623 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2624 struct desc_struct *cs, struct desc_struct *ss)
2625 {
2626 cs->l = 0; /* will be adjusted later */
2627 set_desc_base(cs, 0); /* flat segment */
2628 cs->g = 1; /* 4kb granularity */
2629 set_desc_limit(cs, 0xfffff); /* 4GB limit */
2630 cs->type = 0x0b; /* Read, Execute, Accessed */
2631 cs->s = 1;
2632 cs->dpl = 0; /* will be adjusted later */
2633 cs->p = 1;
2634 cs->d = 1;
2635 cs->avl = 0;
2636
2637 set_desc_base(ss, 0); /* flat segment */
2638 set_desc_limit(ss, 0xfffff); /* 4GB limit */
2639 ss->g = 1; /* 4kb granularity */
2640 ss->s = 1;
2641 ss->type = 0x03; /* Read/Write, Accessed */
2642 ss->d = 1; /* 32bit stack segment */
2643 ss->dpl = 0;
2644 ss->p = 1;
2645 ss->l = 0;
2646 ss->avl = 0;
2647 }
2648
vendor_intel(struct x86_emulate_ctxt * ctxt)2649 static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2650 {
2651 u32 eax, ebx, ecx, edx;
2652
2653 eax = ecx = 0;
2654 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2655 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2656 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2657 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2658 }
2659
em_syscall_is_enabled(struct x86_emulate_ctxt * ctxt)2660 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2661 {
2662 const struct x86_emulate_ops *ops = ctxt->ops;
2663 u32 eax, ebx, ecx, edx;
2664
2665 /*
2666 * syscall should always be enabled in longmode - so only become
2667 * vendor specific (cpuid) if other modes are active...
2668 */
2669 if (ctxt->mode == X86EMUL_MODE_PROT64)
2670 return true;
2671
2672 eax = 0x00000000;
2673 ecx = 0x00000000;
2674 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2675 /*
2676 * Intel ("GenuineIntel")
2677 * remark: Intel CPUs only support "syscall" in 64bit
2678 * longmode. Also an 64bit guest with a
2679 * 32bit compat-app running will #UD !! While this
2680 * behaviour can be fixed (by emulating) into AMD
2681 * response - CPUs of AMD can't behave like Intel.
2682 */
2683 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2684 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2685 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2686 return false;
2687
2688 /* AMD ("AuthenticAMD") */
2689 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2690 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2691 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2692 return true;
2693
2694 /* AMD ("AMDisbetter!") */
2695 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2696 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2697 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2698 return true;
2699
2700 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2701 return false;
2702 }
2703
em_syscall(struct x86_emulate_ctxt * ctxt)2704 static int em_syscall(struct x86_emulate_ctxt *ctxt)
2705 {
2706 const struct x86_emulate_ops *ops = ctxt->ops;
2707 struct desc_struct cs, ss;
2708 u64 msr_data;
2709 u16 cs_sel, ss_sel;
2710 u64 efer = 0;
2711
2712 /* syscall is not available in real mode */
2713 if (ctxt->mode == X86EMUL_MODE_REAL ||
2714 ctxt->mode == X86EMUL_MODE_VM86)
2715 return emulate_ud(ctxt);
2716
2717 if (!(em_syscall_is_enabled(ctxt)))
2718 return emulate_ud(ctxt);
2719
2720 ops->get_msr(ctxt, MSR_EFER, &efer);
2721 setup_syscalls_segments(ctxt, &cs, &ss);
2722
2723 if (!(efer & EFER_SCE))
2724 return emulate_ud(ctxt);
2725
2726 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2727 msr_data >>= 32;
2728 cs_sel = (u16)(msr_data & 0xfffc);
2729 ss_sel = (u16)(msr_data + 8);
2730
2731 if (efer & EFER_LMA) {
2732 cs.d = 0;
2733 cs.l = 1;
2734 }
2735 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2736 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2737
2738 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
2739 if (efer & EFER_LMA) {
2740 #ifdef CONFIG_X86_64
2741 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
2742
2743 ops->get_msr(ctxt,
2744 ctxt->mode == X86EMUL_MODE_PROT64 ?
2745 MSR_LSTAR : MSR_CSTAR, &msr_data);
2746 ctxt->_eip = msr_data;
2747
2748 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2749 ctxt->eflags &= ~msr_data;
2750 ctxt->eflags |= X86_EFLAGS_FIXED;
2751 #endif
2752 } else {
2753 /* legacy mode */
2754 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2755 ctxt->_eip = (u32)msr_data;
2756
2757 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
2758 }
2759
2760 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
2761 return X86EMUL_CONTINUE;
2762 }
2763
em_sysenter(struct x86_emulate_ctxt * ctxt)2764 static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2765 {
2766 const struct x86_emulate_ops *ops = ctxt->ops;
2767 struct desc_struct cs, ss;
2768 u64 msr_data;
2769 u16 cs_sel, ss_sel;
2770 u64 efer = 0;
2771
2772 ops->get_msr(ctxt, MSR_EFER, &efer);
2773 /* inject #GP if in real mode */
2774 if (ctxt->mode == X86EMUL_MODE_REAL)
2775 return emulate_gp(ctxt, 0);
2776
2777 /*
2778 * Not recognized on AMD in compat mode (but is recognized in legacy
2779 * mode).
2780 */
2781 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
2782 && !vendor_intel(ctxt))
2783 return emulate_ud(ctxt);
2784
2785 /* sysenter/sysexit have not been tested in 64bit mode. */
2786 if (ctxt->mode == X86EMUL_MODE_PROT64)
2787 return X86EMUL_UNHANDLEABLE;
2788
2789 setup_syscalls_segments(ctxt, &cs, &ss);
2790
2791 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2792 if ((msr_data & 0xfffc) == 0x0)
2793 return emulate_gp(ctxt, 0);
2794
2795 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
2796 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
2797 ss_sel = cs_sel + 8;
2798 if (efer & EFER_LMA) {
2799 cs.d = 0;
2800 cs.l = 1;
2801 }
2802
2803 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2804 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2805
2806 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2807 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
2808
2809 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2810 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2811 (u32)msr_data;
2812
2813 return X86EMUL_CONTINUE;
2814 }
2815
em_sysexit(struct x86_emulate_ctxt * ctxt)2816 static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2817 {
2818 const struct x86_emulate_ops *ops = ctxt->ops;
2819 struct desc_struct cs, ss;
2820 u64 msr_data, rcx, rdx;
2821 int usermode;
2822 u16 cs_sel = 0, ss_sel = 0;
2823
2824 /* inject #GP if in real mode or Virtual 8086 mode */
2825 if (ctxt->mode == X86EMUL_MODE_REAL ||
2826 ctxt->mode == X86EMUL_MODE_VM86)
2827 return emulate_gp(ctxt, 0);
2828
2829 setup_syscalls_segments(ctxt, &cs, &ss);
2830
2831 if ((ctxt->rex_prefix & 0x8) != 0x0)
2832 usermode = X86EMUL_MODE_PROT64;
2833 else
2834 usermode = X86EMUL_MODE_PROT32;
2835
2836 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2837 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2838
2839 cs.dpl = 3;
2840 ss.dpl = 3;
2841 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2842 switch (usermode) {
2843 case X86EMUL_MODE_PROT32:
2844 cs_sel = (u16)(msr_data + 16);
2845 if ((msr_data & 0xfffc) == 0x0)
2846 return emulate_gp(ctxt, 0);
2847 ss_sel = (u16)(msr_data + 24);
2848 rcx = (u32)rcx;
2849 rdx = (u32)rdx;
2850 break;
2851 case X86EMUL_MODE_PROT64:
2852 cs_sel = (u16)(msr_data + 32);
2853 if (msr_data == 0x0)
2854 return emulate_gp(ctxt, 0);
2855 ss_sel = cs_sel + 8;
2856 cs.d = 0;
2857 cs.l = 1;
2858 if (is_noncanonical_address(rcx) ||
2859 is_noncanonical_address(rdx))
2860 return emulate_gp(ctxt, 0);
2861 break;
2862 }
2863 cs_sel |= SEGMENT_RPL_MASK;
2864 ss_sel |= SEGMENT_RPL_MASK;
2865
2866 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2867 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2868
2869 ctxt->_eip = rdx;
2870 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
2871
2872 return X86EMUL_CONTINUE;
2873 }
2874
emulator_bad_iopl(struct x86_emulate_ctxt * ctxt)2875 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2876 {
2877 int iopl;
2878 if (ctxt->mode == X86EMUL_MODE_REAL)
2879 return false;
2880 if (ctxt->mode == X86EMUL_MODE_VM86)
2881 return true;
2882 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
2883 return ctxt->ops->cpl(ctxt) > iopl;
2884 }
2885
emulator_io_port_access_allowed(struct x86_emulate_ctxt * ctxt,u16 port,u16 len)2886 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2887 u16 port, u16 len)
2888 {
2889 const struct x86_emulate_ops *ops = ctxt->ops;
2890 struct desc_struct tr_seg;
2891 u32 base3;
2892 int r;
2893 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2894 unsigned mask = (1 << len) - 1;
2895 unsigned long base;
2896
2897 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2898 if (!tr_seg.p)
2899 return false;
2900 if (desc_limit_scaled(&tr_seg) < 103)
2901 return false;
2902 base = get_desc_base(&tr_seg);
2903 #ifdef CONFIG_X86_64
2904 base |= ((u64)base3) << 32;
2905 #endif
2906 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2907 if (r != X86EMUL_CONTINUE)
2908 return false;
2909 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2910 return false;
2911 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2912 if (r != X86EMUL_CONTINUE)
2913 return false;
2914 if ((perm >> bit_idx) & mask)
2915 return false;
2916 return true;
2917 }
2918
emulator_io_permited(struct x86_emulate_ctxt * ctxt,u16 port,u16 len)2919 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2920 u16 port, u16 len)
2921 {
2922 if (ctxt->perm_ok)
2923 return true;
2924
2925 if (emulator_bad_iopl(ctxt))
2926 if (!emulator_io_port_access_allowed(ctxt, port, len))
2927 return false;
2928
2929 ctxt->perm_ok = true;
2930
2931 return true;
2932 }
2933
string_registers_quirk(struct x86_emulate_ctxt * ctxt)2934 static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
2935 {
2936 /*
2937 * Intel CPUs mask the counter and pointers in quite strange
2938 * manner when ECX is zero due to REP-string optimizations.
2939 */
2940 #ifdef CONFIG_X86_64
2941 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt))
2942 return;
2943
2944 *reg_write(ctxt, VCPU_REGS_RCX) = 0;
2945
2946 switch (ctxt->b) {
2947 case 0xa4: /* movsb */
2948 case 0xa5: /* movsd/w */
2949 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
2950 /* fall through */
2951 case 0xaa: /* stosb */
2952 case 0xab: /* stosd/w */
2953 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
2954 }
2955 #endif
2956 }
2957
save_state_to_tss16(struct x86_emulate_ctxt * ctxt,struct tss_segment_16 * tss)2958 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2959 struct tss_segment_16 *tss)
2960 {
2961 tss->ip = ctxt->_eip;
2962 tss->flag = ctxt->eflags;
2963 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2964 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2965 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2966 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2967 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2968 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2969 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2970 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
2971
2972 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2973 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2974 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2975 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2976 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2977 }
2978
load_state_from_tss16(struct x86_emulate_ctxt * ctxt,struct tss_segment_16 * tss)2979 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2980 struct tss_segment_16 *tss)
2981 {
2982 int ret;
2983 u8 cpl;
2984
2985 ctxt->_eip = tss->ip;
2986 ctxt->eflags = tss->flag | 2;
2987 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2988 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2989 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2990 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2991 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2992 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2993 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2994 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
2995
2996 /*
2997 * SDM says that segment selectors are loaded before segment
2998 * descriptors
2999 */
3000 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
3001 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3002 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3003 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3004 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
3005
3006 cpl = tss->cs & 3;
3007
3008 /*
3009 * Now load segment descriptors. If fault happens at this stage
3010 * it is handled in a context of new task
3011 */
3012 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3013 X86_TRANSFER_TASK_SWITCH, NULL);
3014 if (ret != X86EMUL_CONTINUE)
3015 return ret;
3016 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3017 X86_TRANSFER_TASK_SWITCH, NULL);
3018 if (ret != X86EMUL_CONTINUE)
3019 return ret;
3020 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3021 X86_TRANSFER_TASK_SWITCH, NULL);
3022 if (ret != X86EMUL_CONTINUE)
3023 return ret;
3024 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3025 X86_TRANSFER_TASK_SWITCH, NULL);
3026 if (ret != X86EMUL_CONTINUE)
3027 return ret;
3028 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3029 X86_TRANSFER_TASK_SWITCH, NULL);
3030 if (ret != X86EMUL_CONTINUE)
3031 return ret;
3032
3033 return X86EMUL_CONTINUE;
3034 }
3035
task_switch_16(struct x86_emulate_ctxt * ctxt,u16 tss_selector,u16 old_tss_sel,ulong old_tss_base,struct desc_struct * new_desc)3036 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
3037 u16 tss_selector, u16 old_tss_sel,
3038 ulong old_tss_base, struct desc_struct *new_desc)
3039 {
3040 const struct x86_emulate_ops *ops = ctxt->ops;
3041 struct tss_segment_16 tss_seg;
3042 int ret;
3043 u32 new_tss_base = get_desc_base(new_desc);
3044
3045 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
3046 &ctxt->exception);
3047 if (ret != X86EMUL_CONTINUE)
3048 return ret;
3049
3050 save_state_to_tss16(ctxt, &tss_seg);
3051
3052 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
3053 &ctxt->exception);
3054 if (ret != X86EMUL_CONTINUE)
3055 return ret;
3056
3057 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
3058 &ctxt->exception);
3059 if (ret != X86EMUL_CONTINUE)
3060 return ret;
3061
3062 if (old_tss_sel != 0xffff) {
3063 tss_seg.prev_task_link = old_tss_sel;
3064
3065 ret = ops->write_std(ctxt, new_tss_base,
3066 &tss_seg.prev_task_link,
3067 sizeof tss_seg.prev_task_link,
3068 &ctxt->exception);
3069 if (ret != X86EMUL_CONTINUE)
3070 return ret;
3071 }
3072
3073 return load_state_from_tss16(ctxt, &tss_seg);
3074 }
3075
save_state_to_tss32(struct x86_emulate_ctxt * ctxt,struct tss_segment_32 * tss)3076 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
3077 struct tss_segment_32 *tss)
3078 {
3079 /* CR3 and ldt selector are not saved intentionally */
3080 tss->eip = ctxt->_eip;
3081 tss->eflags = ctxt->eflags;
3082 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
3083 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
3084 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
3085 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
3086 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
3087 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
3088 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
3089 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
3090
3091 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
3092 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
3093 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
3094 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
3095 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
3096 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
3097 }
3098
load_state_from_tss32(struct x86_emulate_ctxt * ctxt,struct tss_segment_32 * tss)3099 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
3100 struct tss_segment_32 *tss)
3101 {
3102 int ret;
3103 u8 cpl;
3104
3105 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
3106 return emulate_gp(ctxt, 0);
3107 ctxt->_eip = tss->eip;
3108 ctxt->eflags = tss->eflags | 2;
3109
3110 /* General purpose registers */
3111 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
3112 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
3113 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
3114 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
3115 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
3116 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
3117 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
3118 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
3119
3120 /*
3121 * SDM says that segment selectors are loaded before segment
3122 * descriptors. This is important because CPL checks will
3123 * use CS.RPL.
3124 */
3125 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
3126 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3127 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3128 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3129 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
3130 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
3131 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
3132
3133 /*
3134 * If we're switching between Protected Mode and VM86, we need to make
3135 * sure to update the mode before loading the segment descriptors so
3136 * that the selectors are interpreted correctly.
3137 */
3138 if (ctxt->eflags & X86_EFLAGS_VM) {
3139 ctxt->mode = X86EMUL_MODE_VM86;
3140 cpl = 3;
3141 } else {
3142 ctxt->mode = X86EMUL_MODE_PROT32;
3143 cpl = tss->cs & 3;
3144 }
3145
3146 /*
3147 * Now load segment descriptors. If fault happenes at this stage
3148 * it is handled in a context of new task
3149 */
3150 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3151 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
3152 if (ret != X86EMUL_CONTINUE)
3153 return ret;
3154 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3155 X86_TRANSFER_TASK_SWITCH, NULL);
3156 if (ret != X86EMUL_CONTINUE)
3157 return ret;
3158 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3159 X86_TRANSFER_TASK_SWITCH, NULL);
3160 if (ret != X86EMUL_CONTINUE)
3161 return ret;
3162 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3163 X86_TRANSFER_TASK_SWITCH, NULL);
3164 if (ret != X86EMUL_CONTINUE)
3165 return ret;
3166 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3167 X86_TRANSFER_TASK_SWITCH, NULL);
3168 if (ret != X86EMUL_CONTINUE)
3169 return ret;
3170 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3171 X86_TRANSFER_TASK_SWITCH, NULL);
3172 if (ret != X86EMUL_CONTINUE)
3173 return ret;
3174 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3175 X86_TRANSFER_TASK_SWITCH, NULL);
3176
3177 return ret;
3178 }
3179
task_switch_32(struct x86_emulate_ctxt * ctxt,u16 tss_selector,u16 old_tss_sel,ulong old_tss_base,struct desc_struct * new_desc)3180 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
3181 u16 tss_selector, u16 old_tss_sel,
3182 ulong old_tss_base, struct desc_struct *new_desc)
3183 {
3184 const struct x86_emulate_ops *ops = ctxt->ops;
3185 struct tss_segment_32 tss_seg;
3186 int ret;
3187 u32 new_tss_base = get_desc_base(new_desc);
3188 u32 eip_offset = offsetof(struct tss_segment_32, eip);
3189 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
3190
3191 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
3192 &ctxt->exception);
3193 if (ret != X86EMUL_CONTINUE)
3194 return ret;
3195
3196 save_state_to_tss32(ctxt, &tss_seg);
3197
3198 /* Only GP registers and segment selectors are saved */
3199 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
3200 ldt_sel_offset - eip_offset, &ctxt->exception);
3201 if (ret != X86EMUL_CONTINUE)
3202 return ret;
3203
3204 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
3205 &ctxt->exception);
3206 if (ret != X86EMUL_CONTINUE)
3207 return ret;
3208
3209 if (old_tss_sel != 0xffff) {
3210 tss_seg.prev_task_link = old_tss_sel;
3211
3212 ret = ops->write_std(ctxt, new_tss_base,
3213 &tss_seg.prev_task_link,
3214 sizeof tss_seg.prev_task_link,
3215 &ctxt->exception);
3216 if (ret != X86EMUL_CONTINUE)
3217 return ret;
3218 }
3219
3220 return load_state_from_tss32(ctxt, &tss_seg);
3221 }
3222
emulator_do_task_switch(struct x86_emulate_ctxt * ctxt,u16 tss_selector,int idt_index,int reason,bool has_error_code,u32 error_code)3223 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
3224 u16 tss_selector, int idt_index, int reason,
3225 bool has_error_code, u32 error_code)
3226 {
3227 const struct x86_emulate_ops *ops = ctxt->ops;
3228 struct desc_struct curr_tss_desc, next_tss_desc;
3229 int ret;
3230 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
3231 ulong old_tss_base =
3232 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
3233 u32 desc_limit;
3234 ulong desc_addr, dr7;
3235
3236 /* FIXME: old_tss_base == ~0 ? */
3237
3238 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
3239 if (ret != X86EMUL_CONTINUE)
3240 return ret;
3241 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
3242 if (ret != X86EMUL_CONTINUE)
3243 return ret;
3244
3245 /* FIXME: check that next_tss_desc is tss */
3246
3247 /*
3248 * Check privileges. The three cases are task switch caused by...
3249 *
3250 * 1. jmp/call/int to task gate: Check against DPL of the task gate
3251 * 2. Exception/IRQ/iret: No check is performed
3252 * 3. jmp/call to TSS/task-gate: No check is performed since the
3253 * hardware checks it before exiting.
3254 */
3255 if (reason == TASK_SWITCH_GATE) {
3256 if (idt_index != -1) {
3257 /* Software interrupts */
3258 struct desc_struct task_gate_desc;
3259 int dpl;
3260
3261 ret = read_interrupt_descriptor(ctxt, idt_index,
3262 &task_gate_desc);
3263 if (ret != X86EMUL_CONTINUE)
3264 return ret;
3265
3266 dpl = task_gate_desc.dpl;
3267 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
3268 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
3269 }
3270 }
3271
3272 desc_limit = desc_limit_scaled(&next_tss_desc);
3273 if (!next_tss_desc.p ||
3274 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
3275 desc_limit < 0x2b)) {
3276 return emulate_ts(ctxt, tss_selector & 0xfffc);
3277 }
3278
3279 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3280 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
3281 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
3282 }
3283
3284 if (reason == TASK_SWITCH_IRET)
3285 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
3286
3287 /* set back link to prev task only if NT bit is set in eflags
3288 note that old_tss_sel is not used after this point */
3289 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
3290 old_tss_sel = 0xffff;
3291
3292 if (next_tss_desc.type & 8)
3293 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
3294 old_tss_base, &next_tss_desc);
3295 else
3296 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
3297 old_tss_base, &next_tss_desc);
3298 if (ret != X86EMUL_CONTINUE)
3299 return ret;
3300
3301 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
3302 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
3303
3304 if (reason != TASK_SWITCH_IRET) {
3305 next_tss_desc.type |= (1 << 1); /* set busy flag */
3306 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
3307 }
3308
3309 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
3310 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
3311
3312 if (has_error_code) {
3313 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
3314 ctxt->lock_prefix = 0;
3315 ctxt->src.val = (unsigned long) error_code;
3316 ret = em_push(ctxt);
3317 }
3318
3319 ops->get_dr(ctxt, 7, &dr7);
3320 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));
3321
3322 return ret;
3323 }
3324
emulator_task_switch(struct x86_emulate_ctxt * ctxt,u16 tss_selector,int idt_index,int reason,bool has_error_code,u32 error_code)3325 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
3326 u16 tss_selector, int idt_index, int reason,
3327 bool has_error_code, u32 error_code)
3328 {
3329 int rc;
3330
3331 invalidate_registers(ctxt);
3332 ctxt->_eip = ctxt->eip;
3333 ctxt->dst.type = OP_NONE;
3334
3335 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
3336 has_error_code, error_code);
3337
3338 if (rc == X86EMUL_CONTINUE) {
3339 ctxt->eip = ctxt->_eip;
3340 writeback_registers(ctxt);
3341 }
3342
3343 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3344 }
3345
string_addr_inc(struct x86_emulate_ctxt * ctxt,int reg,struct operand * op)3346 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
3347 struct operand *op)
3348 {
3349 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
3350
3351 register_address_increment(ctxt, reg, df * op->bytes);
3352 op->addr.mem.ea = register_address(ctxt, reg);
3353 }
3354
em_das(struct x86_emulate_ctxt * ctxt)3355 static int em_das(struct x86_emulate_ctxt *ctxt)
3356 {
3357 u8 al, old_al;
3358 bool af, cf, old_cf;
3359
3360 cf = ctxt->eflags & X86_EFLAGS_CF;
3361 al = ctxt->dst.val;
3362
3363 old_al = al;
3364 old_cf = cf;
3365 cf = false;
3366 af = ctxt->eflags & X86_EFLAGS_AF;
3367 if ((al & 0x0f) > 9 || af) {
3368 al -= 6;
3369 cf = old_cf | (al >= 250);
3370 af = true;
3371 } else {
3372 af = false;
3373 }
3374 if (old_al > 0x99 || old_cf) {
3375 al -= 0x60;
3376 cf = true;
3377 }
3378
3379 ctxt->dst.val = al;
3380 /* Set PF, ZF, SF */
3381 ctxt->src.type = OP_IMM;
3382 ctxt->src.val = 0;
3383 ctxt->src.bytes = 1;
3384 fastop(ctxt, em_or);
3385 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3386 if (cf)
3387 ctxt->eflags |= X86_EFLAGS_CF;
3388 if (af)
3389 ctxt->eflags |= X86_EFLAGS_AF;
3390 return X86EMUL_CONTINUE;
3391 }
3392
em_aam(struct x86_emulate_ctxt * ctxt)3393 static int em_aam(struct x86_emulate_ctxt *ctxt)
3394 {
3395 u8 al, ah;
3396
3397 if (ctxt->src.val == 0)
3398 return emulate_de(ctxt);
3399
3400 al = ctxt->dst.val & 0xff;
3401 ah = al / ctxt->src.val;
3402 al %= ctxt->src.val;
3403
3404 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3405
3406 /* Set PF, ZF, SF */
3407 ctxt->src.type = OP_IMM;
3408 ctxt->src.val = 0;
3409 ctxt->src.bytes = 1;
3410 fastop(ctxt, em_or);
3411
3412 return X86EMUL_CONTINUE;
3413 }
3414
em_aad(struct x86_emulate_ctxt * ctxt)3415 static int em_aad(struct x86_emulate_ctxt *ctxt)
3416 {
3417 u8 al = ctxt->dst.val & 0xff;
3418 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3419
3420 al = (al + (ah * ctxt->src.val)) & 0xff;
3421
3422 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3423
3424 /* Set PF, ZF, SF */
3425 ctxt->src.type = OP_IMM;
3426 ctxt->src.val = 0;
3427 ctxt->src.bytes = 1;
3428 fastop(ctxt, em_or);
3429
3430 return X86EMUL_CONTINUE;
3431 }
3432
em_call(struct x86_emulate_ctxt * ctxt)3433 static int em_call(struct x86_emulate_ctxt *ctxt)
3434 {
3435 int rc;
3436 long rel = ctxt->src.val;
3437
3438 ctxt->src.val = (unsigned long)ctxt->_eip;
3439 rc = jmp_rel(ctxt, rel);
3440 if (rc != X86EMUL_CONTINUE)
3441 return rc;
3442 return em_push(ctxt);
3443 }
3444
em_call_far(struct x86_emulate_ctxt * ctxt)3445 static int em_call_far(struct x86_emulate_ctxt *ctxt)
3446 {
3447 u16 sel, old_cs;
3448 ulong old_eip;
3449 int rc;
3450 struct desc_struct old_desc, new_desc;
3451 const struct x86_emulate_ops *ops = ctxt->ops;
3452 int cpl = ctxt->ops->cpl(ctxt);
3453 enum x86emul_mode prev_mode = ctxt->mode;
3454
3455 old_eip = ctxt->_eip;
3456 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
3457
3458 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3459 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3460 X86_TRANSFER_CALL_JMP, &new_desc);
3461 if (rc != X86EMUL_CONTINUE)
3462 return rc;
3463
3464 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
3465 if (rc != X86EMUL_CONTINUE)
3466 goto fail;
3467
3468 ctxt->src.val = old_cs;
3469 rc = em_push(ctxt);
3470 if (rc != X86EMUL_CONTINUE)
3471 goto fail;
3472
3473 ctxt->src.val = old_eip;
3474 rc = em_push(ctxt);
3475 /* If we failed, we tainted the memory, but the very least we should
3476 restore cs */
3477 if (rc != X86EMUL_CONTINUE) {
3478 pr_warn_once("faulting far call emulation tainted memory\n");
3479 goto fail;
3480 }
3481 return rc;
3482 fail:
3483 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3484 ctxt->mode = prev_mode;
3485 return rc;
3486
3487 }
3488
em_ret_near_imm(struct x86_emulate_ctxt * ctxt)3489 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3490 {
3491 int rc;
3492 unsigned long eip;
3493
3494 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3495 if (rc != X86EMUL_CONTINUE)
3496 return rc;
3497 rc = assign_eip_near(ctxt, eip);
3498 if (rc != X86EMUL_CONTINUE)
3499 return rc;
3500 rsp_increment(ctxt, ctxt->src.val);
3501 return X86EMUL_CONTINUE;
3502 }
3503
em_xchg(struct x86_emulate_ctxt * ctxt)3504 static int em_xchg(struct x86_emulate_ctxt *ctxt)
3505 {
3506 /* Write back the register source. */
3507 ctxt->src.val = ctxt->dst.val;
3508 write_register_operand(&ctxt->src);
3509
3510 /* Write back the memory destination with implicit LOCK prefix. */
3511 ctxt->dst.val = ctxt->src.orig_val;
3512 ctxt->lock_prefix = 1;
3513 return X86EMUL_CONTINUE;
3514 }
3515
em_imul_3op(struct x86_emulate_ctxt * ctxt)3516 static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3517 {
3518 ctxt->dst.val = ctxt->src2.val;
3519 return fastop(ctxt, em_imul);
3520 }
3521
em_cwd(struct x86_emulate_ctxt * ctxt)3522 static int em_cwd(struct x86_emulate_ctxt *ctxt)
3523 {
3524 ctxt->dst.type = OP_REG;
3525 ctxt->dst.bytes = ctxt->src.bytes;
3526 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
3527 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
3528
3529 return X86EMUL_CONTINUE;
3530 }
3531
em_rdtsc(struct x86_emulate_ctxt * ctxt)3532 static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3533 {
3534 u64 tsc = 0;
3535
3536 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
3537 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3538 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
3539 return X86EMUL_CONTINUE;
3540 }
3541
em_rdpmc(struct x86_emulate_ctxt * ctxt)3542 static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3543 {
3544 u64 pmc;
3545
3546 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
3547 return emulate_gp(ctxt, 0);
3548 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3549 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
3550 return X86EMUL_CONTINUE;
3551 }
3552
em_mov(struct x86_emulate_ctxt * ctxt)3553 static int em_mov(struct x86_emulate_ctxt *ctxt)
3554 {
3555 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
3556 return X86EMUL_CONTINUE;
3557 }
3558
3559 #define FFL(x) bit(X86_FEATURE_##x)
3560
em_movbe(struct x86_emulate_ctxt * ctxt)3561 static int em_movbe(struct x86_emulate_ctxt *ctxt)
3562 {
3563 u32 ebx, ecx, edx, eax = 1;
3564 u16 tmp;
3565
3566 /*
3567 * Check MOVBE is set in the guest-visible CPUID leaf.
3568 */
3569 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3570 if (!(ecx & FFL(MOVBE)))
3571 return emulate_ud(ctxt);
3572
3573 switch (ctxt->op_bytes) {
3574 case 2:
3575 /*
3576 * From MOVBE definition: "...When the operand size is 16 bits,
3577 * the upper word of the destination register remains unchanged
3578 * ..."
3579 *
3580 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3581 * rules so we have to do the operation almost per hand.
3582 */
3583 tmp = (u16)ctxt->src.val;
3584 ctxt->dst.val &= ~0xffffUL;
3585 ctxt->dst.val |= (unsigned long)swab16(tmp);
3586 break;
3587 case 4:
3588 ctxt->dst.val = swab32((u32)ctxt->src.val);
3589 break;
3590 case 8:
3591 ctxt->dst.val = swab64(ctxt->src.val);
3592 break;
3593 default:
3594 BUG();
3595 }
3596 return X86EMUL_CONTINUE;
3597 }
3598
em_cr_write(struct x86_emulate_ctxt * ctxt)3599 static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3600 {
3601 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3602 return emulate_gp(ctxt, 0);
3603
3604 /* Disable writeback. */
3605 ctxt->dst.type = OP_NONE;
3606 return X86EMUL_CONTINUE;
3607 }
3608
em_dr_write(struct x86_emulate_ctxt * ctxt)3609 static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3610 {
3611 unsigned long val;
3612
3613 if (ctxt->mode == X86EMUL_MODE_PROT64)
3614 val = ctxt->src.val & ~0ULL;
3615 else
3616 val = ctxt->src.val & ~0U;
3617
3618 /* #UD condition is already handled. */
3619 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3620 return emulate_gp(ctxt, 0);
3621
3622 /* Disable writeback. */
3623 ctxt->dst.type = OP_NONE;
3624 return X86EMUL_CONTINUE;
3625 }
3626
em_wrmsr(struct x86_emulate_ctxt * ctxt)3627 static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3628 {
3629 u64 msr_data;
3630
3631 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3632 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3633 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
3634 return emulate_gp(ctxt, 0);
3635
3636 return X86EMUL_CONTINUE;
3637 }
3638
em_rdmsr(struct x86_emulate_ctxt * ctxt)3639 static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3640 {
3641 u64 msr_data;
3642
3643 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
3644 return emulate_gp(ctxt, 0);
3645
3646 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3647 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3648 return X86EMUL_CONTINUE;
3649 }
3650
em_mov_rm_sreg(struct x86_emulate_ctxt * ctxt)3651 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3652 {
3653 if (ctxt->modrm_reg > VCPU_SREG_GS)
3654 return emulate_ud(ctxt);
3655
3656 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
3657 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3658 ctxt->dst.bytes = 2;
3659 return X86EMUL_CONTINUE;
3660 }
3661
em_mov_sreg_rm(struct x86_emulate_ctxt * ctxt)3662 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3663 {
3664 u16 sel = ctxt->src.val;
3665
3666 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
3667 return emulate_ud(ctxt);
3668
3669 if (ctxt->modrm_reg == VCPU_SREG_SS)
3670 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3671
3672 /* Disable writeback. */
3673 ctxt->dst.type = OP_NONE;
3674 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
3675 }
3676
em_lldt(struct x86_emulate_ctxt * ctxt)3677 static int em_lldt(struct x86_emulate_ctxt *ctxt)
3678 {
3679 u16 sel = ctxt->src.val;
3680
3681 /* Disable writeback. */
3682 ctxt->dst.type = OP_NONE;
3683 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3684 }
3685
em_ltr(struct x86_emulate_ctxt * ctxt)3686 static int em_ltr(struct x86_emulate_ctxt *ctxt)
3687 {
3688 u16 sel = ctxt->src.val;
3689
3690 /* Disable writeback. */
3691 ctxt->dst.type = OP_NONE;
3692 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3693 }
3694
em_invlpg(struct x86_emulate_ctxt * ctxt)3695 static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3696 {
3697 int rc;
3698 ulong linear;
3699
3700 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
3701 if (rc == X86EMUL_CONTINUE)
3702 ctxt->ops->invlpg(ctxt, linear);
3703 /* Disable writeback. */
3704 ctxt->dst.type = OP_NONE;
3705 return X86EMUL_CONTINUE;
3706 }
3707
em_clts(struct x86_emulate_ctxt * ctxt)3708 static int em_clts(struct x86_emulate_ctxt *ctxt)
3709 {
3710 ulong cr0;
3711
3712 cr0 = ctxt->ops->get_cr(ctxt, 0);
3713 cr0 &= ~X86_CR0_TS;
3714 ctxt->ops->set_cr(ctxt, 0, cr0);
3715 return X86EMUL_CONTINUE;
3716 }
3717
em_hypercall(struct x86_emulate_ctxt * ctxt)3718 static int em_hypercall(struct x86_emulate_ctxt *ctxt)
3719 {
3720 int rc = ctxt->ops->fix_hypercall(ctxt);
3721
3722 if (rc != X86EMUL_CONTINUE)
3723 return rc;
3724
3725 /* Let the processor re-execute the fixed hypercall */
3726 ctxt->_eip = ctxt->eip;
3727 /* Disable writeback. */
3728 ctxt->dst.type = OP_NONE;
3729 return X86EMUL_CONTINUE;
3730 }
3731
emulate_store_desc_ptr(struct x86_emulate_ctxt * ctxt,void (* get)(struct x86_emulate_ctxt * ctxt,struct desc_ptr * ptr))3732 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3733 void (*get)(struct x86_emulate_ctxt *ctxt,
3734 struct desc_ptr *ptr))
3735 {
3736 struct desc_ptr desc_ptr;
3737
3738 if (ctxt->mode == X86EMUL_MODE_PROT64)
3739 ctxt->op_bytes = 8;
3740 get(ctxt, &desc_ptr);
3741 if (ctxt->op_bytes == 2) {
3742 ctxt->op_bytes = 4;
3743 desc_ptr.address &= 0x00ffffff;
3744 }
3745 /* Disable writeback. */
3746 ctxt->dst.type = OP_NONE;
3747 return segmented_write_std(ctxt, ctxt->dst.addr.mem,
3748 &desc_ptr, 2 + ctxt->op_bytes);
3749 }
3750
em_sgdt(struct x86_emulate_ctxt * ctxt)3751 static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3752 {
3753 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3754 }
3755
em_sidt(struct x86_emulate_ctxt * ctxt)3756 static int em_sidt(struct x86_emulate_ctxt *ctxt)
3757 {
3758 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3759 }
3760
em_lgdt_lidt(struct x86_emulate_ctxt * ctxt,bool lgdt)3761 static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
3762 {
3763 struct desc_ptr desc_ptr;
3764 int rc;
3765
3766 if (ctxt->mode == X86EMUL_MODE_PROT64)
3767 ctxt->op_bytes = 8;
3768 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3769 &desc_ptr.size, &desc_ptr.address,
3770 ctxt->op_bytes);
3771 if (rc != X86EMUL_CONTINUE)
3772 return rc;
3773 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3774 is_noncanonical_address(desc_ptr.address))
3775 return emulate_gp(ctxt, 0);
3776 if (lgdt)
3777 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3778 else
3779 ctxt->ops->set_idt(ctxt, &desc_ptr);
3780 /* Disable writeback. */
3781 ctxt->dst.type = OP_NONE;
3782 return X86EMUL_CONTINUE;
3783 }
3784
em_lgdt(struct x86_emulate_ctxt * ctxt)3785 static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3786 {
3787 return em_lgdt_lidt(ctxt, true);
3788 }
3789
em_lidt(struct x86_emulate_ctxt * ctxt)3790 static int em_lidt(struct x86_emulate_ctxt *ctxt)
3791 {
3792 return em_lgdt_lidt(ctxt, false);
3793 }
3794
em_smsw(struct x86_emulate_ctxt * ctxt)3795 static int em_smsw(struct x86_emulate_ctxt *ctxt)
3796 {
3797 if (ctxt->dst.type == OP_MEM)
3798 ctxt->dst.bytes = 2;
3799 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3800 return X86EMUL_CONTINUE;
3801 }
3802
em_lmsw(struct x86_emulate_ctxt * ctxt)3803 static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3804 {
3805 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3806 | (ctxt->src.val & 0x0f));
3807 ctxt->dst.type = OP_NONE;
3808 return X86EMUL_CONTINUE;
3809 }
3810
em_loop(struct x86_emulate_ctxt * ctxt)3811 static int em_loop(struct x86_emulate_ctxt *ctxt)
3812 {
3813 int rc = X86EMUL_CONTINUE;
3814
3815 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
3816 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3817 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3818 rc = jmp_rel(ctxt, ctxt->src.val);
3819
3820 return rc;
3821 }
3822
em_jcxz(struct x86_emulate_ctxt * ctxt)3823 static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3824 {
3825 int rc = X86EMUL_CONTINUE;
3826
3827 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3828 rc = jmp_rel(ctxt, ctxt->src.val);
3829
3830 return rc;
3831 }
3832
em_in(struct x86_emulate_ctxt * ctxt)3833 static int em_in(struct x86_emulate_ctxt *ctxt)
3834 {
3835 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3836 &ctxt->dst.val))
3837 return X86EMUL_IO_NEEDED;
3838
3839 return X86EMUL_CONTINUE;
3840 }
3841
em_out(struct x86_emulate_ctxt * ctxt)3842 static int em_out(struct x86_emulate_ctxt *ctxt)
3843 {
3844 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3845 &ctxt->src.val, 1);
3846 /* Disable writeback. */
3847 ctxt->dst.type = OP_NONE;
3848 return X86EMUL_CONTINUE;
3849 }
3850
em_cli(struct x86_emulate_ctxt * ctxt)3851 static int em_cli(struct x86_emulate_ctxt *ctxt)
3852 {
3853 if (emulator_bad_iopl(ctxt))
3854 return emulate_gp(ctxt, 0);
3855
3856 ctxt->eflags &= ~X86_EFLAGS_IF;
3857 return X86EMUL_CONTINUE;
3858 }
3859
em_sti(struct x86_emulate_ctxt * ctxt)3860 static int em_sti(struct x86_emulate_ctxt *ctxt)
3861 {
3862 if (emulator_bad_iopl(ctxt))
3863 return emulate_gp(ctxt, 0);
3864
3865 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3866 ctxt->eflags |= X86_EFLAGS_IF;
3867 return X86EMUL_CONTINUE;
3868 }
3869
em_cpuid(struct x86_emulate_ctxt * ctxt)3870 static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3871 {
3872 u32 eax, ebx, ecx, edx;
3873
3874 eax = reg_read(ctxt, VCPU_REGS_RAX);
3875 ecx = reg_read(ctxt, VCPU_REGS_RCX);
3876 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3877 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3878 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3879 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3880 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
3881 return X86EMUL_CONTINUE;
3882 }
3883
em_sahf(struct x86_emulate_ctxt * ctxt)3884 static int em_sahf(struct x86_emulate_ctxt *ctxt)
3885 {
3886 u32 flags;
3887
3888 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
3889 X86_EFLAGS_SF;
3890 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3891
3892 ctxt->eflags &= ~0xffUL;
3893 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3894 return X86EMUL_CONTINUE;
3895 }
3896
em_lahf(struct x86_emulate_ctxt * ctxt)3897 static int em_lahf(struct x86_emulate_ctxt *ctxt)
3898 {
3899 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3900 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
3901 return X86EMUL_CONTINUE;
3902 }
3903
em_bswap(struct x86_emulate_ctxt * ctxt)3904 static int em_bswap(struct x86_emulate_ctxt *ctxt)
3905 {
3906 switch (ctxt->op_bytes) {
3907 #ifdef CONFIG_X86_64
3908 case 8:
3909 asm("bswap %0" : "+r"(ctxt->dst.val));
3910 break;
3911 #endif
3912 default:
3913 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3914 break;
3915 }
3916 return X86EMUL_CONTINUE;
3917 }
3918
em_clflush(struct x86_emulate_ctxt * ctxt)3919 static int em_clflush(struct x86_emulate_ctxt *ctxt)
3920 {
3921 /* emulating clflush regardless of cpuid */
3922 return X86EMUL_CONTINUE;
3923 }
3924
em_movsxd(struct x86_emulate_ctxt * ctxt)3925 static int em_movsxd(struct x86_emulate_ctxt *ctxt)
3926 {
3927 ctxt->dst.val = (s32) ctxt->src.val;
3928 return X86EMUL_CONTINUE;
3929 }
3930
check_fxsr(struct x86_emulate_ctxt * ctxt)3931 static int check_fxsr(struct x86_emulate_ctxt *ctxt)
3932 {
3933 u32 eax = 1, ebx, ecx = 0, edx;
3934
3935 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3936 if (!(edx & FFL(FXSR)))
3937 return emulate_ud(ctxt);
3938
3939 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
3940 return emulate_nm(ctxt);
3941
3942 /*
3943 * Don't emulate a case that should never be hit, instead of working
3944 * around a lack of fxsave64/fxrstor64 on old compilers.
3945 */
3946 if (ctxt->mode >= X86EMUL_MODE_PROT64)
3947 return X86EMUL_UNHANDLEABLE;
3948
3949 return X86EMUL_CONTINUE;
3950 }
3951
3952 /*
3953 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode,
3954 * 1) 16 bit mode
3955 * 2) 32 bit mode
3956 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs
3957 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt.
3958 * save and restore
3959 * 3) 64-bit mode with REX.W prefix
3960 * - like (2), but XMM 8-15 are being saved and restored
3961 * 4) 64-bit mode without REX.W prefix
3962 * - like (3), but FIP and FDP are 64 bit
3963 *
3964 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the
3965 * desired result. (4) is not emulated.
3966 *
3967 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS
3968 * and FPU DS) should match.
3969 */
em_fxsave(struct x86_emulate_ctxt * ctxt)3970 static int em_fxsave(struct x86_emulate_ctxt *ctxt)
3971 {
3972 struct fxregs_state fx_state;
3973 size_t size;
3974 int rc;
3975
3976 rc = check_fxsr(ctxt);
3977 if (rc != X86EMUL_CONTINUE)
3978 return rc;
3979
3980 ctxt->ops->get_fpu(ctxt);
3981
3982 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state));
3983
3984 ctxt->ops->put_fpu(ctxt);
3985
3986 if (rc != X86EMUL_CONTINUE)
3987 return rc;
3988
3989 if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR)
3990 size = offsetof(struct fxregs_state, xmm_space[8 * 16/4]);
3991 else
3992 size = offsetof(struct fxregs_state, xmm_space[0]);
3993
3994 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state, size);
3995 }
3996
fxrstor_fixup(struct x86_emulate_ctxt * ctxt,struct fxregs_state * new)3997 static int fxrstor_fixup(struct x86_emulate_ctxt *ctxt,
3998 struct fxregs_state *new)
3999 {
4000 int rc = X86EMUL_CONTINUE;
4001 struct fxregs_state old;
4002
4003 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(old));
4004 if (rc != X86EMUL_CONTINUE)
4005 return rc;
4006
4007 /*
4008 * 64 bit host will restore XMM 8-15, which is not correct on non-64
4009 * bit guests. Load the current values in order to preserve 64 bit
4010 * XMMs after fxrstor.
4011 */
4012 #ifdef CONFIG_X86_64
4013 /* XXX: accessing XMM 8-15 very awkwardly */
4014 memcpy(&new->xmm_space[8 * 16/4], &old.xmm_space[8 * 16/4], 8 * 16);
4015 #endif
4016
4017 /*
4018 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but
4019 * does save and restore MXCSR.
4020 */
4021 if (!(ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))
4022 memcpy(new->xmm_space, old.xmm_space, 8 * 16);
4023
4024 return rc;
4025 }
4026
em_fxrstor(struct x86_emulate_ctxt * ctxt)4027 static int em_fxrstor(struct x86_emulate_ctxt *ctxt)
4028 {
4029 struct fxregs_state fx_state;
4030 int rc;
4031
4032 rc = check_fxsr(ctxt);
4033 if (rc != X86EMUL_CONTINUE)
4034 return rc;
4035
4036 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, 512);
4037 if (rc != X86EMUL_CONTINUE)
4038 return rc;
4039
4040 if (fx_state.mxcsr >> 16)
4041 return emulate_gp(ctxt, 0);
4042
4043 ctxt->ops->get_fpu(ctxt);
4044
4045 if (ctxt->mode < X86EMUL_MODE_PROT64)
4046 rc = fxrstor_fixup(ctxt, &fx_state);
4047
4048 if (rc == X86EMUL_CONTINUE)
4049 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state));
4050
4051 ctxt->ops->put_fpu(ctxt);
4052
4053 return rc;
4054 }
4055
valid_cr(int nr)4056 static bool valid_cr(int nr)
4057 {
4058 switch (nr) {
4059 case 0:
4060 case 2 ... 4:
4061 case 8:
4062 return true;
4063 default:
4064 return false;
4065 }
4066 }
4067
check_cr_read(struct x86_emulate_ctxt * ctxt)4068 static int check_cr_read(struct x86_emulate_ctxt *ctxt)
4069 {
4070 if (!valid_cr(ctxt->modrm_reg))
4071 return emulate_ud(ctxt);
4072
4073 return X86EMUL_CONTINUE;
4074 }
4075
check_cr_write(struct x86_emulate_ctxt * ctxt)4076 static int check_cr_write(struct x86_emulate_ctxt *ctxt)
4077 {
4078 u64 new_val = ctxt->src.val64;
4079 int cr = ctxt->modrm_reg;
4080 u64 efer = 0;
4081
4082 static u64 cr_reserved_bits[] = {
4083 0xffffffff00000000ULL,
4084 0, 0, 0, /* CR3 checked later */
4085 CR4_RESERVED_BITS,
4086 0, 0, 0,
4087 CR8_RESERVED_BITS,
4088 };
4089
4090 if (!valid_cr(cr))
4091 return emulate_ud(ctxt);
4092
4093 if (new_val & cr_reserved_bits[cr])
4094 return emulate_gp(ctxt, 0);
4095
4096 switch (cr) {
4097 case 0: {
4098 u64 cr4;
4099 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
4100 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
4101 return emulate_gp(ctxt, 0);
4102
4103 cr4 = ctxt->ops->get_cr(ctxt, 4);
4104 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4105
4106 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
4107 !(cr4 & X86_CR4_PAE))
4108 return emulate_gp(ctxt, 0);
4109
4110 break;
4111 }
4112 case 3: {
4113 u64 rsvd = 0;
4114
4115 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4116 if (efer & EFER_LMA)
4117 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
4118
4119 if (new_val & rsvd)
4120 return emulate_gp(ctxt, 0);
4121
4122 break;
4123 }
4124 case 4: {
4125 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4126
4127 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
4128 return emulate_gp(ctxt, 0);
4129
4130 break;
4131 }
4132 }
4133
4134 return X86EMUL_CONTINUE;
4135 }
4136
check_dr7_gd(struct x86_emulate_ctxt * ctxt)4137 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
4138 {
4139 unsigned long dr7;
4140
4141 ctxt->ops->get_dr(ctxt, 7, &dr7);
4142
4143 /* Check if DR7.Global_Enable is set */
4144 return dr7 & (1 << 13);
4145 }
4146
check_dr_read(struct x86_emulate_ctxt * ctxt)4147 static int check_dr_read(struct x86_emulate_ctxt *ctxt)
4148 {
4149 int dr = ctxt->modrm_reg;
4150 u64 cr4;
4151
4152 if (dr > 7)
4153 return emulate_ud(ctxt);
4154
4155 cr4 = ctxt->ops->get_cr(ctxt, 4);
4156 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
4157 return emulate_ud(ctxt);
4158
4159 if (check_dr7_gd(ctxt)) {
4160 ulong dr6;
4161
4162 ctxt->ops->get_dr(ctxt, 6, &dr6);
4163 dr6 &= ~15;
4164 dr6 |= DR6_BD | DR6_RTM;
4165 ctxt->ops->set_dr(ctxt, 6, dr6);
4166 return emulate_db(ctxt);
4167 }
4168
4169 return X86EMUL_CONTINUE;
4170 }
4171
check_dr_write(struct x86_emulate_ctxt * ctxt)4172 static int check_dr_write(struct x86_emulate_ctxt *ctxt)
4173 {
4174 u64 new_val = ctxt->src.val64;
4175 int dr = ctxt->modrm_reg;
4176
4177 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
4178 return emulate_gp(ctxt, 0);
4179
4180 return check_dr_read(ctxt);
4181 }
4182
check_svme(struct x86_emulate_ctxt * ctxt)4183 static int check_svme(struct x86_emulate_ctxt *ctxt)
4184 {
4185 u64 efer;
4186
4187 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4188
4189 if (!(efer & EFER_SVME))
4190 return emulate_ud(ctxt);
4191
4192 return X86EMUL_CONTINUE;
4193 }
4194
check_svme_pa(struct x86_emulate_ctxt * ctxt)4195 static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
4196 {
4197 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
4198
4199 /* Valid physical address? */
4200 if (rax & 0xffff000000000000ULL)
4201 return emulate_gp(ctxt, 0);
4202
4203 return check_svme(ctxt);
4204 }
4205
check_rdtsc(struct x86_emulate_ctxt * ctxt)4206 static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
4207 {
4208 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
4209
4210 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
4211 return emulate_ud(ctxt);
4212
4213 return X86EMUL_CONTINUE;
4214 }
4215
check_rdpmc(struct x86_emulate_ctxt * ctxt)4216 static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
4217 {
4218 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
4219 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
4220
4221 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
4222 ctxt->ops->check_pmc(ctxt, rcx))
4223 return emulate_gp(ctxt, 0);
4224
4225 return X86EMUL_CONTINUE;
4226 }
4227
check_perm_in(struct x86_emulate_ctxt * ctxt)4228 static int check_perm_in(struct x86_emulate_ctxt *ctxt)
4229 {
4230 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
4231 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
4232 return emulate_gp(ctxt, 0);
4233
4234 return X86EMUL_CONTINUE;
4235 }
4236
check_perm_out(struct x86_emulate_ctxt * ctxt)4237 static int check_perm_out(struct x86_emulate_ctxt *ctxt)
4238 {
4239 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
4240 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
4241 return emulate_gp(ctxt, 0);
4242
4243 return X86EMUL_CONTINUE;
4244 }
4245
4246 #define D(_y) { .flags = (_y) }
4247 #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
4248 #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
4249 .intercept = x86_intercept_##_i, .check_perm = (_p) }
4250 #define N D(NotImpl)
4251 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
4252 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
4253 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
4254 #define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
4255 #define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
4256 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
4257 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
4258 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
4259 #define II(_f, _e, _i) \
4260 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
4261 #define IIP(_f, _e, _i, _p) \
4262 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
4263 .intercept = x86_intercept_##_i, .check_perm = (_p) }
4264 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
4265
4266 #define D2bv(_f) D((_f) | ByteOp), D(_f)
4267 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
4268 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
4269 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
4270 #define I2bvIP(_f, _e, _i, _p) \
4271 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
4272
4273 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
4274 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
4275 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
4276
4277 static const struct opcode group7_rm0[] = {
4278 N,
4279 I(SrcNone | Priv | EmulateOnUD, em_hypercall),
4280 N, N, N, N, N, N,
4281 };
4282
4283 static const struct opcode group7_rm1[] = {
4284 DI(SrcNone | Priv, monitor),
4285 DI(SrcNone | Priv, mwait),
4286 N, N, N, N, N, N,
4287 };
4288
4289 static const struct opcode group7_rm3[] = {
4290 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
4291 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall),
4292 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
4293 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
4294 DIP(SrcNone | Prot | Priv, stgi, check_svme),
4295 DIP(SrcNone | Prot | Priv, clgi, check_svme),
4296 DIP(SrcNone | Prot | Priv, skinit, check_svme),
4297 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
4298 };
4299
4300 static const struct opcode group7_rm7[] = {
4301 N,
4302 DIP(SrcNone, rdtscp, check_rdtsc),
4303 N, N, N, N, N, N,
4304 };
4305
4306 static const struct opcode group1[] = {
4307 F(Lock, em_add),
4308 F(Lock | PageTable, em_or),
4309 F(Lock, em_adc),
4310 F(Lock, em_sbb),
4311 F(Lock | PageTable, em_and),
4312 F(Lock, em_sub),
4313 F(Lock, em_xor),
4314 F(NoWrite, em_cmp),
4315 };
4316
4317 static const struct opcode group1A[] = {
4318 I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N,
4319 };
4320
4321 static const struct opcode group2[] = {
4322 F(DstMem | ModRM, em_rol),
4323 F(DstMem | ModRM, em_ror),
4324 F(DstMem | ModRM, em_rcl),
4325 F(DstMem | ModRM, em_rcr),
4326 F(DstMem | ModRM, em_shl),
4327 F(DstMem | ModRM, em_shr),
4328 F(DstMem | ModRM, em_shl),
4329 F(DstMem | ModRM, em_sar),
4330 };
4331
4332 static const struct opcode group3[] = {
4333 F(DstMem | SrcImm | NoWrite, em_test),
4334 F(DstMem | SrcImm | NoWrite, em_test),
4335 F(DstMem | SrcNone | Lock, em_not),
4336 F(DstMem | SrcNone | Lock, em_neg),
4337 F(DstXacc | Src2Mem, em_mul_ex),
4338 F(DstXacc | Src2Mem, em_imul_ex),
4339 F(DstXacc | Src2Mem, em_div_ex),
4340 F(DstXacc | Src2Mem, em_idiv_ex),
4341 };
4342
4343 static const struct opcode group4[] = {
4344 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
4345 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
4346 N, N, N, N, N, N,
4347 };
4348
4349 static const struct opcode group5[] = {
4350 F(DstMem | SrcNone | Lock, em_inc),
4351 F(DstMem | SrcNone | Lock, em_dec),
4352 I(SrcMem | NearBranch, em_call_near_abs),
4353 I(SrcMemFAddr | ImplicitOps, em_call_far),
4354 I(SrcMem | NearBranch, em_jmp_abs),
4355 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
4356 I(SrcMem | Stack, em_push), D(Undefined),
4357 };
4358
4359 static const struct opcode group6[] = {
4360 DI(Prot | DstMem, sldt),
4361 DI(Prot | DstMem, str),
4362 II(Prot | Priv | SrcMem16, em_lldt, lldt),
4363 II(Prot | Priv | SrcMem16, em_ltr, ltr),
4364 N, N, N, N,
4365 };
4366
4367 static const struct group_dual group7 = { {
4368 II(Mov | DstMem, em_sgdt, sgdt),
4369 II(Mov | DstMem, em_sidt, sidt),
4370 II(SrcMem | Priv, em_lgdt, lgdt),
4371 II(SrcMem | Priv, em_lidt, lidt),
4372 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4373 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4374 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
4375 }, {
4376 EXT(0, group7_rm0),
4377 EXT(0, group7_rm1),
4378 N, EXT(0, group7_rm3),
4379 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4380 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4381 EXT(0, group7_rm7),
4382 } };
4383
4384 static const struct opcode group8[] = {
4385 N, N, N, N,
4386 F(DstMem | SrcImmByte | NoWrite, em_bt),
4387 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
4388 F(DstMem | SrcImmByte | Lock, em_btr),
4389 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
4390 };
4391
4392 static const struct group_dual group9 = { {
4393 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
4394 }, {
4395 N, N, N, N, N, N, N, N,
4396 } };
4397
4398 static const struct opcode group11[] = {
4399 I(DstMem | SrcImm | Mov | PageTable, em_mov),
4400 X7(D(Undefined)),
4401 };
4402
4403 static const struct gprefix pfx_0f_ae_7 = {
4404 I(SrcMem | ByteOp, em_clflush), N, N, N,
4405 };
4406
4407 static const struct group_dual group15 = { {
4408 I(ModRM | Aligned16, em_fxsave),
4409 I(ModRM | Aligned16, em_fxrstor),
4410 N, N, N, N, N, GP(0, &pfx_0f_ae_7),
4411 }, {
4412 N, N, N, N, N, N, N, N,
4413 } };
4414
4415 static const struct gprefix pfx_0f_6f_0f_7f = {
4416 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
4417 };
4418
4419 static const struct instr_dual instr_dual_0f_2b = {
4420 I(0, em_mov), N
4421 };
4422
4423 static const struct gprefix pfx_0f_2b = {
4424 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
4425 };
4426
4427 static const struct gprefix pfx_0f_28_0f_29 = {
4428 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
4429 };
4430
4431 static const struct gprefix pfx_0f_e7 = {
4432 N, I(Sse, em_mov), N, N,
4433 };
4434
4435 static const struct escape escape_d9 = { {
4436 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
4437 }, {
4438 /* 0xC0 - 0xC7 */
4439 N, N, N, N, N, N, N, N,
4440 /* 0xC8 - 0xCF */
4441 N, N, N, N, N, N, N, N,
4442 /* 0xD0 - 0xC7 */
4443 N, N, N, N, N, N, N, N,
4444 /* 0xD8 - 0xDF */
4445 N, N, N, N, N, N, N, N,
4446 /* 0xE0 - 0xE7 */
4447 N, N, N, N, N, N, N, N,
4448 /* 0xE8 - 0xEF */
4449 N, N, N, N, N, N, N, N,
4450 /* 0xF0 - 0xF7 */
4451 N, N, N, N, N, N, N, N,
4452 /* 0xF8 - 0xFF */
4453 N, N, N, N, N, N, N, N,
4454 } };
4455
4456 static const struct escape escape_db = { {
4457 N, N, N, N, N, N, N, N,
4458 }, {
4459 /* 0xC0 - 0xC7 */
4460 N, N, N, N, N, N, N, N,
4461 /* 0xC8 - 0xCF */
4462 N, N, N, N, N, N, N, N,
4463 /* 0xD0 - 0xC7 */
4464 N, N, N, N, N, N, N, N,
4465 /* 0xD8 - 0xDF */
4466 N, N, N, N, N, N, N, N,
4467 /* 0xE0 - 0xE7 */
4468 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
4469 /* 0xE8 - 0xEF */
4470 N, N, N, N, N, N, N, N,
4471 /* 0xF0 - 0xF7 */
4472 N, N, N, N, N, N, N, N,
4473 /* 0xF8 - 0xFF */
4474 N, N, N, N, N, N, N, N,
4475 } };
4476
4477 static const struct escape escape_dd = { {
4478 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
4479 }, {
4480 /* 0xC0 - 0xC7 */
4481 N, N, N, N, N, N, N, N,
4482 /* 0xC8 - 0xCF */
4483 N, N, N, N, N, N, N, N,
4484 /* 0xD0 - 0xC7 */
4485 N, N, N, N, N, N, N, N,
4486 /* 0xD8 - 0xDF */
4487 N, N, N, N, N, N, N, N,
4488 /* 0xE0 - 0xE7 */
4489 N, N, N, N, N, N, N, N,
4490 /* 0xE8 - 0xEF */
4491 N, N, N, N, N, N, N, N,
4492 /* 0xF0 - 0xF7 */
4493 N, N, N, N, N, N, N, N,
4494 /* 0xF8 - 0xFF */
4495 N, N, N, N, N, N, N, N,
4496 } };
4497
4498 static const struct instr_dual instr_dual_0f_c3 = {
4499 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
4500 };
4501
4502 static const struct mode_dual mode_dual_63 = {
4503 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
4504 };
4505
4506 static const struct opcode opcode_table[256] = {
4507 /* 0x00 - 0x07 */
4508 F6ALU(Lock, em_add),
4509 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
4510 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
4511 /* 0x08 - 0x0F */
4512 F6ALU(Lock | PageTable, em_or),
4513 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4514 N,
4515 /* 0x10 - 0x17 */
4516 F6ALU(Lock, em_adc),
4517 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4518 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
4519 /* 0x18 - 0x1F */
4520 F6ALU(Lock, em_sbb),
4521 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4522 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
4523 /* 0x20 - 0x27 */
4524 F6ALU(Lock | PageTable, em_and), N, N,
4525 /* 0x28 - 0x2F */
4526 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
4527 /* 0x30 - 0x37 */
4528 F6ALU(Lock, em_xor), N, N,
4529 /* 0x38 - 0x3F */
4530 F6ALU(NoWrite, em_cmp), N, N,
4531 /* 0x40 - 0x4F */
4532 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
4533 /* 0x50 - 0x57 */
4534 X8(I(SrcReg | Stack, em_push)),
4535 /* 0x58 - 0x5F */
4536 X8(I(DstReg | Stack, em_pop)),
4537 /* 0x60 - 0x67 */
4538 I(ImplicitOps | Stack | No64, em_pusha),
4539 I(ImplicitOps | Stack | No64, em_popa),
4540 N, MD(ModRM, &mode_dual_63),
4541 N, N, N, N,
4542 /* 0x68 - 0x6F */
4543 I(SrcImm | Mov | Stack, em_push),
4544 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
4545 I(SrcImmByte | Mov | Stack, em_push),
4546 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
4547 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
4548 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
4549 /* 0x70 - 0x7F */
4550 X16(D(SrcImmByte | NearBranch)),
4551 /* 0x80 - 0x87 */
4552 G(ByteOp | DstMem | SrcImm, group1),
4553 G(DstMem | SrcImm, group1),
4554 G(ByteOp | DstMem | SrcImm | No64, group1),
4555 G(DstMem | SrcImmByte, group1),
4556 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
4557 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
4558 /* 0x88 - 0x8F */
4559 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
4560 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
4561 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
4562 D(ModRM | SrcMem | NoAccess | DstReg),
4563 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4564 G(0, group1A),
4565 /* 0x90 - 0x97 */
4566 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
4567 /* 0x98 - 0x9F */
4568 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
4569 I(SrcImmFAddr | No64, em_call_far), N,
4570 II(ImplicitOps | Stack, em_pushf, pushf),
4571 II(ImplicitOps | Stack, em_popf, popf),
4572 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
4573 /* 0xA0 - 0xA7 */
4574 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
4575 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
4576 I2bv(SrcSI | DstDI | Mov | String, em_mov),
4577 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
4578 /* 0xA8 - 0xAF */
4579 F2bv(DstAcc | SrcImm | NoWrite, em_test),
4580 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4581 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
4582 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
4583 /* 0xB0 - 0xB7 */
4584 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
4585 /* 0xB8 - 0xBF */
4586 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
4587 /* 0xC0 - 0xC7 */
4588 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
4589 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4590 I(ImplicitOps | NearBranch, em_ret),
4591 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4592 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
4593 G(ByteOp, group11), G(0, group11),
4594 /* 0xC8 - 0xCF */
4595 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
4596 I(ImplicitOps | SrcImmU16, em_ret_far_imm),
4597 I(ImplicitOps, em_ret_far),
4598 D(ImplicitOps), DI(SrcImmByte, intn),
4599 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
4600 /* 0xD0 - 0xD7 */
4601 G(Src2One | ByteOp, group2), G(Src2One, group2),
4602 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
4603 I(DstAcc | SrcImmUByte | No64, em_aam),
4604 I(DstAcc | SrcImmUByte | No64, em_aad),
4605 F(DstAcc | ByteOp | No64, em_salc),
4606 I(DstAcc | SrcXLat | ByteOp, em_mov),
4607 /* 0xD8 - 0xDF */
4608 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
4609 /* 0xE0 - 0xE7 */
4610 X3(I(SrcImmByte | NearBranch, em_loop)),
4611 I(SrcImmByte | NearBranch, em_jcxz),
4612 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4613 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
4614 /* 0xE8 - 0xEF */
4615 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4616 I(SrcImmFAddr | No64, em_jmp_far),
4617 D(SrcImmByte | ImplicitOps | NearBranch),
4618 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4619 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
4620 /* 0xF0 - 0xF7 */
4621 N, DI(ImplicitOps, icebp), N, N,
4622 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4623 G(ByteOp, group3), G(0, group3),
4624 /* 0xF8 - 0xFF */
4625 D(ImplicitOps), D(ImplicitOps),
4626 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
4627 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4628 };
4629
4630 static const struct opcode twobyte_table[256] = {
4631 /* 0x00 - 0x0F */
4632 G(0, group6), GD(0, &group7), N, N,
4633 N, I(ImplicitOps | EmulateOnUD, em_syscall),
4634 II(ImplicitOps | Priv, em_clts, clts), N,
4635 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
4636 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
4637 /* 0x10 - 0x1F */
4638 N, N, N, N, N, N, N, N,
4639 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4640 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
4641 /* 0x20 - 0x2F */
4642 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4643 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4644 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4645 check_cr_write),
4646 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4647 check_dr_write),
4648 N, N, N, N,
4649 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4650 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
4651 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
4652 N, N, N, N,
4653 /* 0x30 - 0x3F */
4654 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
4655 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
4656 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
4657 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
4658 I(ImplicitOps | EmulateOnUD, em_sysenter),
4659 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
4660 N, N,
4661 N, N, N, N, N, N, N, N,
4662 /* 0x40 - 0x4F */
4663 X16(D(DstReg | SrcMem | ModRM)),
4664 /* 0x50 - 0x5F */
4665 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4666 /* 0x60 - 0x6F */
4667 N, N, N, N,
4668 N, N, N, N,
4669 N, N, N, N,
4670 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
4671 /* 0x70 - 0x7F */
4672 N, N, N, N,
4673 N, N, N, N,
4674 N, N, N, N,
4675 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
4676 /* 0x80 - 0x8F */
4677 X16(D(SrcImm | NearBranch)),
4678 /* 0x90 - 0x9F */
4679 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
4680 /* 0xA0 - 0xA7 */
4681 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
4682 II(ImplicitOps, em_cpuid, cpuid),
4683 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
4684 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4685 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
4686 /* 0xA8 - 0xAF */
4687 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
4688 II(EmulateOnUD | ImplicitOps, em_rsm, rsm),
4689 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
4690 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4691 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4692 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
4693 /* 0xB0 - 0xB7 */
4694 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
4695 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
4696 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
4697 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4698 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
4699 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4700 /* 0xB8 - 0xBF */
4701 N, N,
4702 G(BitOp, group8),
4703 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4704 I(DstReg | SrcMem | ModRM, em_bsf_c),
4705 I(DstReg | SrcMem | ModRM, em_bsr_c),
4706 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4707 /* 0xC0 - 0xC7 */
4708 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
4709 N, ID(0, &instr_dual_0f_c3),
4710 N, N, N, GD(0, &group9),
4711 /* 0xC8 - 0xCF */
4712 X8(I(DstReg, em_bswap)),
4713 /* 0xD0 - 0xDF */
4714 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4715 /* 0xE0 - 0xEF */
4716 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4717 N, N, N, N, N, N, N, N,
4718 /* 0xF0 - 0xFF */
4719 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4720 };
4721
4722 static const struct instr_dual instr_dual_0f_38_f0 = {
4723 I(DstReg | SrcMem | Mov, em_movbe), N
4724 };
4725
4726 static const struct instr_dual instr_dual_0f_38_f1 = {
4727 I(DstMem | SrcReg | Mov, em_movbe), N
4728 };
4729
4730 static const struct gprefix three_byte_0f_38_f0 = {
4731 ID(0, &instr_dual_0f_38_f0), N, N, N
4732 };
4733
4734 static const struct gprefix three_byte_0f_38_f1 = {
4735 ID(0, &instr_dual_0f_38_f1), N, N, N
4736 };
4737
4738 /*
4739 * Insns below are selected by the prefix which indexed by the third opcode
4740 * byte.
4741 */
4742 static const struct opcode opcode_map_0f_38[256] = {
4743 /* 0x00 - 0x7f */
4744 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4745 /* 0x80 - 0xef */
4746 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4747 /* 0xf0 - 0xf1 */
4748 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4749 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
4750 /* 0xf2 - 0xff */
4751 N, N, X4(N), X8(N)
4752 };
4753
4754 #undef D
4755 #undef N
4756 #undef G
4757 #undef GD
4758 #undef I
4759 #undef GP
4760 #undef EXT
4761 #undef MD
4762 #undef ID
4763
4764 #undef D2bv
4765 #undef D2bvIP
4766 #undef I2bv
4767 #undef I2bvIP
4768 #undef I6ALU
4769
imm_size(struct x86_emulate_ctxt * ctxt)4770 static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
4771 {
4772 unsigned size;
4773
4774 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4775 if (size == 8)
4776 size = 4;
4777 return size;
4778 }
4779
decode_imm(struct x86_emulate_ctxt * ctxt,struct operand * op,unsigned size,bool sign_extension)4780 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4781 unsigned size, bool sign_extension)
4782 {
4783 int rc = X86EMUL_CONTINUE;
4784
4785 op->type = OP_IMM;
4786 op->bytes = size;
4787 op->addr.mem.ea = ctxt->_eip;
4788 /* NB. Immediates are sign-extended as necessary. */
4789 switch (op->bytes) {
4790 case 1:
4791 op->val = insn_fetch(s8, ctxt);
4792 break;
4793 case 2:
4794 op->val = insn_fetch(s16, ctxt);
4795 break;
4796 case 4:
4797 op->val = insn_fetch(s32, ctxt);
4798 break;
4799 case 8:
4800 op->val = insn_fetch(s64, ctxt);
4801 break;
4802 }
4803 if (!sign_extension) {
4804 switch (op->bytes) {
4805 case 1:
4806 op->val &= 0xff;
4807 break;
4808 case 2:
4809 op->val &= 0xffff;
4810 break;
4811 case 4:
4812 op->val &= 0xffffffff;
4813 break;
4814 }
4815 }
4816 done:
4817 return rc;
4818 }
4819
decode_operand(struct x86_emulate_ctxt * ctxt,struct operand * op,unsigned d)4820 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4821 unsigned d)
4822 {
4823 int rc = X86EMUL_CONTINUE;
4824
4825 switch (d) {
4826 case OpReg:
4827 decode_register_operand(ctxt, op);
4828 break;
4829 case OpImmUByte:
4830 rc = decode_imm(ctxt, op, 1, false);
4831 break;
4832 case OpMem:
4833 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4834 mem_common:
4835 *op = ctxt->memop;
4836 ctxt->memopp = op;
4837 if (ctxt->d & BitOp)
4838 fetch_bit_operand(ctxt);
4839 op->orig_val = op->val;
4840 break;
4841 case OpMem64:
4842 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
4843 goto mem_common;
4844 case OpAcc:
4845 op->type = OP_REG;
4846 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4847 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4848 fetch_register_operand(op);
4849 op->orig_val = op->val;
4850 break;
4851 case OpAccLo:
4852 op->type = OP_REG;
4853 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4854 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4855 fetch_register_operand(op);
4856 op->orig_val = op->val;
4857 break;
4858 case OpAccHi:
4859 if (ctxt->d & ByteOp) {
4860 op->type = OP_NONE;
4861 break;
4862 }
4863 op->type = OP_REG;
4864 op->bytes = ctxt->op_bytes;
4865 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4866 fetch_register_operand(op);
4867 op->orig_val = op->val;
4868 break;
4869 case OpDI:
4870 op->type = OP_MEM;
4871 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4872 op->addr.mem.ea =
4873 register_address(ctxt, VCPU_REGS_RDI);
4874 op->addr.mem.seg = VCPU_SREG_ES;
4875 op->val = 0;
4876 op->count = 1;
4877 break;
4878 case OpDX:
4879 op->type = OP_REG;
4880 op->bytes = 2;
4881 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4882 fetch_register_operand(op);
4883 break;
4884 case OpCL:
4885 op->type = OP_IMM;
4886 op->bytes = 1;
4887 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4888 break;
4889 case OpImmByte:
4890 rc = decode_imm(ctxt, op, 1, true);
4891 break;
4892 case OpOne:
4893 op->type = OP_IMM;
4894 op->bytes = 1;
4895 op->val = 1;
4896 break;
4897 case OpImm:
4898 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4899 break;
4900 case OpImm64:
4901 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4902 break;
4903 case OpMem8:
4904 ctxt->memop.bytes = 1;
4905 if (ctxt->memop.type == OP_REG) {
4906 ctxt->memop.addr.reg = decode_register(ctxt,
4907 ctxt->modrm_rm, true);
4908 fetch_register_operand(&ctxt->memop);
4909 }
4910 goto mem_common;
4911 case OpMem16:
4912 ctxt->memop.bytes = 2;
4913 goto mem_common;
4914 case OpMem32:
4915 ctxt->memop.bytes = 4;
4916 goto mem_common;
4917 case OpImmU16:
4918 rc = decode_imm(ctxt, op, 2, false);
4919 break;
4920 case OpImmU:
4921 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4922 break;
4923 case OpSI:
4924 op->type = OP_MEM;
4925 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4926 op->addr.mem.ea =
4927 register_address(ctxt, VCPU_REGS_RSI);
4928 op->addr.mem.seg = ctxt->seg_override;
4929 op->val = 0;
4930 op->count = 1;
4931 break;
4932 case OpXLat:
4933 op->type = OP_MEM;
4934 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4935 op->addr.mem.ea =
4936 address_mask(ctxt,
4937 reg_read(ctxt, VCPU_REGS_RBX) +
4938 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4939 op->addr.mem.seg = ctxt->seg_override;
4940 op->val = 0;
4941 break;
4942 case OpImmFAddr:
4943 op->type = OP_IMM;
4944 op->addr.mem.ea = ctxt->_eip;
4945 op->bytes = ctxt->op_bytes + 2;
4946 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4947 break;
4948 case OpMemFAddr:
4949 ctxt->memop.bytes = ctxt->op_bytes + 2;
4950 goto mem_common;
4951 case OpES:
4952 op->type = OP_IMM;
4953 op->val = VCPU_SREG_ES;
4954 break;
4955 case OpCS:
4956 op->type = OP_IMM;
4957 op->val = VCPU_SREG_CS;
4958 break;
4959 case OpSS:
4960 op->type = OP_IMM;
4961 op->val = VCPU_SREG_SS;
4962 break;
4963 case OpDS:
4964 op->type = OP_IMM;
4965 op->val = VCPU_SREG_DS;
4966 break;
4967 case OpFS:
4968 op->type = OP_IMM;
4969 op->val = VCPU_SREG_FS;
4970 break;
4971 case OpGS:
4972 op->type = OP_IMM;
4973 op->val = VCPU_SREG_GS;
4974 break;
4975 case OpImplicit:
4976 /* Special instructions do their own operand decoding. */
4977 default:
4978 op->type = OP_NONE; /* Disable writeback. */
4979 break;
4980 }
4981
4982 done:
4983 return rc;
4984 }
4985
x86_decode_insn(struct x86_emulate_ctxt * ctxt,void * insn,int insn_len)4986 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
4987 {
4988 int rc = X86EMUL_CONTINUE;
4989 int mode = ctxt->mode;
4990 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
4991 bool op_prefix = false;
4992 bool has_seg_override = false;
4993 struct opcode opcode;
4994 u16 dummy;
4995 struct desc_struct desc;
4996
4997 ctxt->memop.type = OP_NONE;
4998 ctxt->memopp = NULL;
4999 ctxt->_eip = ctxt->eip;
5000 ctxt->fetch.ptr = ctxt->fetch.data;
5001 ctxt->fetch.end = ctxt->fetch.data + insn_len;
5002 ctxt->opcode_len = 1;
5003 if (insn_len > 0)
5004 memcpy(ctxt->fetch.data, insn, insn_len);
5005 else {
5006 rc = __do_insn_fetch_bytes(ctxt, 1);
5007 if (rc != X86EMUL_CONTINUE)
5008 return rc;
5009 }
5010
5011 switch (mode) {
5012 case X86EMUL_MODE_REAL:
5013 case X86EMUL_MODE_VM86:
5014 def_op_bytes = def_ad_bytes = 2;
5015 ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS);
5016 if (desc.d)
5017 def_op_bytes = def_ad_bytes = 4;
5018 break;
5019 case X86EMUL_MODE_PROT16:
5020 def_op_bytes = def_ad_bytes = 2;
5021 break;
5022 case X86EMUL_MODE_PROT32:
5023 def_op_bytes = def_ad_bytes = 4;
5024 break;
5025 #ifdef CONFIG_X86_64
5026 case X86EMUL_MODE_PROT64:
5027 def_op_bytes = 4;
5028 def_ad_bytes = 8;
5029 break;
5030 #endif
5031 default:
5032 return EMULATION_FAILED;
5033 }
5034
5035 ctxt->op_bytes = def_op_bytes;
5036 ctxt->ad_bytes = def_ad_bytes;
5037
5038 /* Legacy prefixes. */
5039 for (;;) {
5040 switch (ctxt->b = insn_fetch(u8, ctxt)) {
5041 case 0x66: /* operand-size override */
5042 op_prefix = true;
5043 /* switch between 2/4 bytes */
5044 ctxt->op_bytes = def_op_bytes ^ 6;
5045 break;
5046 case 0x67: /* address-size override */
5047 if (mode == X86EMUL_MODE_PROT64)
5048 /* switch between 4/8 bytes */
5049 ctxt->ad_bytes = def_ad_bytes ^ 12;
5050 else
5051 /* switch between 2/4 bytes */
5052 ctxt->ad_bytes = def_ad_bytes ^ 6;
5053 break;
5054 case 0x26: /* ES override */
5055 case 0x2e: /* CS override */
5056 case 0x36: /* SS override */
5057 case 0x3e: /* DS override */
5058 has_seg_override = true;
5059 ctxt->seg_override = (ctxt->b >> 3) & 3;
5060 break;
5061 case 0x64: /* FS override */
5062 case 0x65: /* GS override */
5063 has_seg_override = true;
5064 ctxt->seg_override = ctxt->b & 7;
5065 break;
5066 case 0x40 ... 0x4f: /* REX */
5067 if (mode != X86EMUL_MODE_PROT64)
5068 goto done_prefixes;
5069 ctxt->rex_prefix = ctxt->b;
5070 continue;
5071 case 0xf0: /* LOCK */
5072 ctxt->lock_prefix = 1;
5073 break;
5074 case 0xf2: /* REPNE/REPNZ */
5075 case 0xf3: /* REP/REPE/REPZ */
5076 ctxt->rep_prefix = ctxt->b;
5077 break;
5078 default:
5079 goto done_prefixes;
5080 }
5081
5082 /* Any legacy prefix after a REX prefix nullifies its effect. */
5083
5084 ctxt->rex_prefix = 0;
5085 }
5086
5087 done_prefixes:
5088
5089 /* REX prefix. */
5090 if (ctxt->rex_prefix & 8)
5091 ctxt->op_bytes = 8; /* REX.W */
5092
5093 /* Opcode byte(s). */
5094 opcode = opcode_table[ctxt->b];
5095 /* Two-byte opcode? */
5096 if (ctxt->b == 0x0f) {
5097 ctxt->opcode_len = 2;
5098 ctxt->b = insn_fetch(u8, ctxt);
5099 opcode = twobyte_table[ctxt->b];
5100
5101 /* 0F_38 opcode map */
5102 if (ctxt->b == 0x38) {
5103 ctxt->opcode_len = 3;
5104 ctxt->b = insn_fetch(u8, ctxt);
5105 opcode = opcode_map_0f_38[ctxt->b];
5106 }
5107 }
5108 ctxt->d = opcode.flags;
5109
5110 if (ctxt->d & ModRM)
5111 ctxt->modrm = insn_fetch(u8, ctxt);
5112
5113 /* vex-prefix instructions are not implemented */
5114 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
5115 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
5116 ctxt->d = NotImpl;
5117 }
5118
5119 while (ctxt->d & GroupMask) {
5120 switch (ctxt->d & GroupMask) {
5121 case Group:
5122 goffset = (ctxt->modrm >> 3) & 7;
5123 opcode = opcode.u.group[goffset];
5124 break;
5125 case GroupDual:
5126 goffset = (ctxt->modrm >> 3) & 7;
5127 if ((ctxt->modrm >> 6) == 3)
5128 opcode = opcode.u.gdual->mod3[goffset];
5129 else
5130 opcode = opcode.u.gdual->mod012[goffset];
5131 break;
5132 case RMExt:
5133 goffset = ctxt->modrm & 7;
5134 opcode = opcode.u.group[goffset];
5135 break;
5136 case Prefix:
5137 if (ctxt->rep_prefix && op_prefix)
5138 return EMULATION_FAILED;
5139 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
5140 switch (simd_prefix) {
5141 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
5142 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
5143 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
5144 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
5145 }
5146 break;
5147 case Escape:
5148 if (ctxt->modrm > 0xbf)
5149 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
5150 else
5151 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
5152 break;
5153 case InstrDual:
5154 if ((ctxt->modrm >> 6) == 3)
5155 opcode = opcode.u.idual->mod3;
5156 else
5157 opcode = opcode.u.idual->mod012;
5158 break;
5159 case ModeDual:
5160 if (ctxt->mode == X86EMUL_MODE_PROT64)
5161 opcode = opcode.u.mdual->mode64;
5162 else
5163 opcode = opcode.u.mdual->mode32;
5164 break;
5165 default:
5166 return EMULATION_FAILED;
5167 }
5168
5169 ctxt->d &= ~(u64)GroupMask;
5170 ctxt->d |= opcode.flags;
5171 }
5172
5173 /* Unrecognised? */
5174 if (ctxt->d == 0)
5175 return EMULATION_FAILED;
5176
5177 ctxt->execute = opcode.u.execute;
5178
5179 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
5180 return EMULATION_FAILED;
5181
5182 if (unlikely(ctxt->d &
5183 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
5184 No16))) {
5185 /*
5186 * These are copied unconditionally here, and checked unconditionally
5187 * in x86_emulate_insn.
5188 */
5189 ctxt->check_perm = opcode.check_perm;
5190 ctxt->intercept = opcode.intercept;
5191
5192 if (ctxt->d & NotImpl)
5193 return EMULATION_FAILED;
5194
5195 if (mode == X86EMUL_MODE_PROT64) {
5196 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
5197 ctxt->op_bytes = 8;
5198 else if (ctxt->d & NearBranch)
5199 ctxt->op_bytes = 8;
5200 }
5201
5202 if (ctxt->d & Op3264) {
5203 if (mode == X86EMUL_MODE_PROT64)
5204 ctxt->op_bytes = 8;
5205 else
5206 ctxt->op_bytes = 4;
5207 }
5208
5209 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
5210 ctxt->op_bytes = 4;
5211
5212 if (ctxt->d & Sse)
5213 ctxt->op_bytes = 16;
5214 else if (ctxt->d & Mmx)
5215 ctxt->op_bytes = 8;
5216 }
5217
5218 /* ModRM and SIB bytes. */
5219 if (ctxt->d & ModRM) {
5220 rc = decode_modrm(ctxt, &ctxt->memop);
5221 if (!has_seg_override) {
5222 has_seg_override = true;
5223 ctxt->seg_override = ctxt->modrm_seg;
5224 }
5225 } else if (ctxt->d & MemAbs)
5226 rc = decode_abs(ctxt, &ctxt->memop);
5227 if (rc != X86EMUL_CONTINUE)
5228 goto done;
5229
5230 if (!has_seg_override)
5231 ctxt->seg_override = VCPU_SREG_DS;
5232
5233 ctxt->memop.addr.mem.seg = ctxt->seg_override;
5234
5235 /*
5236 * Decode and fetch the source operand: register, memory
5237 * or immediate.
5238 */
5239 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
5240 if (rc != X86EMUL_CONTINUE)
5241 goto done;
5242
5243 /*
5244 * Decode and fetch the second source operand: register, memory
5245 * or immediate.
5246 */
5247 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
5248 if (rc != X86EMUL_CONTINUE)
5249 goto done;
5250
5251 /* Decode and fetch the destination operand: register or memory. */
5252 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
5253
5254 if (ctxt->rip_relative && likely(ctxt->memopp))
5255 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
5256 ctxt->memopp->addr.mem.ea + ctxt->_eip);
5257
5258 done:
5259 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
5260 }
5261
x86_page_table_writing_insn(struct x86_emulate_ctxt * ctxt)5262 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
5263 {
5264 return ctxt->d & PageTable;
5265 }
5266
string_insn_completed(struct x86_emulate_ctxt * ctxt)5267 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
5268 {
5269 /* The second termination condition only applies for REPE
5270 * and REPNE. Test if the repeat string operation prefix is
5271 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
5272 * corresponding termination condition according to:
5273 * - if REPE/REPZ and ZF = 0 then done
5274 * - if REPNE/REPNZ and ZF = 1 then done
5275 */
5276 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
5277 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
5278 && (((ctxt->rep_prefix == REPE_PREFIX) &&
5279 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
5280 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
5281 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
5282 return true;
5283
5284 return false;
5285 }
5286
flush_pending_x87_faults(struct x86_emulate_ctxt * ctxt)5287 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
5288 {
5289 int rc;
5290
5291 ctxt->ops->get_fpu(ctxt);
5292 rc = asm_safe("fwait");
5293 ctxt->ops->put_fpu(ctxt);
5294
5295 if (unlikely(rc != X86EMUL_CONTINUE))
5296 return emulate_exception(ctxt, MF_VECTOR, 0, false);
5297
5298 return X86EMUL_CONTINUE;
5299 }
5300
fetch_possible_mmx_operand(struct x86_emulate_ctxt * ctxt,struct operand * op)5301 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
5302 struct operand *op)
5303 {
5304 if (op->type == OP_MM)
5305 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
5306 }
5307
fastop(struct x86_emulate_ctxt * ctxt,void (* fop)(struct fastop *))5308 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
5309 {
5310 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
5311
5312 if (!(ctxt->d & ByteOp))
5313 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
5314
5315 asm("push %[flags]; popf; " CALL_NOSPEC " ; pushf; pop %[flags]\n"
5316 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
5317 [thunk_target]"+S"(fop), ASM_CALL_CONSTRAINT
5318 : "c"(ctxt->src2.val));
5319
5320 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
5321 if (!fop) /* exception is returned in fop variable */
5322 return emulate_de(ctxt);
5323 return X86EMUL_CONTINUE;
5324 }
5325
init_decode_cache(struct x86_emulate_ctxt * ctxt)5326 void init_decode_cache(struct x86_emulate_ctxt *ctxt)
5327 {
5328 memset(&ctxt->rip_relative, 0,
5329 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
5330
5331 ctxt->io_read.pos = 0;
5332 ctxt->io_read.end = 0;
5333 ctxt->mem_read.end = 0;
5334 }
5335
x86_emulate_insn(struct x86_emulate_ctxt * ctxt)5336 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
5337 {
5338 const struct x86_emulate_ops *ops = ctxt->ops;
5339 int rc = X86EMUL_CONTINUE;
5340 int saved_dst_type = ctxt->dst.type;
5341 unsigned emul_flags;
5342
5343 ctxt->mem_read.pos = 0;
5344
5345 /* LOCK prefix is allowed only with some instructions */
5346 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
5347 rc = emulate_ud(ctxt);
5348 goto done;
5349 }
5350
5351 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
5352 rc = emulate_ud(ctxt);
5353 goto done;
5354 }
5355
5356 emul_flags = ctxt->ops->get_hflags(ctxt);
5357 if (unlikely(ctxt->d &
5358 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
5359 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
5360 (ctxt->d & Undefined)) {
5361 rc = emulate_ud(ctxt);
5362 goto done;
5363 }
5364
5365 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
5366 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
5367 rc = emulate_ud(ctxt);
5368 goto done;
5369 }
5370
5371 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
5372 rc = emulate_nm(ctxt);
5373 goto done;
5374 }
5375
5376 if (ctxt->d & Mmx) {
5377 rc = flush_pending_x87_faults(ctxt);
5378 if (rc != X86EMUL_CONTINUE)
5379 goto done;
5380 /*
5381 * Now that we know the fpu is exception safe, we can fetch
5382 * operands from it.
5383 */
5384 fetch_possible_mmx_operand(ctxt, &ctxt->src);
5385 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
5386 if (!(ctxt->d & Mov))
5387 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
5388 }
5389
5390 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) {
5391 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5392 X86_ICPT_PRE_EXCEPT);
5393 if (rc != X86EMUL_CONTINUE)
5394 goto done;
5395 }
5396
5397 /* Instruction can only be executed in protected mode */
5398 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
5399 rc = emulate_ud(ctxt);
5400 goto done;
5401 }
5402
5403 /* Privileged instruction can be executed only in CPL=0 */
5404 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
5405 if (ctxt->d & PrivUD)
5406 rc = emulate_ud(ctxt);
5407 else
5408 rc = emulate_gp(ctxt, 0);
5409 goto done;
5410 }
5411
5412 /* Do instruction specific permission checks */
5413 if (ctxt->d & CheckPerm) {
5414 rc = ctxt->check_perm(ctxt);
5415 if (rc != X86EMUL_CONTINUE)
5416 goto done;
5417 }
5418
5419 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
5420 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5421 X86_ICPT_POST_EXCEPT);
5422 if (rc != X86EMUL_CONTINUE)
5423 goto done;
5424 }
5425
5426 if (ctxt->rep_prefix && (ctxt->d & String)) {
5427 /* All REP prefixes have the same first termination condition */
5428 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
5429 string_registers_quirk(ctxt);
5430 ctxt->eip = ctxt->_eip;
5431 ctxt->eflags &= ~X86_EFLAGS_RF;
5432 goto done;
5433 }
5434 }
5435 }
5436
5437 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
5438 rc = segmented_read(ctxt, ctxt->src.addr.mem,
5439 ctxt->src.valptr, ctxt->src.bytes);
5440 if (rc != X86EMUL_CONTINUE)
5441 goto done;
5442 ctxt->src.orig_val64 = ctxt->src.val64;
5443 }
5444
5445 if (ctxt->src2.type == OP_MEM) {
5446 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
5447 &ctxt->src2.val, ctxt->src2.bytes);
5448 if (rc != X86EMUL_CONTINUE)
5449 goto done;
5450 }
5451
5452 if ((ctxt->d & DstMask) == ImplicitOps)
5453 goto special_insn;
5454
5455
5456 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
5457 /* optimisation - avoid slow emulated read if Mov */
5458 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
5459 &ctxt->dst.val, ctxt->dst.bytes);
5460 if (rc != X86EMUL_CONTINUE) {
5461 if (!(ctxt->d & NoWrite) &&
5462 rc == X86EMUL_PROPAGATE_FAULT &&
5463 ctxt->exception.vector == PF_VECTOR)
5464 ctxt->exception.error_code |= PFERR_WRITE_MASK;
5465 goto done;
5466 }
5467 }
5468 /* Copy full 64-bit value for CMPXCHG8B. */
5469 ctxt->dst.orig_val64 = ctxt->dst.val64;
5470
5471 special_insn:
5472
5473 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
5474 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5475 X86_ICPT_POST_MEMACCESS);
5476 if (rc != X86EMUL_CONTINUE)
5477 goto done;
5478 }
5479
5480 if (ctxt->rep_prefix && (ctxt->d & String))
5481 ctxt->eflags |= X86_EFLAGS_RF;
5482 else
5483 ctxt->eflags &= ~X86_EFLAGS_RF;
5484
5485 if (ctxt->execute) {
5486 if (ctxt->d & Fastop) {
5487 void (*fop)(struct fastop *) = (void *)ctxt->execute;
5488 rc = fastop(ctxt, fop);
5489 if (rc != X86EMUL_CONTINUE)
5490 goto done;
5491 goto writeback;
5492 }
5493 rc = ctxt->execute(ctxt);
5494 if (rc != X86EMUL_CONTINUE)
5495 goto done;
5496 goto writeback;
5497 }
5498
5499 if (ctxt->opcode_len == 2)
5500 goto twobyte_insn;
5501 else if (ctxt->opcode_len == 3)
5502 goto threebyte_insn;
5503
5504 switch (ctxt->b) {
5505 case 0x70 ... 0x7f: /* jcc (short) */
5506 if (test_cc(ctxt->b, ctxt->eflags))
5507 rc = jmp_rel(ctxt, ctxt->src.val);
5508 break;
5509 case 0x8d: /* lea r16/r32, m */
5510 ctxt->dst.val = ctxt->src.addr.mem.ea;
5511 break;
5512 case 0x90 ... 0x97: /* nop / xchg reg, rax */
5513 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
5514 ctxt->dst.type = OP_NONE;
5515 else
5516 rc = em_xchg(ctxt);
5517 break;
5518 case 0x98: /* cbw/cwde/cdqe */
5519 switch (ctxt->op_bytes) {
5520 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5521 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5522 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
5523 }
5524 break;
5525 case 0xcc: /* int3 */
5526 rc = emulate_int(ctxt, 3);
5527 break;
5528 case 0xcd: /* int n */
5529 rc = emulate_int(ctxt, ctxt->src.val);
5530 break;
5531 case 0xce: /* into */
5532 if (ctxt->eflags & X86_EFLAGS_OF)
5533 rc = emulate_int(ctxt, 4);
5534 break;
5535 case 0xe9: /* jmp rel */
5536 case 0xeb: /* jmp rel short */
5537 rc = jmp_rel(ctxt, ctxt->src.val);
5538 ctxt->dst.type = OP_NONE; /* Disable writeback. */
5539 break;
5540 case 0xf4: /* hlt */
5541 ctxt->ops->halt(ctxt);
5542 break;
5543 case 0xf5: /* cmc */
5544 /* complement carry flag from eflags reg */
5545 ctxt->eflags ^= X86_EFLAGS_CF;
5546 break;
5547 case 0xf8: /* clc */
5548 ctxt->eflags &= ~X86_EFLAGS_CF;
5549 break;
5550 case 0xf9: /* stc */
5551 ctxt->eflags |= X86_EFLAGS_CF;
5552 break;
5553 case 0xfc: /* cld */
5554 ctxt->eflags &= ~X86_EFLAGS_DF;
5555 break;
5556 case 0xfd: /* std */
5557 ctxt->eflags |= X86_EFLAGS_DF;
5558 break;
5559 default:
5560 goto cannot_emulate;
5561 }
5562
5563 if (rc != X86EMUL_CONTINUE)
5564 goto done;
5565
5566 writeback:
5567 if (ctxt->d & SrcWrite) {
5568 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5569 rc = writeback(ctxt, &ctxt->src);
5570 if (rc != X86EMUL_CONTINUE)
5571 goto done;
5572 }
5573 if (!(ctxt->d & NoWrite)) {
5574 rc = writeback(ctxt, &ctxt->dst);
5575 if (rc != X86EMUL_CONTINUE)
5576 goto done;
5577 }
5578
5579 /*
5580 * restore dst type in case the decoding will be reused
5581 * (happens for string instruction )
5582 */
5583 ctxt->dst.type = saved_dst_type;
5584
5585 if ((ctxt->d & SrcMask) == SrcSI)
5586 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
5587
5588 if ((ctxt->d & DstMask) == DstDI)
5589 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
5590
5591 if (ctxt->rep_prefix && (ctxt->d & String)) {
5592 unsigned int count;
5593 struct read_cache *r = &ctxt->io_read;
5594 if ((ctxt->d & SrcMask) == SrcSI)
5595 count = ctxt->src.count;
5596 else
5597 count = ctxt->dst.count;
5598 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
5599
5600 if (!string_insn_completed(ctxt)) {
5601 /*
5602 * Re-enter guest when pio read ahead buffer is empty
5603 * or, if it is not used, after each 1024 iteration.
5604 */
5605 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
5606 (r->end == 0 || r->end != r->pos)) {
5607 /*
5608 * Reset read cache. Usually happens before
5609 * decode, but since instruction is restarted
5610 * we have to do it here.
5611 */
5612 ctxt->mem_read.end = 0;
5613 writeback_registers(ctxt);
5614 return EMULATION_RESTART;
5615 }
5616 goto done; /* skip rip writeback */
5617 }
5618 ctxt->eflags &= ~X86_EFLAGS_RF;
5619 }
5620
5621 ctxt->eip = ctxt->_eip;
5622
5623 done:
5624 if (rc == X86EMUL_PROPAGATE_FAULT) {
5625 WARN_ON(ctxt->exception.vector > 0x1f);
5626 ctxt->have_exception = true;
5627 }
5628 if (rc == X86EMUL_INTERCEPTED)
5629 return EMULATION_INTERCEPTED;
5630
5631 if (rc == X86EMUL_CONTINUE)
5632 writeback_registers(ctxt);
5633
5634 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
5635
5636 twobyte_insn:
5637 switch (ctxt->b) {
5638 case 0x09: /* wbinvd */
5639 (ctxt->ops->wbinvd)(ctxt);
5640 break;
5641 case 0x08: /* invd */
5642 case 0x0d: /* GrpP (prefetch) */
5643 case 0x18: /* Grp16 (prefetch/nop) */
5644 case 0x1f: /* nop */
5645 break;
5646 case 0x20: /* mov cr, reg */
5647 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
5648 break;
5649 case 0x21: /* mov from dr to reg */
5650 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
5651 break;
5652 case 0x40 ... 0x4f: /* cmov */
5653 if (test_cc(ctxt->b, ctxt->eflags))
5654 ctxt->dst.val = ctxt->src.val;
5655 else if (ctxt->op_bytes != 4)
5656 ctxt->dst.type = OP_NONE; /* no writeback */
5657 break;
5658 case 0x80 ... 0x8f: /* jnz rel, etc*/
5659 if (test_cc(ctxt->b, ctxt->eflags))
5660 rc = jmp_rel(ctxt, ctxt->src.val);
5661 break;
5662 case 0x90 ... 0x9f: /* setcc r/m8 */
5663 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
5664 break;
5665 case 0xb6 ... 0xb7: /* movzx */
5666 ctxt->dst.bytes = ctxt->op_bytes;
5667 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
5668 : (u16) ctxt->src.val;
5669 break;
5670 case 0xbe ... 0xbf: /* movsx */
5671 ctxt->dst.bytes = ctxt->op_bytes;
5672 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
5673 (s16) ctxt->src.val;
5674 break;
5675 default:
5676 goto cannot_emulate;
5677 }
5678
5679 threebyte_insn:
5680
5681 if (rc != X86EMUL_CONTINUE)
5682 goto done;
5683
5684 goto writeback;
5685
5686 cannot_emulate:
5687 return EMULATION_FAILED;
5688 }
5689
emulator_invalidate_register_cache(struct x86_emulate_ctxt * ctxt)5690 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5691 {
5692 invalidate_registers(ctxt);
5693 }
5694
emulator_writeback_register_cache(struct x86_emulate_ctxt * ctxt)5695 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5696 {
5697 writeback_registers(ctxt);
5698 }
5699