1 /*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef __MDP5_KMS_H__
19 #define __MDP5_KMS_H__
20
21 #include "msm_drv.h"
22 #include "msm_kms.h"
23 #include "mdp/mdp_kms.h"
24 #include "mdp5_cfg.h" /* must be included before mdp5.xml.h */
25 #include "mdp5.xml.h"
26 #include "mdp5_ctl.h"
27 #include "mdp5_smp.h"
28
29 struct mdp5_kms {
30 struct mdp_kms base;
31
32 struct drm_device *dev;
33
34 struct platform_device *pdev;
35
36 struct mdp5_cfg_handler *cfg;
37 uint32_t caps; /* MDP capabilities (MDP_CAP_XXX bits) */
38
39
40 /* mapper-id used to request GEM buffer mapped for scanout: */
41 int id;
42 struct msm_mmu *mmu;
43
44 struct mdp5_smp *smp;
45 struct mdp5_ctl_manager *ctlm;
46
47 /* io/register spaces: */
48 void __iomem *mmio;
49
50 struct clk *axi_clk;
51 struct clk *ahb_clk;
52 struct clk *core_clk;
53 struct clk *lut_clk;
54 struct clk *vsync_clk;
55
56 /*
57 * lock to protect access to global resources: ie., following register:
58 * - REG_MDP5_DISP_INTF_SEL
59 */
60 spinlock_t resource_lock;
61
62 bool rpm_enabled;
63
64 struct mdp_irq error_handler;
65 };
66 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)
67
68 struct mdp5_plane_state {
69 struct drm_plane_state base;
70
71 /* aligned with property */
72 uint8_t premultiplied;
73 uint8_t zpos;
74 uint8_t alpha;
75
76 /* assigned by crtc blender */
77 enum mdp_mixer_stage_id stage;
78
79 /* some additional transactional status to help us know in the
80 * apply path whether we need to update SMP allocation, and
81 * whether current update is still pending:
82 */
83 bool mode_changed : 1;
84 bool pending : 1;
85 };
86 #define to_mdp5_plane_state(x) \
87 container_of(x, struct mdp5_plane_state, base)
88
89 enum mdp5_intf_mode {
90 MDP5_INTF_MODE_NONE = 0,
91
92 /* Modes used for DSI interface (INTF_DSI type): */
93 MDP5_INTF_DSI_MODE_VIDEO,
94 MDP5_INTF_DSI_MODE_COMMAND,
95
96 /* Modes used for WB interface (INTF_WB type): */
97 MDP5_INTF_WB_MODE_BLOCK,
98 MDP5_INTF_WB_MODE_LINE,
99 };
100
101 struct mdp5_interface {
102 int num; /* display interface number */
103 enum mdp5_intf_type type;
104 enum mdp5_intf_mode mode;
105 };
106
mdp5_write(struct mdp5_kms * mdp5_kms,u32 reg,u32 data)107 static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
108 {
109 msm_writel(data, mdp5_kms->mmio + reg);
110 }
111
mdp5_read(struct mdp5_kms * mdp5_kms,u32 reg)112 static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
113 {
114 return msm_readl(mdp5_kms->mmio + reg);
115 }
116
pipe2name(enum mdp5_pipe pipe)117 static inline const char *pipe2name(enum mdp5_pipe pipe)
118 {
119 static const char *names[] = {
120 #define NAME(n) [SSPP_ ## n] = #n
121 NAME(VIG0), NAME(VIG1), NAME(VIG2),
122 NAME(RGB0), NAME(RGB1), NAME(RGB2),
123 NAME(DMA0), NAME(DMA1),
124 NAME(VIG3), NAME(RGB3),
125 #undef NAME
126 };
127 return names[pipe];
128 }
129
pipe2nclients(enum mdp5_pipe pipe)130 static inline int pipe2nclients(enum mdp5_pipe pipe)
131 {
132 switch (pipe) {
133 case SSPP_RGB0:
134 case SSPP_RGB1:
135 case SSPP_RGB2:
136 case SSPP_RGB3:
137 return 1;
138 default:
139 return 3;
140 }
141 }
142
intf2err(int intf_num)143 static inline uint32_t intf2err(int intf_num)
144 {
145 switch (intf_num) {
146 case 0: return MDP5_IRQ_INTF0_UNDER_RUN;
147 case 1: return MDP5_IRQ_INTF1_UNDER_RUN;
148 case 2: return MDP5_IRQ_INTF2_UNDER_RUN;
149 case 3: return MDP5_IRQ_INTF3_UNDER_RUN;
150 default: return 0;
151 }
152 }
153
154 #define GET_PING_PONG_ID(layer_mixer) ((layer_mixer == 5) ? 3 : layer_mixer)
intf2vblank(int lm,struct mdp5_interface * intf)155 static inline uint32_t intf2vblank(int lm, struct mdp5_interface *intf)
156 {
157 /*
158 * In case of DSI Command Mode, the Ping Pong's read pointer IRQ
159 * acts as a Vblank signal. The Ping Pong buffer used is bound to
160 * layer mixer.
161 */
162
163 if ((intf->type == INTF_DSI) &&
164 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND))
165 return MDP5_IRQ_PING_PONG_0_RD_PTR << GET_PING_PONG_ID(lm);
166
167 if (intf->type == INTF_WB)
168 return MDP5_IRQ_WB_2_DONE;
169
170 switch (intf->num) {
171 case 0: return MDP5_IRQ_INTF0_VSYNC;
172 case 1: return MDP5_IRQ_INTF1_VSYNC;
173 case 2: return MDP5_IRQ_INTF2_VSYNC;
174 case 3: return MDP5_IRQ_INTF3_VSYNC;
175 default: return 0;
176 }
177 }
178
lm2ppdone(int lm)179 static inline uint32_t lm2ppdone(int lm)
180 {
181 return MDP5_IRQ_PING_PONG_0_DONE << GET_PING_PONG_ID(lm);
182 }
183
184 int mdp5_disable(struct mdp5_kms *mdp5_kms);
185 int mdp5_enable(struct mdp5_kms *mdp5_kms);
186
187 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
188 uint32_t old_irqmask);
189 void mdp5_irq_preinstall(struct msm_kms *kms);
190 int mdp5_irq_postinstall(struct msm_kms *kms);
191 void mdp5_irq_uninstall(struct msm_kms *kms);
192 irqreturn_t mdp5_irq(struct msm_kms *kms);
193 int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
194 void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
195 int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms);
196 void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);
197
198 uint32_t mdp5_plane_get_flush(struct drm_plane *plane);
199 void mdp5_plane_complete_flip(struct drm_plane *plane);
200 void mdp5_plane_complete_commit(struct drm_plane *plane,
201 struct drm_plane_state *state);
202 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
203 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
204 enum mdp5_pipe pipe, bool private_plane,
205 uint32_t reg_offset, uint32_t caps);
206
207 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
208
209 int mdp5_crtc_get_lm(struct drm_crtc *crtc);
210 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc,
211 struct mdp5_interface *intf, struct mdp5_ctl *ctl);
212 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc);
213 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
214 struct drm_plane *plane, int id);
215
216 struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
217 struct mdp5_interface *intf, struct mdp5_ctl *ctl);
218 int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
219 struct drm_encoder *slave_encoder);
220 int mdp5_encoder_get_linecount(struct drm_encoder *encoder);
221 u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder);
222
223 #ifdef CONFIG_DRM_MSM_DSI
224 struct drm_encoder *mdp5_cmd_encoder_init(struct drm_device *dev,
225 struct mdp5_interface *intf, struct mdp5_ctl *ctl);
226 int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
227 struct drm_encoder *slave_encoder);
228 #else
mdp5_cmd_encoder_init(struct drm_device * dev,struct mdp5_interface * intf,struct mdp5_ctl * ctl)229 static inline struct drm_encoder *mdp5_cmd_encoder_init(struct drm_device *dev,
230 struct mdp5_interface *intf, struct mdp5_ctl *ctl)
231 {
232 return ERR_PTR(-EINVAL);
233 }
mdp5_cmd_encoder_set_split_display(struct drm_encoder * encoder,struct drm_encoder * slave_encoder)234 static inline int mdp5_cmd_encoder_set_split_display(
235 struct drm_encoder *encoder, struct drm_encoder *slave_encoder)
236 {
237 return -EINVAL;
238 }
239 #endif
240
241 #endif /* __MDP5_KMS_H__ */
242