1 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #ifndef __MGA_DRV_H__
32 #define __MGA_DRV_H__
33
34 #include <drm/drm_legacy.h>
35
36 /* General customization:
37 */
38
39 #define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
40
41 #define DRIVER_NAME "mga"
42 #define DRIVER_DESC "Matrox G200/G400"
43 #define DRIVER_DATE "20051102"
44
45 #define DRIVER_MAJOR 3
46 #define DRIVER_MINOR 2
47 #define DRIVER_PATCHLEVEL 1
48
49 typedef struct drm_mga_primary_buffer {
50 u8 *start;
51 u8 *end;
52 int size;
53
54 u32 tail;
55 int space;
56 volatile long wrapped;
57
58 volatile u32 *status;
59
60 u32 last_flush;
61 u32 last_wrap;
62
63 u32 high_mark;
64 } drm_mga_primary_buffer_t;
65
66 typedef struct drm_mga_freelist {
67 struct drm_mga_freelist *next;
68 struct drm_mga_freelist *prev;
69 drm_mga_age_t age;
70 struct drm_buf *buf;
71 } drm_mga_freelist_t;
72
73 typedef struct {
74 drm_mga_freelist_t *list_entry;
75 int discard;
76 int dispatched;
77 } drm_mga_buf_priv_t;
78
79 typedef struct drm_mga_private {
80 drm_mga_primary_buffer_t prim;
81 drm_mga_sarea_t *sarea_priv;
82
83 drm_mga_freelist_t *head;
84 drm_mga_freelist_t *tail;
85
86 unsigned int warp_pipe;
87 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
88
89 int chipset;
90 int usec_timeout;
91
92 /**
93 * If set, the new DMA initialization sequence was used. This is
94 * primarilly used to select how the driver should uninitialized its
95 * internal DMA structures.
96 */
97 int used_new_dma_init;
98
99 /**
100 * If AGP memory is used for DMA buffers, this will be the value
101 * \c MGA_PAGPXFER. Otherwise, it will be zero (for a PCI transfer).
102 */
103 u32 dma_access;
104
105 /**
106 * If AGP memory is used for DMA buffers, this will be the value
107 * \c MGA_WAGP_ENABLE. Otherwise, it will be zero (for a PCI
108 * transfer).
109 */
110 u32 wagp_enable;
111
112 /**
113 * \name MMIO region parameters.
114 *
115 * \sa drm_mga_private_t::mmio
116 */
117 /*@{ */
118 resource_size_t mmio_base; /**< Bus address of base of MMIO. */
119 resource_size_t mmio_size; /**< Size of the MMIO region. */
120 /*@} */
121
122 u32 clear_cmd;
123 u32 maccess;
124
125 atomic_t vbl_received; /**< Number of vblanks received. */
126 wait_queue_head_t fence_queue;
127 atomic_t last_fence_retired;
128 u32 next_fence_to_post;
129
130 unsigned int fb_cpp;
131 unsigned int front_offset;
132 unsigned int front_pitch;
133 unsigned int back_offset;
134 unsigned int back_pitch;
135
136 unsigned int depth_cpp;
137 unsigned int depth_offset;
138 unsigned int depth_pitch;
139
140 unsigned int texture_offset;
141 unsigned int texture_size;
142
143 drm_local_map_t *sarea;
144 drm_local_map_t *mmio;
145 drm_local_map_t *status;
146 drm_local_map_t *warp;
147 drm_local_map_t *primary;
148 drm_local_map_t *agp_textures;
149
150 unsigned long agp_handle;
151 unsigned int agp_size;
152 } drm_mga_private_t;
153
154 extern const struct drm_ioctl_desc mga_ioctls[];
155 extern int mga_max_ioctl;
156
157 /* mga_dma.c */
158 extern int mga_dma_bootstrap(struct drm_device *dev, void *data,
159 struct drm_file *file_priv);
160 extern int mga_dma_init(struct drm_device *dev, void *data,
161 struct drm_file *file_priv);
162 extern int mga_dma_flush(struct drm_device *dev, void *data,
163 struct drm_file *file_priv);
164 extern int mga_dma_reset(struct drm_device *dev, void *data,
165 struct drm_file *file_priv);
166 extern int mga_dma_buffers(struct drm_device *dev, void *data,
167 struct drm_file *file_priv);
168 extern int mga_driver_load(struct drm_device *dev, unsigned long flags);
169 extern int mga_driver_unload(struct drm_device *dev);
170 extern void mga_driver_lastclose(struct drm_device *dev);
171 extern int mga_driver_dma_quiescent(struct drm_device *dev);
172
173 extern int mga_do_wait_for_idle(drm_mga_private_t *dev_priv);
174
175 extern void mga_do_dma_flush(drm_mga_private_t *dev_priv);
176 extern void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv);
177 extern void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv);
178
179 extern int mga_freelist_put(struct drm_device *dev, struct drm_buf *buf);
180
181 /* mga_warp.c */
182 extern int mga_warp_install_microcode(drm_mga_private_t *dev_priv);
183 extern int mga_warp_init(drm_mga_private_t *dev_priv);
184
185 /* mga_irq.c */
186 extern int mga_enable_vblank(struct drm_device *dev, unsigned int pipe);
187 extern void mga_disable_vblank(struct drm_device *dev, unsigned int pipe);
188 extern u32 mga_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
189 extern int mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence);
190 extern int mga_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
191 extern irqreturn_t mga_driver_irq_handler(int irq, void *arg);
192 extern void mga_driver_irq_preinstall(struct drm_device *dev);
193 extern int mga_driver_irq_postinstall(struct drm_device *dev);
194 extern void mga_driver_irq_uninstall(struct drm_device *dev);
195 extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
196 unsigned long arg);
197
198 #define mga_flush_write_combine() wmb()
199
200 #define MGA_READ8(reg) DRM_READ8(dev_priv->mmio, (reg))
201 #define MGA_READ(reg) DRM_READ32(dev_priv->mmio, (reg))
202 #define MGA_WRITE8(reg, val) DRM_WRITE8(dev_priv->mmio, (reg), (val))
203 #define MGA_WRITE(reg, val) DRM_WRITE32(dev_priv->mmio, (reg), (val))
204
205 #define DWGREG0 0x1c00
206 #define DWGREG0_END 0x1dff
207 #define DWGREG1 0x2c00
208 #define DWGREG1_END 0x2dff
209
210 #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
211 #define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
212 #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
213 #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
214
215 /* ================================================================
216 * Helper macross...
217 */
218
219 #define MGA_EMIT_STATE(dev_priv, dirty) \
220 do { \
221 if ((dirty) & ~MGA_UPLOAD_CLIPRECTS) { \
222 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) \
223 mga_g400_emit_state(dev_priv); \
224 else \
225 mga_g200_emit_state(dev_priv); \
226 } \
227 } while (0)
228
229 #define WRAP_TEST_WITH_RETURN(dev_priv) \
230 do { \
231 if (test_bit(0, &dev_priv->prim.wrapped)) { \
232 if (mga_is_idle(dev_priv)) { \
233 mga_do_dma_wrap_end(dev_priv); \
234 } else if (dev_priv->prim.space < \
235 dev_priv->prim.high_mark) { \
236 if (MGA_DMA_DEBUG) \
237 DRM_INFO("wrap...\n"); \
238 return -EBUSY; \
239 } \
240 } \
241 } while (0)
242
243 #define WRAP_WAIT_WITH_RETURN(dev_priv) \
244 do { \
245 if (test_bit(0, &dev_priv->prim.wrapped)) { \
246 if (mga_do_wait_for_idle(dev_priv) < 0) { \
247 if (MGA_DMA_DEBUG) \
248 DRM_INFO("wrap...\n"); \
249 return -EBUSY; \
250 } \
251 mga_do_dma_wrap_end(dev_priv); \
252 } \
253 } while (0)
254
255 /* ================================================================
256 * Primary DMA command stream
257 */
258
259 #define MGA_VERBOSE 0
260
261 #define DMA_LOCALS unsigned int write; volatile u8 *prim;
262
263 #define DMA_BLOCK_SIZE (5 * sizeof(u32))
264
265 #define BEGIN_DMA(n) \
266 do { \
267 if (MGA_VERBOSE) { \
268 DRM_INFO("BEGIN_DMA(%d)\n", (n)); \
269 DRM_INFO(" space=0x%x req=0x%Zx\n", \
270 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE); \
271 } \
272 prim = dev_priv->prim.start; \
273 write = dev_priv->prim.tail; \
274 } while (0)
275
276 #define BEGIN_DMA_WRAP() \
277 do { \
278 if (MGA_VERBOSE) { \
279 DRM_INFO("BEGIN_DMA()\n"); \
280 DRM_INFO(" space=0x%x\n", dev_priv->prim.space); \
281 } \
282 prim = dev_priv->prim.start; \
283 write = dev_priv->prim.tail; \
284 } while (0)
285
286 #define ADVANCE_DMA() \
287 do { \
288 dev_priv->prim.tail = write; \
289 if (MGA_VERBOSE) \
290 DRM_INFO("ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
291 write, dev_priv->prim.space); \
292 } while (0)
293
294 #define FLUSH_DMA() \
295 do { \
296 if (0) { \
297 DRM_INFO("\n"); \
298 DRM_INFO(" tail=0x%06x head=0x%06lx\n", \
299 dev_priv->prim.tail, \
300 (unsigned long)(MGA_READ(MGA_PRIMADDRESS) - \
301 dev_priv->primary->offset)); \
302 } \
303 if (!test_bit(0, &dev_priv->prim.wrapped)) { \
304 if (dev_priv->prim.space < dev_priv->prim.high_mark) \
305 mga_do_dma_wrap_start(dev_priv); \
306 else \
307 mga_do_dma_flush(dev_priv); \
308 } \
309 } while (0)
310
311 /* Never use this, always use DMA_BLOCK(...) for primary DMA output.
312 */
313 #define DMA_WRITE(offset, val) \
314 do { \
315 if (MGA_VERBOSE) \
316 DRM_INFO(" DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \
317 (u32)(val), write + (offset) * sizeof(u32)); \
318 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
319 } while (0)
320
321 #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \
322 do { \
323 DMA_WRITE(0, ((DMAREG(reg0) << 0) | \
324 (DMAREG(reg1) << 8) | \
325 (DMAREG(reg2) << 16) | \
326 (DMAREG(reg3) << 24))); \
327 DMA_WRITE(1, val0); \
328 DMA_WRITE(2, val1); \
329 DMA_WRITE(3, val2); \
330 DMA_WRITE(4, val3); \
331 write += DMA_BLOCK_SIZE; \
332 } while (0)
333
334 /* Buffer aging via primary DMA stream head pointer.
335 */
336
337 #define SET_AGE(age, h, w) \
338 do { \
339 (age)->head = h; \
340 (age)->wrap = w; \
341 } while (0)
342
343 #define TEST_AGE(age, h, w) ((age)->wrap < w || \
344 ((age)->wrap == w && \
345 (age)->head < h))
346
347 #define AGE_BUFFER(buf_priv) \
348 do { \
349 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
350 if ((buf_priv)->dispatched) { \
351 entry->age.head = (dev_priv->prim.tail + \
352 dev_priv->primary->offset); \
353 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
354 } else { \
355 entry->age.head = 0; \
356 entry->age.wrap = 0; \
357 } \
358 } while (0)
359
360 #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
361 MGA_DWGENGSTS | \
362 MGA_ENDPRDMASTS)
363 #define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
364 MGA_ENDPRDMASTS)
365
366 #define MGA_DMA_DEBUG 0
367
368 /* A reduced set of the mga registers.
369 */
370 #define MGA_CRTC_INDEX 0x1fd4
371 #define MGA_CRTC_DATA 0x1fd5
372
373 /* CRTC11 */
374 #define MGA_VINTCLR (1 << 4)
375 #define MGA_VINTEN (1 << 5)
376
377 #define MGA_ALPHACTRL 0x2c7c
378 #define MGA_AR0 0x1c60
379 #define MGA_AR1 0x1c64
380 #define MGA_AR2 0x1c68
381 #define MGA_AR3 0x1c6c
382 #define MGA_AR4 0x1c70
383 #define MGA_AR5 0x1c74
384 #define MGA_AR6 0x1c78
385
386 #define MGA_CXBNDRY 0x1c80
387 #define MGA_CXLEFT 0x1ca0
388 #define MGA_CXRIGHT 0x1ca4
389
390 #define MGA_DMAPAD 0x1c54
391 #define MGA_DSTORG 0x2cb8
392 #define MGA_DWGCTL 0x1c00
393 # define MGA_OPCOD_MASK (15 << 0)
394 # define MGA_OPCOD_TRAP (4 << 0)
395 # define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
396 # define MGA_OPCOD_BITBLT (8 << 0)
397 # define MGA_OPCOD_ILOAD (9 << 0)
398 # define MGA_ATYPE_MASK (7 << 4)
399 # define MGA_ATYPE_RPL (0 << 4)
400 # define MGA_ATYPE_RSTR (1 << 4)
401 # define MGA_ATYPE_ZI (3 << 4)
402 # define MGA_ATYPE_BLK (4 << 4)
403 # define MGA_ATYPE_I (7 << 4)
404 # define MGA_LINEAR (1 << 7)
405 # define MGA_ZMODE_MASK (7 << 8)
406 # define MGA_ZMODE_NOZCMP (0 << 8)
407 # define MGA_ZMODE_ZE (2 << 8)
408 # define MGA_ZMODE_ZNE (3 << 8)
409 # define MGA_ZMODE_ZLT (4 << 8)
410 # define MGA_ZMODE_ZLTE (5 << 8)
411 # define MGA_ZMODE_ZGT (6 << 8)
412 # define MGA_ZMODE_ZGTE (7 << 8)
413 # define MGA_SOLID (1 << 11)
414 # define MGA_ARZERO (1 << 12)
415 # define MGA_SGNZERO (1 << 13)
416 # define MGA_SHIFTZERO (1 << 14)
417 # define MGA_BOP_MASK (15 << 16)
418 # define MGA_BOP_ZERO (0 << 16)
419 # define MGA_BOP_DST (10 << 16)
420 # define MGA_BOP_SRC (12 << 16)
421 # define MGA_BOP_ONE (15 << 16)
422 # define MGA_TRANS_SHIFT 20
423 # define MGA_TRANS_MASK (15 << 20)
424 # define MGA_BLTMOD_MASK (15 << 25)
425 # define MGA_BLTMOD_BMONOLEF (0 << 25)
426 # define MGA_BLTMOD_BMONOWF (4 << 25)
427 # define MGA_BLTMOD_PLAN (1 << 25)
428 # define MGA_BLTMOD_BFCOL (2 << 25)
429 # define MGA_BLTMOD_BU32BGR (3 << 25)
430 # define MGA_BLTMOD_BU32RGB (7 << 25)
431 # define MGA_BLTMOD_BU24BGR (11 << 25)
432 # define MGA_BLTMOD_BU24RGB (15 << 25)
433 # define MGA_PATTERN (1 << 29)
434 # define MGA_TRANSC (1 << 30)
435 # define MGA_CLIPDIS (1 << 31)
436 #define MGA_DWGSYNC 0x2c4c
437
438 #define MGA_FCOL 0x1c24
439 #define MGA_FIFOSTATUS 0x1e10
440 #define MGA_FOGCOL 0x1cf4
441 #define MGA_FXBNDRY 0x1c84
442 #define MGA_FXLEFT 0x1ca8
443 #define MGA_FXRIGHT 0x1cac
444
445 #define MGA_ICLEAR 0x1e18
446 # define MGA_SOFTRAPICLR (1 << 0)
447 # define MGA_VLINEICLR (1 << 5)
448 #define MGA_IEN 0x1e1c
449 # define MGA_SOFTRAPIEN (1 << 0)
450 # define MGA_VLINEIEN (1 << 5)
451
452 #define MGA_LEN 0x1c5c
453
454 #define MGA_MACCESS 0x1c04
455
456 #define MGA_PITCH 0x1c8c
457 #define MGA_PLNWT 0x1c1c
458 #define MGA_PRIMADDRESS 0x1e58
459 # define MGA_DMA_GENERAL (0 << 0)
460 # define MGA_DMA_BLIT (1 << 0)
461 # define MGA_DMA_VECTOR (2 << 0)
462 # define MGA_DMA_VERTEX (3 << 0)
463 #define MGA_PRIMEND 0x1e5c
464 # define MGA_PRIMNOSTART (1 << 0)
465 # define MGA_PAGPXFER (1 << 1)
466 #define MGA_PRIMPTR 0x1e50
467 # define MGA_PRIMPTREN0 (1 << 0)
468 # define MGA_PRIMPTREN1 (1 << 1)
469
470 #define MGA_RST 0x1e40
471 # define MGA_SOFTRESET (1 << 0)
472 # define MGA_SOFTEXTRST (1 << 1)
473
474 #define MGA_SECADDRESS 0x2c40
475 #define MGA_SECEND 0x2c44
476 #define MGA_SETUPADDRESS 0x2cd0
477 #define MGA_SETUPEND 0x2cd4
478 #define MGA_SGN 0x1c58
479 #define MGA_SOFTRAP 0x2c48
480 #define MGA_SRCORG 0x2cb4
481 # define MGA_SRMMAP_MASK (1 << 0)
482 # define MGA_SRCMAP_FB (0 << 0)
483 # define MGA_SRCMAP_SYSMEM (1 << 0)
484 # define MGA_SRCACC_MASK (1 << 1)
485 # define MGA_SRCACC_PCI (0 << 1)
486 # define MGA_SRCACC_AGP (1 << 1)
487 #define MGA_STATUS 0x1e14
488 # define MGA_SOFTRAPEN (1 << 0)
489 # define MGA_VSYNCPEN (1 << 4)
490 # define MGA_VLINEPEN (1 << 5)
491 # define MGA_DWGENGSTS (1 << 16)
492 # define MGA_ENDPRDMASTS (1 << 17)
493 #define MGA_STENCIL 0x2cc8
494 #define MGA_STENCILCTL 0x2ccc
495
496 #define MGA_TDUALSTAGE0 0x2cf8
497 #define MGA_TDUALSTAGE1 0x2cfc
498 #define MGA_TEXBORDERCOL 0x2c5c
499 #define MGA_TEXCTL 0x2c30
500 #define MGA_TEXCTL2 0x2c3c
501 # define MGA_DUALTEX (1 << 7)
502 # define MGA_G400_TC2_MAGIC (1 << 15)
503 # define MGA_MAP1_ENABLE (1 << 31)
504 #define MGA_TEXFILTER 0x2c58
505 #define MGA_TEXHEIGHT 0x2c2c
506 #define MGA_TEXORG 0x2c24
507 # define MGA_TEXORGMAP_MASK (1 << 0)
508 # define MGA_TEXORGMAP_FB (0 << 0)
509 # define MGA_TEXORGMAP_SYSMEM (1 << 0)
510 # define MGA_TEXORGACC_MASK (1 << 1)
511 # define MGA_TEXORGACC_PCI (0 << 1)
512 # define MGA_TEXORGACC_AGP (1 << 1)
513 #define MGA_TEXORG1 0x2ca4
514 #define MGA_TEXORG2 0x2ca8
515 #define MGA_TEXORG3 0x2cac
516 #define MGA_TEXORG4 0x2cb0
517 #define MGA_TEXTRANS 0x2c34
518 #define MGA_TEXTRANSHIGH 0x2c38
519 #define MGA_TEXWIDTH 0x2c28
520
521 #define MGA_WACCEPTSEQ 0x1dd4
522 #define MGA_WCODEADDR 0x1e6c
523 #define MGA_WFLAG 0x1dc4
524 #define MGA_WFLAG1 0x1de0
525 #define MGA_WFLAGNB 0x1e64
526 #define MGA_WFLAGNB1 0x1e08
527 #define MGA_WGETMSB 0x1dc8
528 #define MGA_WIADDR 0x1dc0
529 #define MGA_WIADDR2 0x1dd8
530 # define MGA_WMODE_SUSPEND (0 << 0)
531 # define MGA_WMODE_RESUME (1 << 0)
532 # define MGA_WMODE_JUMP (2 << 0)
533 # define MGA_WMODE_START (3 << 0)
534 # define MGA_WAGP_ENABLE (1 << 2)
535 #define MGA_WMISC 0x1e70
536 # define MGA_WUCODECACHE_ENABLE (1 << 0)
537 # define MGA_WMASTER_ENABLE (1 << 1)
538 # define MGA_WCACHEFLUSH_ENABLE (1 << 3)
539 #define MGA_WVRTXSZ 0x1dcc
540
541 #define MGA_YBOT 0x1c9c
542 #define MGA_YDST 0x1c90
543 #define MGA_YDSTLEN 0x1c88
544 #define MGA_YDSTORG 0x1c94
545 #define MGA_YTOP 0x1c98
546
547 #define MGA_ZORG 0x1c0c
548
549 /* This finishes the current batch of commands
550 */
551 #define MGA_EXEC 0x0100
552
553 /* AGP PLL encoding (for G200 only).
554 */
555 #define MGA_AGP_PLL 0x1e4c
556 # define MGA_AGP2XPLL_DISABLE (0 << 0)
557 # define MGA_AGP2XPLL_ENABLE (1 << 0)
558
559 /* Warp registers
560 */
561 #define MGA_WR0 0x2d00
562 #define MGA_WR1 0x2d04
563 #define MGA_WR2 0x2d08
564 #define MGA_WR3 0x2d0c
565 #define MGA_WR4 0x2d10
566 #define MGA_WR5 0x2d14
567 #define MGA_WR6 0x2d18
568 #define MGA_WR7 0x2d1c
569 #define MGA_WR8 0x2d20
570 #define MGA_WR9 0x2d24
571 #define MGA_WR10 0x2d28
572 #define MGA_WR11 0x2d2c
573 #define MGA_WR12 0x2d30
574 #define MGA_WR13 0x2d34
575 #define MGA_WR14 0x2d38
576 #define MGA_WR15 0x2d3c
577 #define MGA_WR16 0x2d40
578 #define MGA_WR17 0x2d44
579 #define MGA_WR18 0x2d48
580 #define MGA_WR19 0x2d4c
581 #define MGA_WR20 0x2d50
582 #define MGA_WR21 0x2d54
583 #define MGA_WR22 0x2d58
584 #define MGA_WR23 0x2d5c
585 #define MGA_WR24 0x2d60
586 #define MGA_WR25 0x2d64
587 #define MGA_WR26 0x2d68
588 #define MGA_WR27 0x2d6c
589 #define MGA_WR28 0x2d70
590 #define MGA_WR29 0x2d74
591 #define MGA_WR30 0x2d78
592 #define MGA_WR31 0x2d7c
593 #define MGA_WR32 0x2d80
594 #define MGA_WR33 0x2d84
595 #define MGA_WR34 0x2d88
596 #define MGA_WR35 0x2d8c
597 #define MGA_WR36 0x2d90
598 #define MGA_WR37 0x2d94
599 #define MGA_WR38 0x2d98
600 #define MGA_WR39 0x2d9c
601 #define MGA_WR40 0x2da0
602 #define MGA_WR41 0x2da4
603 #define MGA_WR42 0x2da8
604 #define MGA_WR43 0x2dac
605 #define MGA_WR44 0x2db0
606 #define MGA_WR45 0x2db4
607 #define MGA_WR46 0x2db8
608 #define MGA_WR47 0x2dbc
609 #define MGA_WR48 0x2dc0
610 #define MGA_WR49 0x2dc4
611 #define MGA_WR50 0x2dc8
612 #define MGA_WR51 0x2dcc
613 #define MGA_WR52 0x2dd0
614 #define MGA_WR53 0x2dd4
615 #define MGA_WR54 0x2dd8
616 #define MGA_WR55 0x2ddc
617 #define MGA_WR56 0x2de0
618 #define MGA_WR57 0x2de4
619 #define MGA_WR58 0x2de8
620 #define MGA_WR59 0x2dec
621 #define MGA_WR60 0x2df0
622 #define MGA_WR61 0x2df4
623 #define MGA_WR62 0x2df8
624 #define MGA_WR63 0x2dfc
625 # define MGA_G400_WR_MAGIC (1 << 6)
626 # define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */
627
628 #define MGA_ILOAD_ALIGN 64
629 #define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
630
631 #define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
632 MGA_ATYPE_I | \
633 MGA_ZMODE_NOZCMP | \
634 MGA_ARZERO | \
635 MGA_SGNZERO | \
636 MGA_BOP_SRC | \
637 (15 << MGA_TRANS_SHIFT))
638
639 #define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
640 MGA_ZMODE_NOZCMP | \
641 MGA_SOLID | \
642 MGA_ARZERO | \
643 MGA_SGNZERO | \
644 MGA_SHIFTZERO | \
645 MGA_BOP_SRC | \
646 (0 << MGA_TRANS_SHIFT) | \
647 MGA_BLTMOD_BMONOLEF | \
648 MGA_TRANSC | \
649 MGA_CLIPDIS)
650
651 #define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
652 MGA_ATYPE_RPL | \
653 MGA_SGNZERO | \
654 MGA_SHIFTZERO | \
655 MGA_BOP_SRC | \
656 (0 << MGA_TRANS_SHIFT) | \
657 MGA_BLTMOD_BFCOL | \
658 MGA_CLIPDIS)
659
660 /* Simple idle test.
661 */
mga_is_idle(drm_mga_private_t * dev_priv)662 static __inline__ int mga_is_idle(drm_mga_private_t *dev_priv)
663 {
664 u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
665 return (status == MGA_ENDPRDMASTS);
666 }
667
668 #endif
669