1#include <dt-bindings/clock/tegra124-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra124-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/reset/tegra124-car.h> 7#include <dt-bindings/thermal/tegra124-soctherm.h> 8 9#include "skeleton.dtsi" 10 11/ { 12 compatible = "nvidia,tegra124"; 13 interrupt-parent = <&lic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 pcie-controller@01003000 { 18 compatible = "nvidia,tegra124-pcie"; 19 device_type = "pci"; 20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 23 reg-names = "pads", "afi", "cs"; 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26 interrupt-names = "intr", "msi"; 27 28 #interrupt-cells = <1>; 29 interrupt-map-mask = <0 0 0 0>; 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 31 32 bus-range = <0x00 0xff>; 33 #address-cells = <3>; 34 #size-cells = <2>; 35 36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 41 42 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 43 <&tegra_car TEGRA124_CLK_AFI>, 44 <&tegra_car TEGRA124_CLK_PLL_E>, 45 <&tegra_car TEGRA124_CLK_CML0>; 46 clock-names = "pex", "afi", "pll_e", "cml"; 47 resets = <&tegra_car 70>, 48 <&tegra_car 72>, 49 <&tegra_car 74>; 50 reset-names = "pex", "afi", "pcie_x"; 51 status = "disabled"; 52 53 pci@1,0 { 54 device_type = "pci"; 55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 56 reg = <0x000800 0 0 0 0>; 57 status = "disabled"; 58 59 #address-cells = <3>; 60 #size-cells = <2>; 61 ranges; 62 63 nvidia,num-lanes = <2>; 64 }; 65 66 pci@2,0 { 67 device_type = "pci"; 68 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 69 reg = <0x001000 0 0 0 0>; 70 status = "disabled"; 71 72 #address-cells = <3>; 73 #size-cells = <2>; 74 ranges; 75 76 nvidia,num-lanes = <1>; 77 }; 78 }; 79 80 host1x@50000000 { 81 compatible = "nvidia,tegra124-host1x", "simple-bus"; 82 reg = <0x0 0x50000000 0x0 0x00034000>; 83 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 84 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 85 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 86 resets = <&tegra_car 28>; 87 reset-names = "host1x"; 88 89 #address-cells = <2>; 90 #size-cells = <2>; 91 92 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 93 94 dc@54200000 { 95 compatible = "nvidia,tegra124-dc"; 96 reg = <0x0 0x54200000 0x0 0x00040000>; 97 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&tegra_car TEGRA124_CLK_DISP1>, 99 <&tegra_car TEGRA124_CLK_PLL_P>; 100 clock-names = "dc", "parent"; 101 resets = <&tegra_car 27>; 102 reset-names = "dc"; 103 104 iommus = <&mc TEGRA_SWGROUP_DC>; 105 106 nvidia,head = <0>; 107 }; 108 109 dc@54240000 { 110 compatible = "nvidia,tegra124-dc"; 111 reg = <0x0 0x54240000 0x0 0x00040000>; 112 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 113 clocks = <&tegra_car TEGRA124_CLK_DISP2>, 114 <&tegra_car TEGRA124_CLK_PLL_P>; 115 clock-names = "dc", "parent"; 116 resets = <&tegra_car 26>; 117 reset-names = "dc"; 118 119 iommus = <&mc TEGRA_SWGROUP_DCB>; 120 121 nvidia,head = <1>; 122 }; 123 124 hdmi@54280000 { 125 compatible = "nvidia,tegra124-hdmi"; 126 reg = <0x0 0x54280000 0x0 0x00040000>; 127 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 128 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 129 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 130 clock-names = "hdmi", "parent"; 131 resets = <&tegra_car 51>; 132 reset-names = "hdmi"; 133 status = "disabled"; 134 }; 135 136 sor@54540000 { 137 compatible = "nvidia,tegra124-sor"; 138 reg = <0x0 0x54540000 0x0 0x00040000>; 139 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 141 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 142 <&tegra_car TEGRA124_CLK_PLL_DP>, 143 <&tegra_car TEGRA124_CLK_CLK_M>; 144 clock-names = "sor", "parent", "dp", "safe"; 145 resets = <&tegra_car 182>; 146 reset-names = "sor"; 147 status = "disabled"; 148 }; 149 150 dpaux: dpaux@545c0000 { 151 compatible = "nvidia,tegra124-dpaux"; 152 reg = <0x0 0x545c0000 0x0 0x00040000>; 153 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 155 <&tegra_car TEGRA124_CLK_PLL_DP>; 156 clock-names = "dpaux", "parent"; 157 resets = <&tegra_car 181>; 158 reset-names = "dpaux"; 159 status = "disabled"; 160 }; 161 }; 162 163 gic: interrupt-controller@50041000 { 164 compatible = "arm,cortex-a15-gic"; 165 #interrupt-cells = <3>; 166 interrupt-controller; 167 reg = <0x0 0x50041000 0x0 0x1000>, 168 <0x0 0x50042000 0x0 0x1000>, 169 <0x0 0x50044000 0x0 0x2000>, 170 <0x0 0x50046000 0x0 0x2000>; 171 interrupts = <GIC_PPI 9 172 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 173 interrupt-parent = <&gic>; 174 }; 175 176 /* 177 * Please keep the following 0, notation in place as a former mainline 178 * U-Boot version was looking for that particular notation in order to 179 * perform required fix-ups on that GPU node. 180 */ 181 gpu@0,57000000 { 182 compatible = "nvidia,gk20a"; 183 reg = <0x0 0x57000000 0x0 0x01000000>, 184 <0x0 0x58000000 0x0 0x01000000>; 185 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 187 interrupt-names = "stall", "nonstall"; 188 clocks = <&tegra_car TEGRA124_CLK_GPU>, 189 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 190 clock-names = "gpu", "pwr"; 191 resets = <&tegra_car 184>; 192 reset-names = "gpu"; 193 194 iommus = <&mc TEGRA_SWGROUP_GPU>; 195 196 status = "disabled"; 197 }; 198 199 lic: interrupt-controller@60004000 { 200 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 201 reg = <0x0 0x60004000 0x0 0x100>, 202 <0x0 0x60004100 0x0 0x100>, 203 <0x0 0x60004200 0x0 0x100>, 204 <0x0 0x60004300 0x0 0x100>, 205 <0x0 0x60004400 0x0 0x100>; 206 interrupt-controller; 207 #interrupt-cells = <3>; 208 interrupt-parent = <&gic>; 209 }; 210 211 timer@60005000 { 212 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 213 reg = <0x0 0x60005000 0x0 0x400>; 214 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 221 }; 222 223 tegra_car: clock@60006000 { 224 compatible = "nvidia,tegra124-car"; 225 reg = <0x0 0x60006000 0x0 0x1000>; 226 #clock-cells = <1>; 227 #reset-cells = <1>; 228 nvidia,external-memory-controller = <&emc>; 229 }; 230 231 flow-controller@60007000 { 232 compatible = "nvidia,tegra124-flowctrl"; 233 reg = <0x0 0x60007000 0x0 0x1000>; 234 }; 235 236 actmon@6000c800 { 237 compatible = "nvidia,tegra124-actmon"; 238 reg = <0x0 0x6000c800 0x0 0x400>; 239 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 241 <&tegra_car TEGRA124_CLK_EMC>; 242 clock-names = "actmon", "emc"; 243 resets = <&tegra_car 119>; 244 reset-names = "actmon"; 245 }; 246 247 gpio: gpio@6000d000 { 248 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 249 reg = <0x0 0x6000d000 0x0 0x1000>; 250 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 258 #gpio-cells = <2>; 259 gpio-controller; 260 #interrupt-cells = <2>; 261 interrupt-controller; 262 /* 263 gpio-ranges = <&pinmux 0 0 251>; 264 */ 265 }; 266 267 apbdma: dma@60020000 { 268 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 269 reg = <0x0 0x60020000 0x0 0x1400>; 270 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 303 resets = <&tegra_car 34>; 304 reset-names = "dma"; 305 #dma-cells = <1>; 306 }; 307 308 apbmisc@70000800 { 309 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 310 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 311 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 312 }; 313 314 pinmux: pinmux@70000868 { 315 compatible = "nvidia,tegra124-pinmux"; 316 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 317 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 318 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 319 }; 320 321 /* 322 * There are two serial driver i.e. 8250 based simple serial 323 * driver and APB DMA based serial driver for higher baudrate 324 * and performace. To enable the 8250 based driver, the compatible 325 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 326 * the APB DMA based serial driver, the compatible is 327 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 328 */ 329 uarta: serial@70006000 { 330 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 331 reg = <0x0 0x70006000 0x0 0x40>; 332 reg-shift = <2>; 333 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 335 resets = <&tegra_car 6>; 336 reset-names = "serial"; 337 dmas = <&apbdma 8>, <&apbdma 8>; 338 dma-names = "rx", "tx"; 339 status = "disabled"; 340 }; 341 342 uartb: serial@70006040 { 343 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 344 reg = <0x0 0x70006040 0x0 0x40>; 345 reg-shift = <2>; 346 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 348 resets = <&tegra_car 7>; 349 reset-names = "serial"; 350 dmas = <&apbdma 9>, <&apbdma 9>; 351 dma-names = "rx", "tx"; 352 status = "disabled"; 353 }; 354 355 uartc: serial@70006200 { 356 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 357 reg = <0x0 0x70006200 0x0 0x40>; 358 reg-shift = <2>; 359 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 361 resets = <&tegra_car 55>; 362 reset-names = "serial"; 363 dmas = <&apbdma 10>, <&apbdma 10>; 364 dma-names = "rx", "tx"; 365 status = "disabled"; 366 }; 367 368 uartd: serial@70006300 { 369 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 370 reg = <0x0 0x70006300 0x0 0x40>; 371 reg-shift = <2>; 372 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 374 resets = <&tegra_car 65>; 375 reset-names = "serial"; 376 dmas = <&apbdma 19>, <&apbdma 19>; 377 dma-names = "rx", "tx"; 378 status = "disabled"; 379 }; 380 381 pwm: pwm@7000a000 { 382 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 383 reg = <0x0 0x7000a000 0x0 0x100>; 384 #pwm-cells = <2>; 385 clocks = <&tegra_car TEGRA124_CLK_PWM>; 386 resets = <&tegra_car 17>; 387 reset-names = "pwm"; 388 status = "disabled"; 389 }; 390 391 i2c@7000c000 { 392 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 393 reg = <0x0 0x7000c000 0x0 0x100>; 394 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 398 clock-names = "div-clk"; 399 resets = <&tegra_car 12>; 400 reset-names = "i2c"; 401 dmas = <&apbdma 21>, <&apbdma 21>; 402 dma-names = "rx", "tx"; 403 status = "disabled"; 404 }; 405 406 i2c@7000c400 { 407 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 408 reg = <0x0 0x7000c400 0x0 0x100>; 409 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 413 clock-names = "div-clk"; 414 resets = <&tegra_car 54>; 415 reset-names = "i2c"; 416 dmas = <&apbdma 22>, <&apbdma 22>; 417 dma-names = "rx", "tx"; 418 status = "disabled"; 419 }; 420 421 i2c@7000c500 { 422 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 423 reg = <0x0 0x7000c500 0x0 0x100>; 424 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 428 clock-names = "div-clk"; 429 resets = <&tegra_car 67>; 430 reset-names = "i2c"; 431 dmas = <&apbdma 23>, <&apbdma 23>; 432 dma-names = "rx", "tx"; 433 status = "disabled"; 434 }; 435 436 i2c@7000c700 { 437 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 438 reg = <0x0 0x7000c700 0x0 0x100>; 439 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 443 clock-names = "div-clk"; 444 resets = <&tegra_car 103>; 445 reset-names = "i2c"; 446 dmas = <&apbdma 26>, <&apbdma 26>; 447 dma-names = "rx", "tx"; 448 status = "disabled"; 449 }; 450 451 i2c@7000d000 { 452 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 453 reg = <0x0 0x7000d000 0x0 0x100>; 454 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 458 clock-names = "div-clk"; 459 resets = <&tegra_car 47>; 460 reset-names = "i2c"; 461 dmas = <&apbdma 24>, <&apbdma 24>; 462 dma-names = "rx", "tx"; 463 status = "disabled"; 464 }; 465 466 i2c@7000d100 { 467 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 468 reg = <0x0 0x7000d100 0x0 0x100>; 469 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 473 clock-names = "div-clk"; 474 resets = <&tegra_car 166>; 475 reset-names = "i2c"; 476 dmas = <&apbdma 30>, <&apbdma 30>; 477 dma-names = "rx", "tx"; 478 status = "disabled"; 479 }; 480 481 spi@7000d400 { 482 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 483 reg = <0x0 0x7000d400 0x0 0x200>; 484 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 488 clock-names = "spi"; 489 resets = <&tegra_car 41>; 490 reset-names = "spi"; 491 dmas = <&apbdma 15>, <&apbdma 15>; 492 dma-names = "rx", "tx"; 493 status = "disabled"; 494 }; 495 496 spi@7000d600 { 497 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 498 reg = <0x0 0x7000d600 0x0 0x200>; 499 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 503 clock-names = "spi"; 504 resets = <&tegra_car 44>; 505 reset-names = "spi"; 506 dmas = <&apbdma 16>, <&apbdma 16>; 507 dma-names = "rx", "tx"; 508 status = "disabled"; 509 }; 510 511 spi@7000d800 { 512 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 513 reg = <0x0 0x7000d800 0x0 0x200>; 514 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 518 clock-names = "spi"; 519 resets = <&tegra_car 46>; 520 reset-names = "spi"; 521 dmas = <&apbdma 17>, <&apbdma 17>; 522 dma-names = "rx", "tx"; 523 status = "disabled"; 524 }; 525 526 spi@7000da00 { 527 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 528 reg = <0x0 0x7000da00 0x0 0x200>; 529 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 533 clock-names = "spi"; 534 resets = <&tegra_car 68>; 535 reset-names = "spi"; 536 dmas = <&apbdma 18>, <&apbdma 18>; 537 dma-names = "rx", "tx"; 538 status = "disabled"; 539 }; 540 541 spi@7000dc00 { 542 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 543 reg = <0x0 0x7000dc00 0x0 0x200>; 544 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 548 clock-names = "spi"; 549 resets = <&tegra_car 104>; 550 reset-names = "spi"; 551 dmas = <&apbdma 27>, <&apbdma 27>; 552 dma-names = "rx", "tx"; 553 status = "disabled"; 554 }; 555 556 spi@7000de00 { 557 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 558 reg = <0x0 0x7000de00 0x0 0x200>; 559 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 563 clock-names = "spi"; 564 resets = <&tegra_car 105>; 565 reset-names = "spi"; 566 dmas = <&apbdma 28>, <&apbdma 28>; 567 dma-names = "rx", "tx"; 568 status = "disabled"; 569 }; 570 571 rtc@7000e000 { 572 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 573 reg = <0x0 0x7000e000 0x0 0x100>; 574 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&tegra_car TEGRA124_CLK_RTC>; 576 }; 577 578 pmc@7000e400 { 579 compatible = "nvidia,tegra124-pmc"; 580 reg = <0x0 0x7000e400 0x0 0x400>; 581 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 582 clock-names = "pclk", "clk32k_in"; 583 }; 584 585 fuse@7000f800 { 586 compatible = "nvidia,tegra124-efuse"; 587 reg = <0x0 0x7000f800 0x0 0x400>; 588 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 589 clock-names = "fuse"; 590 resets = <&tegra_car 39>; 591 reset-names = "fuse"; 592 }; 593 594 mc: memory-controller@70019000 { 595 compatible = "nvidia,tegra124-mc"; 596 reg = <0x0 0x70019000 0x0 0x1000>; 597 clocks = <&tegra_car TEGRA124_CLK_MC>; 598 clock-names = "mc"; 599 600 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 601 602 #iommu-cells = <1>; 603 }; 604 605 emc: emc@7001b000 { 606 compatible = "nvidia,tegra124-emc"; 607 reg = <0x0 0x7001b000 0x0 0x1000>; 608 609 nvidia,memory-controller = <&mc>; 610 }; 611 612 sata@70020000 { 613 compatible = "nvidia,tegra124-ahci"; 614 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 615 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 616 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&tegra_car TEGRA124_CLK_SATA>, 618 <&tegra_car TEGRA124_CLK_SATA_OOB>, 619 <&tegra_car TEGRA124_CLK_CML1>, 620 <&tegra_car TEGRA124_CLK_PLL_E>; 621 clock-names = "sata", "sata-oob", "cml1", "pll_e"; 622 resets = <&tegra_car 124>, 623 <&tegra_car 123>, 624 <&tegra_car 129>; 625 reset-names = "sata", "sata-oob", "sata-cold"; 626 status = "disabled"; 627 }; 628 629 hda@70030000 { 630 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; 631 reg = <0x0 0x70030000 0x0 0x10000>; 632 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&tegra_car TEGRA124_CLK_HDA>, 634 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 635 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 636 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 637 resets = <&tegra_car 125>, /* hda */ 638 <&tegra_car 128>, /* hda2hdmi */ 639 <&tegra_car 111>; /* hda2codec_2x */ 640 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 641 status = "disabled"; 642 }; 643 644 usb@70090000 { 645 compatible = "nvidia,tegra124-xusb"; 646 reg = <0x0 0x70090000 0x0 0x8000>, 647 <0x0 0x70098000 0x0 0x1000>, 648 <0x0 0x70099000 0x0 0x1000>; 649 reg-names = "hcd", "fpci", "ipfs"; 650 651 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 653 654 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, 655 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, 656 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, 657 <&tegra_car TEGRA124_CLK_XUSB_SS>, 658 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, 659 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, 660 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, 661 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, 662 <&tegra_car TEGRA124_CLK_PLL_U_480M>, 663 <&tegra_car TEGRA124_CLK_CLK_M>, 664 <&tegra_car TEGRA124_CLK_PLL_E>; 665 clock-names = "xusb_host", "xusb_host_src", 666 "xusb_falcon_src", "xusb_ss", 667 "xusb_ss_div2", "xusb_ss_src", 668 "xusb_hs_src", "xusb_fs_src", 669 "pll_u_480m", "clk_m", "pll_e"; 670 resets = <&tegra_car 89>, <&tegra_car 156>, 671 <&tegra_car 143>; 672 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 673 674 nvidia,xusb-padctl = <&padctl>; 675 676 status = "disabled"; 677 }; 678 679 padctl: padctl@7009f000 { 680 compatible = "nvidia,tegra124-xusb-padctl"; 681 reg = <0x0 0x7009f000 0x0 0x1000>; 682 resets = <&tegra_car 142>; 683 reset-names = "padctl"; 684 685 pads { 686 usb2 { 687 status = "disabled"; 688 689 lanes { 690 usb2-0 { 691 status = "disabled"; 692 #phy-cells = <0>; 693 }; 694 695 usb2-1 { 696 status = "disabled"; 697 #phy-cells = <0>; 698 }; 699 700 usb2-2 { 701 status = "disabled"; 702 #phy-cells = <0>; 703 }; 704 }; 705 }; 706 707 ulpi { 708 status = "disabled"; 709 710 lanes { 711 ulpi-0 { 712 status = "disabled"; 713 #phy-cells = <0>; 714 }; 715 }; 716 }; 717 718 hsic { 719 status = "disabled"; 720 721 lanes { 722 hsic-0 { 723 status = "disabled"; 724 #phy-cells = <0>; 725 }; 726 727 hsic-1 { 728 status = "disabled"; 729 #phy-cells = <0>; 730 }; 731 }; 732 }; 733 734 pcie { 735 status = "disabled"; 736 737 lanes { 738 pcie-0 { 739 status = "disabled"; 740 #phy-cells = <0>; 741 }; 742 743 pcie-1 { 744 status = "disabled"; 745 #phy-cells = <0>; 746 }; 747 748 pcie-2 { 749 status = "disabled"; 750 #phy-cells = <0>; 751 }; 752 753 pcie-3 { 754 status = "disabled"; 755 #phy-cells = <0>; 756 }; 757 758 pcie-4 { 759 status = "disabled"; 760 #phy-cells = <0>; 761 }; 762 }; 763 }; 764 765 sata { 766 status = "disabled"; 767 768 lanes { 769 sata-0 { 770 status = "disabled"; 771 #phy-cells = <0>; 772 }; 773 }; 774 }; 775 }; 776 777 ports { 778 usb2-0 { 779 status = "disabled"; 780 }; 781 782 usb2-1 { 783 status = "disabled"; 784 }; 785 786 usb2-2 { 787 status = "disabled"; 788 }; 789 790 ulpi-0 { 791 status = "disabled"; 792 }; 793 794 hsic-0 { 795 status = "disabled"; 796 }; 797 798 hsic-1 { 799 status = "disabled"; 800 }; 801 802 usb3-0 { 803 status = "disabled"; 804 }; 805 806 usb3-1 { 807 status = "disabled"; 808 }; 809 }; 810 }; 811 812 sdhci@700b0000 { 813 compatible = "nvidia,tegra124-sdhci"; 814 reg = <0x0 0x700b0000 0x0 0x200>; 815 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 816 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 817 resets = <&tegra_car 14>; 818 reset-names = "sdhci"; 819 status = "disabled"; 820 }; 821 822 sdhci@700b0200 { 823 compatible = "nvidia,tegra124-sdhci"; 824 reg = <0x0 0x700b0200 0x0 0x200>; 825 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 827 resets = <&tegra_car 9>; 828 reset-names = "sdhci"; 829 status = "disabled"; 830 }; 831 832 sdhci@700b0400 { 833 compatible = "nvidia,tegra124-sdhci"; 834 reg = <0x0 0x700b0400 0x0 0x200>; 835 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 837 resets = <&tegra_car 69>; 838 reset-names = "sdhci"; 839 status = "disabled"; 840 }; 841 842 sdhci@700b0600 { 843 compatible = "nvidia,tegra124-sdhci"; 844 reg = <0x0 0x700b0600 0x0 0x200>; 845 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 847 resets = <&tegra_car 15>; 848 reset-names = "sdhci"; 849 status = "disabled"; 850 }; 851 852 soctherm: thermal-sensor@700e2000 { 853 compatible = "nvidia,tegra124-soctherm"; 854 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 855 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 856 reg-names = "soctherm-reg", "car-reg"; 857 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 859 <&tegra_car TEGRA124_CLK_SOC_THERM>; 860 clock-names = "tsensor", "soctherm"; 861 resets = <&tegra_car 78>; 862 reset-names = "soctherm"; 863 #thermal-sensor-cells = <1>; 864 865 throttle-cfgs { 866 throttle_heavy: heavy { 867 nvidia,priority = <100>; 868 nvidia,cpu-throt-percent = <85>; 869 870 #cooling-cells = <2>; 871 }; 872 }; 873 }; 874 875 dfll: clock@70110000 { 876 compatible = "nvidia,tegra124-dfll"; 877 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 878 <0 0x70110000 0 0x100>, /* I2C output control */ 879 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 880 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 881 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, 883 <&tegra_car TEGRA124_CLK_DFLL_REF>, 884 <&tegra_car TEGRA124_CLK_I2C5>; 885 clock-names = "soc", "ref", "i2c"; 886 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; 887 reset-names = "dvco"; 888 #clock-cells = <0>; 889 clock-output-names = "dfllCPU_out"; 890 nvidia,sample-rate = <12500>; 891 nvidia,droop-ctrl = <0x00000f00>; 892 nvidia,force-mode = <1>; 893 nvidia,cf = <10>; 894 nvidia,ci = <0>; 895 nvidia,cg = <2>; 896 status = "disabled"; 897 }; 898 899 ahub@70300000 { 900 compatible = "nvidia,tegra124-ahub"; 901 reg = <0x0 0x70300000 0x0 0x200>, 902 <0x0 0x70300800 0x0 0x800>, 903 <0x0 0x70300200 0x0 0x600>; 904 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 906 <&tegra_car TEGRA124_CLK_APBIF>; 907 clock-names = "d_audio", "apbif"; 908 resets = <&tegra_car 106>, /* d_audio */ 909 <&tegra_car 107>, /* apbif */ 910 <&tegra_car 30>, /* i2s0 */ 911 <&tegra_car 11>, /* i2s1 */ 912 <&tegra_car 18>, /* i2s2 */ 913 <&tegra_car 101>, /* i2s3 */ 914 <&tegra_car 102>, /* i2s4 */ 915 <&tegra_car 108>, /* dam0 */ 916 <&tegra_car 109>, /* dam1 */ 917 <&tegra_car 110>, /* dam2 */ 918 <&tegra_car 10>, /* spdif */ 919 <&tegra_car 153>, /* amx */ 920 <&tegra_car 185>, /* amx1 */ 921 <&tegra_car 154>, /* adx */ 922 <&tegra_car 180>, /* adx1 */ 923 <&tegra_car 186>, /* afc0 */ 924 <&tegra_car 187>, /* afc1 */ 925 <&tegra_car 188>, /* afc2 */ 926 <&tegra_car 189>, /* afc3 */ 927 <&tegra_car 190>, /* afc4 */ 928 <&tegra_car 191>; /* afc5 */ 929 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 930 "i2s3", "i2s4", "dam0", "dam1", "dam2", 931 "spdif", "amx", "amx1", "adx", "adx1", 932 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 933 dmas = <&apbdma 1>, <&apbdma 1>, 934 <&apbdma 2>, <&apbdma 2>, 935 <&apbdma 3>, <&apbdma 3>, 936 <&apbdma 4>, <&apbdma 4>, 937 <&apbdma 6>, <&apbdma 6>, 938 <&apbdma 7>, <&apbdma 7>, 939 <&apbdma 12>, <&apbdma 12>, 940 <&apbdma 13>, <&apbdma 13>, 941 <&apbdma 14>, <&apbdma 14>, 942 <&apbdma 29>, <&apbdma 29>; 943 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 944 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 945 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 946 "rx9", "tx9"; 947 ranges; 948 #address-cells = <2>; 949 #size-cells = <2>; 950 951 tegra_i2s0: i2s@70301000 { 952 compatible = "nvidia,tegra124-i2s"; 953 reg = <0x0 0x70301000 0x0 0x100>; 954 nvidia,ahub-cif-ids = <4 4>; 955 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 956 resets = <&tegra_car 30>; 957 reset-names = "i2s"; 958 status = "disabled"; 959 }; 960 961 tegra_i2s1: i2s@70301100 { 962 compatible = "nvidia,tegra124-i2s"; 963 reg = <0x0 0x70301100 0x0 0x100>; 964 nvidia,ahub-cif-ids = <5 5>; 965 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 966 resets = <&tegra_car 11>; 967 reset-names = "i2s"; 968 status = "disabled"; 969 }; 970 971 tegra_i2s2: i2s@70301200 { 972 compatible = "nvidia,tegra124-i2s"; 973 reg = <0x0 0x70301200 0x0 0x100>; 974 nvidia,ahub-cif-ids = <6 6>; 975 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 976 resets = <&tegra_car 18>; 977 reset-names = "i2s"; 978 status = "disabled"; 979 }; 980 981 tegra_i2s3: i2s@70301300 { 982 compatible = "nvidia,tegra124-i2s"; 983 reg = <0x0 0x70301300 0x0 0x100>; 984 nvidia,ahub-cif-ids = <7 7>; 985 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 986 resets = <&tegra_car 101>; 987 reset-names = "i2s"; 988 status = "disabled"; 989 }; 990 991 tegra_i2s4: i2s@70301400 { 992 compatible = "nvidia,tegra124-i2s"; 993 reg = <0x0 0x70301400 0x0 0x100>; 994 nvidia,ahub-cif-ids = <8 8>; 995 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 996 resets = <&tegra_car 102>; 997 reset-names = "i2s"; 998 status = "disabled"; 999 }; 1000 }; 1001 1002 usb@7d000000 { 1003 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1004 reg = <0x0 0x7d000000 0x0 0x4000>; 1005 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1006 phy_type = "utmi"; 1007 clocks = <&tegra_car TEGRA124_CLK_USBD>; 1008 resets = <&tegra_car 22>; 1009 reset-names = "usb"; 1010 nvidia,phy = <&phy1>; 1011 status = "disabled"; 1012 }; 1013 1014 phy1: usb-phy@7d000000 { 1015 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1016 reg = <0x0 0x7d000000 0x0 0x4000>, 1017 <0x0 0x7d000000 0x0 0x4000>; 1018 phy_type = "utmi"; 1019 clocks = <&tegra_car TEGRA124_CLK_USBD>, 1020 <&tegra_car TEGRA124_CLK_PLL_U>, 1021 <&tegra_car TEGRA124_CLK_USBD>; 1022 clock-names = "reg", "pll_u", "utmi-pads"; 1023 resets = <&tegra_car 22>, <&tegra_car 22>; 1024 reset-names = "usb", "utmi-pads"; 1025 nvidia,hssync-start-delay = <0>; 1026 nvidia,idle-wait-delay = <17>; 1027 nvidia,elastic-limit = <16>; 1028 nvidia,term-range-adj = <6>; 1029 nvidia,xcvr-setup = <9>; 1030 nvidia,xcvr-lsfslew = <0>; 1031 nvidia,xcvr-lsrslew = <3>; 1032 nvidia,hssquelch-level = <2>; 1033 nvidia,hsdiscon-level = <5>; 1034 nvidia,xcvr-hsslew = <12>; 1035 nvidia,has-utmi-pad-registers; 1036 status = "disabled"; 1037 }; 1038 1039 usb@7d004000 { 1040 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1041 reg = <0x0 0x7d004000 0x0 0x4000>; 1042 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1043 phy_type = "utmi"; 1044 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1045 resets = <&tegra_car 58>; 1046 reset-names = "usb"; 1047 nvidia,phy = <&phy2>; 1048 status = "disabled"; 1049 }; 1050 1051 phy2: usb-phy@7d004000 { 1052 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1053 reg = <0x0 0x7d004000 0x0 0x4000>, 1054 <0x0 0x7d000000 0x0 0x4000>; 1055 phy_type = "utmi"; 1056 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1057 <&tegra_car TEGRA124_CLK_PLL_U>, 1058 <&tegra_car TEGRA124_CLK_USBD>; 1059 clock-names = "reg", "pll_u", "utmi-pads"; 1060 resets = <&tegra_car 58>, <&tegra_car 22>; 1061 reset-names = "usb", "utmi-pads"; 1062 nvidia,hssync-start-delay = <0>; 1063 nvidia,idle-wait-delay = <17>; 1064 nvidia,elastic-limit = <16>; 1065 nvidia,term-range-adj = <6>; 1066 nvidia,xcvr-setup = <9>; 1067 nvidia,xcvr-lsfslew = <0>; 1068 nvidia,xcvr-lsrslew = <3>; 1069 nvidia,hssquelch-level = <2>; 1070 nvidia,hsdiscon-level = <5>; 1071 nvidia,xcvr-hsslew = <12>; 1072 status = "disabled"; 1073 }; 1074 1075 usb@7d008000 { 1076 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1077 reg = <0x0 0x7d008000 0x0 0x4000>; 1078 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1079 phy_type = "utmi"; 1080 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1081 resets = <&tegra_car 59>; 1082 reset-names = "usb"; 1083 nvidia,phy = <&phy3>; 1084 status = "disabled"; 1085 }; 1086 1087 phy3: usb-phy@7d008000 { 1088 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1089 reg = <0x0 0x7d008000 0x0 0x4000>, 1090 <0x0 0x7d000000 0x0 0x4000>; 1091 phy_type = "utmi"; 1092 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1093 <&tegra_car TEGRA124_CLK_PLL_U>, 1094 <&tegra_car TEGRA124_CLK_USBD>; 1095 clock-names = "reg", "pll_u", "utmi-pads"; 1096 resets = <&tegra_car 59>, <&tegra_car 22>; 1097 reset-names = "usb", "utmi-pads"; 1098 nvidia,hssync-start-delay = <0>; 1099 nvidia,idle-wait-delay = <17>; 1100 nvidia,elastic-limit = <16>; 1101 nvidia,term-range-adj = <6>; 1102 nvidia,xcvr-setup = <9>; 1103 nvidia,xcvr-lsfslew = <0>; 1104 nvidia,xcvr-lsrslew = <3>; 1105 nvidia,hssquelch-level = <2>; 1106 nvidia,hsdiscon-level = <5>; 1107 nvidia,xcvr-hsslew = <12>; 1108 status = "disabled"; 1109 }; 1110 1111 cpus { 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 1115 cpu@0 { 1116 device_type = "cpu"; 1117 compatible = "arm,cortex-a15"; 1118 reg = <0>; 1119 1120 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, 1121 <&tegra_car TEGRA124_CLK_CCLK_LP>, 1122 <&tegra_car TEGRA124_CLK_PLL_X>, 1123 <&tegra_car TEGRA124_CLK_PLL_P>, 1124 <&dfll>; 1125 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; 1126 /* FIXME: what's the actual transition time? */ 1127 clock-latency = <300000>; 1128 }; 1129 1130 cpu@1 { 1131 device_type = "cpu"; 1132 compatible = "arm,cortex-a15"; 1133 reg = <1>; 1134 }; 1135 1136 cpu@2 { 1137 device_type = "cpu"; 1138 compatible = "arm,cortex-a15"; 1139 reg = <2>; 1140 }; 1141 1142 cpu@3 { 1143 device_type = "cpu"; 1144 compatible = "arm,cortex-a15"; 1145 reg = <3>; 1146 }; 1147 }; 1148 1149 pmu { 1150 compatible = "arm,cortex-a15-pmu"; 1151 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1155 interrupt-affinity = <&{/cpus/cpu@0}>, 1156 <&{/cpus/cpu@1}>, 1157 <&{/cpus/cpu@2}>, 1158 <&{/cpus/cpu@3}>; 1159 }; 1160 1161 thermal-zones { 1162 cpu { 1163 polling-delay-passive = <1000>; 1164 polling-delay = <1000>; 1165 1166 thermal-sensors = 1167 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1168 1169 trips { 1170 cpu-shutdown-trip { 1171 temperature = <103000>; 1172 hysteresis = <0>; 1173 type = "critical"; 1174 }; 1175 cpu_throttle_trip: throttle-trip { 1176 temperature = <100000>; 1177 hysteresis = <1000>; 1178 type = "hot"; 1179 }; 1180 }; 1181 1182 cooling-maps { 1183 map0 { 1184 trip = <&cpu_throttle_trip>; 1185 cooling-device = <&throttle_heavy 1 1>; 1186 }; 1187 }; 1188 }; 1189 1190 mem { 1191 polling-delay-passive = <1000>; 1192 polling-delay = <1000>; 1193 1194 thermal-sensors = 1195 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1196 1197 trips { 1198 mem-shutdown-trip { 1199 temperature = <103000>; 1200 hysteresis = <0>; 1201 type = "critical"; 1202 }; 1203 }; 1204 1205 cooling-maps { 1206 /* 1207 * There are currently no cooling maps, 1208 * because there are no cooling devices. 1209 */ 1210 }; 1211 }; 1212 1213 gpu { 1214 polling-delay-passive = <1000>; 1215 polling-delay = <1000>; 1216 1217 thermal-sensors = 1218 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1219 1220 trips { 1221 gpu-shutdown-trip { 1222 temperature = <101000>; 1223 hysteresis = <0>; 1224 type = "critical"; 1225 }; 1226 gpu_throttle_trip: throttle-trip { 1227 temperature = <99000>; 1228 hysteresis = <1000>; 1229 type = "hot"; 1230 }; 1231 }; 1232 1233 cooling-maps { 1234 map0 { 1235 trip = <&gpu_throttle_trip>; 1236 cooling-device = <&throttle_heavy 1 1>; 1237 }; 1238 }; 1239 }; 1240 1241 pllx { 1242 polling-delay-passive = <1000>; 1243 polling-delay = <1000>; 1244 1245 thermal-sensors = 1246 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1247 1248 trips { 1249 pllx-shutdown-trip { 1250 temperature = <103000>; 1251 hysteresis = <0>; 1252 type = "critical"; 1253 }; 1254 }; 1255 1256 cooling-maps { 1257 /* 1258 * There are currently no cooling maps, 1259 * because there are no cooling devices. 1260 */ 1261 }; 1262 }; 1263 }; 1264 1265 timer { 1266 compatible = "arm,armv7-timer"; 1267 interrupts = <GIC_PPI 13 1268 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1269 <GIC_PPI 14 1270 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1271 <GIC_PPI 11 1272 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1273 <GIC_PPI 10 1274 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1275 interrupt-parent = <&gic>; 1276 }; 1277}; 1278