1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 Intel Deutschland GmbH
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
27 * in the file called COPYING.
28 *
29 * Contact Information:
30 * Intel Linux Wireless <linuxwifi@intel.com>
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
37 * Copyright(c) 2016 Intel Deutschland GmbH
38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
67 #include <linux/pci.h>
68 #include <linux/pci-aspm.h>
69 #include <linux/interrupt.h>
70 #include <linux/debugfs.h>
71 #include <linux/sched.h>
72 #include <linux/bitops.h>
73 #include <linux/gfp.h>
74 #include <linux/vmalloc.h>
75 #include <linux/pm_runtime.h>
76
77 #include "iwl-drv.h"
78 #include "iwl-trans.h"
79 #include "iwl-csr.h"
80 #include "iwl-prph.h"
81 #include "iwl-scd.h"
82 #include "iwl-agn-hw.h"
83 #include "iwl-fw-error-dump.h"
84 #include "internal.h"
85 #include "iwl-fh.h"
86
87 /* extended range in FW SRAM */
88 #define IWL_FW_MEM_EXTENDED_START 0x40000
89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
90
iwl_pcie_free_fw_monitor(struct iwl_trans * trans)91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
92 {
93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
94
95 if (!trans_pcie->fw_mon_page)
96 return;
97
98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
100 __free_pages(trans_pcie->fw_mon_page,
101 get_order(trans_pcie->fw_mon_size));
102 trans_pcie->fw_mon_page = NULL;
103 trans_pcie->fw_mon_phys = 0;
104 trans_pcie->fw_mon_size = 0;
105 }
106
iwl_pcie_alloc_fw_monitor(struct iwl_trans * trans,u8 max_power)107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
108 {
109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
110 struct page *page = NULL;
111 dma_addr_t phys;
112 u32 size = 0;
113 u8 power;
114
115 if (!max_power) {
116 /* default max_power is maximum */
117 max_power = 26;
118 } else {
119 max_power += 11;
120 }
121
122 if (WARN(max_power > 26,
123 "External buffer size for monitor is too big %d, check the FW TLV\n",
124 max_power))
125 return;
126
127 if (trans_pcie->fw_mon_page) {
128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
129 trans_pcie->fw_mon_size,
130 DMA_FROM_DEVICE);
131 return;
132 }
133
134 phys = 0;
135 for (power = max_power; power >= 11; power--) {
136 int order;
137
138 size = BIT(power);
139 order = get_order(size);
140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
141 order);
142 if (!page)
143 continue;
144
145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
146 DMA_FROM_DEVICE);
147 if (dma_mapping_error(trans->dev, phys)) {
148 __free_pages(page, order);
149 page = NULL;
150 continue;
151 }
152 IWL_INFO(trans,
153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
154 size, order);
155 break;
156 }
157
158 if (WARN_ON_ONCE(!page))
159 return;
160
161 if (power != max_power)
162 IWL_ERR(trans,
163 "Sorry - debug buffer is only %luK while you requested %luK\n",
164 (unsigned long)BIT(power - 10),
165 (unsigned long)BIT(max_power - 10));
166
167 trans_pcie->fw_mon_page = page;
168 trans_pcie->fw_mon_phys = phys;
169 trans_pcie->fw_mon_size = size;
170 }
171
iwl_trans_pcie_read_shr(struct iwl_trans * trans,u32 reg)172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
173 {
174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
175 ((reg & 0x0000ffff) | (2 << 28)));
176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
177 }
178
iwl_trans_pcie_write_shr(struct iwl_trans * trans,u32 reg,u32 val)179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
180 {
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
183 ((reg & 0x0000ffff) | (3 << 28)));
184 }
185
iwl_pcie_set_pwr(struct iwl_trans * trans,bool vaux)186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
187 {
188 if (trans->cfg->apmg_not_supported)
189 return;
190
191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 ~APMG_PS_CTRL_MSK_PWR_SRC);
195 else
196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
198 ~APMG_PS_CTRL_MSK_PWR_SRC);
199 }
200
201 /* PCI registers */
202 #define PCI_CFG_RETRY_TIMEOUT 0x041
203
iwl_pcie_apm_config(struct iwl_trans * trans)204 static void iwl_pcie_apm_config(struct iwl_trans *trans)
205 {
206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
207 u16 lctl;
208 u16 cap;
209
210 /*
211 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
212 * Check if BIOS (or OS) enabled L1-ASPM on this device.
213 * If so (likely), disable L0S, so device moves directly L0->L1;
214 * costs negligible amount of power savings.
215 * If not (unlikely), enable L0S, so there is at least some
216 * power savings, even without L1.
217 */
218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
221 else
222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
224
225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
227 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
229 trans->ltr_enabled ? "En" : "Dis");
230 }
231
232 /*
233 * Start up NIC's basic functionality after it has been reset
234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
235 * NOTE: This does not load uCode nor start the embedded processor
236 */
iwl_pcie_apm_init(struct iwl_trans * trans)237 static int iwl_pcie_apm_init(struct iwl_trans *trans)
238 {
239 int ret = 0;
240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
241
242 /*
243 * Use "set_bit" below rather than "write", to preserve any hardware
244 * bits already set by default after reset.
245 */
246
247 /* Disable L0S exit timer (platform NMI Work/Around) */
248 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
251
252 /*
253 * Disable L0s without affecting L1;
254 * don't wait for ICH L0s (ICH bug W/A)
255 */
256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
258
259 /* Set FH wait threshold to maximum (HW error during stress W/A) */
260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
261
262 /*
263 * Enable HAP INTA (interrupt from management bus) to
264 * wake device's PCI Express link L1a -> L0s
265 */
266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
268
269 iwl_pcie_apm_config(trans);
270
271 /* Configure analog phase-lock-loop before activating to D0A */
272 if (trans->cfg->base_params->pll_cfg)
273 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
274
275 /*
276 * Set "initialization complete" bit to move adapter from
277 * D0U* --> D0A* (powered-up active) state.
278 */
279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
280
281 /*
282 * Wait for clock stabilization; once stabilized, access to
283 * device-internal resources is supported, e.g. iwl_write_prph()
284 * and accesses to uCode SRAM.
285 */
286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
289 if (ret < 0) {
290 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
291 goto out;
292 }
293
294 if (trans->cfg->host_interrupt_operation_mode) {
295 /*
296 * This is a bit of an abuse - This is needed for 7260 / 3160
297 * only check host_interrupt_operation_mode even if this is
298 * not related to host_interrupt_operation_mode.
299 *
300 * Enable the oscillator to count wake up time for L1 exit. This
301 * consumes slightly more power (100uA) - but allows to be sure
302 * that we wake up from L1 on time.
303 *
304 * This looks weird: read twice the same register, discard the
305 * value, set a bit, and yet again, read that same register
306 * just to discard the value. But that's the way the hardware
307 * seems to like it.
308 */
309 iwl_read_prph(trans, OSC_CLK);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
312 iwl_read_prph(trans, OSC_CLK);
313 iwl_read_prph(trans, OSC_CLK);
314 }
315
316 /*
317 * Enable DMA clock and wait for it to stabilize.
318 *
319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
320 * bits do not disable clocks. This preserves any hardware
321 * bits already set by default in "CLK_CTRL_REG" after reset.
322 */
323 if (!trans->cfg->apmg_not_supported) {
324 iwl_write_prph(trans, APMG_CLK_EN_REG,
325 APMG_CLK_VAL_DMA_CLK_RQT);
326 udelay(20);
327
328 /* Disable L1-Active */
329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
331
332 /* Clear the interrupt in APMG if the NIC is in RFKILL */
333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
334 APMG_RTC_INT_STT_RFKILL);
335 }
336
337 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
338
339 out:
340 return ret;
341 }
342
343 /*
344 * Enable LP XTAL to avoid HW bug where device may consume much power if
345 * FW is not loaded after device reset. LP XTAL is disabled by default
346 * after device HW reset. Do it only if XTAL is fed by internal source.
347 * Configure device's "persistence" mode to avoid resetting XTAL again when
348 * SHRD_HW_RST occurs in S3.
349 */
iwl_pcie_apm_lp_xtal_enable(struct iwl_trans * trans)350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
351 {
352 int ret;
353 u32 apmg_gp1_reg;
354 u32 apmg_xtal_cfg_reg;
355 u32 dl_cfg_reg;
356
357 /* Force XTAL ON */
358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
360
361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
363 usleep_range(1000, 2000);
364
365 /*
366 * Set "initialization complete" bit to move adapter from
367 * D0U* --> D0A* (powered-up active) state.
368 */
369 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
370
371 /*
372 * Wait for clock stabilization; once stabilized, access to
373 * device-internal resources is possible.
374 */
375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
378 25000);
379 if (WARN_ON(ret < 0)) {
380 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
381 /* Release XTAL ON request */
382 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
383 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
384 return;
385 }
386
387 /*
388 * Clear "disable persistence" to avoid LP XTAL resetting when
389 * SHRD_HW_RST is applied in S3.
390 */
391 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
392 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
393
394 /*
395 * Force APMG XTAL to be active to prevent its disabling by HW
396 * caused by APMG idle state.
397 */
398 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
399 SHR_APMG_XTAL_CFG_REG);
400 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
401 apmg_xtal_cfg_reg |
402 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
403
404 /*
405 * Reset entire device again - do controller reset (results in
406 * SHRD_HW_RST). Turn MAC off before proceeding.
407 */
408 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
409 usleep_range(1000, 2000);
410
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
414 SHR_APMG_GP1_WF_XTAL_LP_EN |
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
416
417 /* Clear delay line clock power up */
418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
421
422 /*
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
425 */
426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
428
429 /*
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
432 */
433 iwl_clear_bit(trans, CSR_GP_CNTRL,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
435
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
438 CSR_MONITOR_XTAL_RESOURCES);
439
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
443 udelay(10);
444
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
447 apmg_xtal_cfg_reg &
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
449 }
450
iwl_pcie_apm_stop_master(struct iwl_trans * trans)451 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
452 {
453 int ret = 0;
454
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
457
458 ret = iwl_poll_bit(trans, CSR_RESET,
459 CSR_RESET_REG_FLAG_MASTER_DISABLED,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
461 if (ret < 0)
462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
463
464 IWL_DEBUG_INFO(trans, "stop master\n");
465
466 return ret;
467 }
468
iwl_pcie_apm_stop(struct iwl_trans * trans,bool op_mode_leave)469 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
470 {
471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
472
473 if (op_mode_leave) {
474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
475 iwl_pcie_apm_init(trans);
476
477 /* inform ME that we are leaving */
478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
480 APMG_PCIDEV_STT_VAL_WAKE_ME);
481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
482 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
483 CSR_RESET_LINK_PWR_MGMT_DISABLED);
484 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
485 CSR_HW_IF_CONFIG_REG_PREPARE |
486 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
487 mdelay(1);
488 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
489 CSR_RESET_LINK_PWR_MGMT_DISABLED);
490 }
491 mdelay(5);
492 }
493
494 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
495
496 /* Stop device's DMA activity */
497 iwl_pcie_apm_stop_master(trans);
498
499 if (trans->cfg->lp_xtal_workaround) {
500 iwl_pcie_apm_lp_xtal_enable(trans);
501 return;
502 }
503
504 /* Reset the entire device */
505 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
506 usleep_range(1000, 2000);
507
508 /*
509 * Clear "initialization complete" bit to move adapter from
510 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
511 */
512 iwl_clear_bit(trans, CSR_GP_CNTRL,
513 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
514 }
515
iwl_pcie_nic_init(struct iwl_trans * trans)516 static int iwl_pcie_nic_init(struct iwl_trans *trans)
517 {
518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
519
520 /* nic_init */
521 spin_lock(&trans_pcie->irq_lock);
522 iwl_pcie_apm_init(trans);
523
524 spin_unlock(&trans_pcie->irq_lock);
525
526 iwl_pcie_set_pwr(trans, false);
527
528 iwl_op_mode_nic_config(trans->op_mode);
529
530 /* Allocate the RX queue, or reset if it is already allocated */
531 iwl_pcie_rx_init(trans);
532
533 /* Allocate or reset and init all Tx and Command queues */
534 if (iwl_pcie_tx_init(trans))
535 return -ENOMEM;
536
537 if (trans->cfg->base_params->shadow_reg_enable) {
538 /* enable shadow regs in HW */
539 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
540 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
541 }
542
543 return 0;
544 }
545
546 #define HW_READY_TIMEOUT (50)
547
548 /* Note: returns poll_bit return value, which is >= 0 if success */
iwl_pcie_set_hw_ready(struct iwl_trans * trans)549 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
550 {
551 int ret;
552
553 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
555
556 /* See if we got it */
557 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
558 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
559 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
560 HW_READY_TIMEOUT);
561
562 if (ret >= 0)
563 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
564
565 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
566 return ret;
567 }
568
569 /* Note: returns standard 0/-ERROR code */
iwl_pcie_prepare_card_hw(struct iwl_trans * trans)570 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
571 {
572 int ret;
573 int t = 0;
574 int iter;
575
576 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
577
578 ret = iwl_pcie_set_hw_ready(trans);
579 /* If the card is ready, exit 0 */
580 if (ret >= 0)
581 return 0;
582
583 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
584 CSR_RESET_LINK_PWR_MGMT_DISABLED);
585 usleep_range(1000, 2000);
586
587 for (iter = 0; iter < 10; iter++) {
588 /* If HW is not ready, prepare the conditions to check again */
589 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
590 CSR_HW_IF_CONFIG_REG_PREPARE);
591
592 do {
593 ret = iwl_pcie_set_hw_ready(trans);
594 if (ret >= 0)
595 return 0;
596
597 usleep_range(200, 1000);
598 t += 200;
599 } while (t < 150000);
600 msleep(25);
601 }
602
603 IWL_ERR(trans, "Couldn't prepare the card\n");
604
605 return ret;
606 }
607
608 /*
609 * ucode
610 */
iwl_pcie_load_firmware_chunk_fh(struct iwl_trans * trans,u32 dst_addr,dma_addr_t phy_addr,u32 byte_cnt)611 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
612 u32 dst_addr, dma_addr_t phy_addr,
613 u32 byte_cnt)
614 {
615 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
616 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
617
618 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
619 dst_addr);
620
621 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
622 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
623
624 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
625 (iwl_get_dma_hi_addr(phy_addr)
626 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
627
628 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
629 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
630 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
632
633 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
634 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
636 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
637 }
638
iwl_pcie_load_firmware_chunk_tfh(struct iwl_trans * trans,u32 dst_addr,dma_addr_t phy_addr,u32 byte_cnt)639 static void iwl_pcie_load_firmware_chunk_tfh(struct iwl_trans *trans,
640 u32 dst_addr, dma_addr_t phy_addr,
641 u32 byte_cnt)
642 {
643 /* Stop DMA channel */
644 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, 0);
645
646 /* Configure SRAM address */
647 iwl_write32(trans, TFH_SRV_DMA_CHNL0_SRAM_ADDR,
648 dst_addr);
649
650 /* Configure DRAM address - 64 bit */
651 iwl_write64(trans, TFH_SRV_DMA_CHNL0_DRAM_ADDR, phy_addr);
652
653 /* Configure byte count to transfer */
654 iwl_write32(trans, TFH_SRV_DMA_CHNL0_BC, byte_cnt);
655
656 /* Enable the DRAM2SRAM to start */
657 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, TFH_SRV_DMA_SNOOP |
658 TFH_SRV_DMA_TO_DRIVER |
659 TFH_SRV_DMA_START);
660 }
661
iwl_pcie_load_firmware_chunk(struct iwl_trans * trans,u32 dst_addr,dma_addr_t phy_addr,u32 byte_cnt)662 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
663 u32 dst_addr, dma_addr_t phy_addr,
664 u32 byte_cnt)
665 {
666 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
667 unsigned long flags;
668 int ret;
669
670 trans_pcie->ucode_write_complete = false;
671
672 if (!iwl_trans_grab_nic_access(trans, &flags))
673 return -EIO;
674
675 if (trans->cfg->use_tfh)
676 iwl_pcie_load_firmware_chunk_tfh(trans, dst_addr, phy_addr,
677 byte_cnt);
678 else
679 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
680 byte_cnt);
681 iwl_trans_release_nic_access(trans, &flags);
682
683 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
684 trans_pcie->ucode_write_complete, 5 * HZ);
685 if (!ret) {
686 IWL_ERR(trans, "Failed to load firmware chunk!\n");
687 return -ETIMEDOUT;
688 }
689
690 return 0;
691 }
692
iwl_pcie_load_section(struct iwl_trans * trans,u8 section_num,const struct fw_desc * section)693 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
694 const struct fw_desc *section)
695 {
696 u8 *v_addr;
697 dma_addr_t p_addr;
698 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
699 int ret = 0;
700
701 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
702 section_num);
703
704 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
705 GFP_KERNEL | __GFP_NOWARN);
706 if (!v_addr) {
707 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
708 chunk_sz = PAGE_SIZE;
709 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
710 &p_addr, GFP_KERNEL);
711 if (!v_addr)
712 return -ENOMEM;
713 }
714
715 for (offset = 0; offset < section->len; offset += chunk_sz) {
716 u32 copy_size, dst_addr;
717 bool extended_addr = false;
718
719 copy_size = min_t(u32, chunk_sz, section->len - offset);
720 dst_addr = section->offset + offset;
721
722 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
723 dst_addr <= IWL_FW_MEM_EXTENDED_END)
724 extended_addr = true;
725
726 if (extended_addr)
727 iwl_set_bits_prph(trans, LMPM_CHICK,
728 LMPM_CHICK_EXTENDED_ADDR_SPACE);
729
730 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
731 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
732 copy_size);
733
734 if (extended_addr)
735 iwl_clear_bits_prph(trans, LMPM_CHICK,
736 LMPM_CHICK_EXTENDED_ADDR_SPACE);
737
738 if (ret) {
739 IWL_ERR(trans,
740 "Could not load the [%d] uCode section\n",
741 section_num);
742 break;
743 }
744 }
745
746 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
747 return ret;
748 }
749
750 /*
751 * Driver Takes the ownership on secure machine before FW load
752 * and prevent race with the BT load.
753 * W/A for ROM bug. (should be remove in the next Si step)
754 */
iwl_pcie_rsa_race_bug_wa(struct iwl_trans * trans)755 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
756 {
757 u32 val, loop = 1000;
758
759 /*
760 * Check the RSA semaphore is accessible.
761 * If the HW isn't locked and the rsa semaphore isn't accessible,
762 * we are in trouble.
763 */
764 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
765 if (val & (BIT(1) | BIT(17))) {
766 IWL_DEBUG_INFO(trans,
767 "can't access the RSA semaphore it is write protected\n");
768 return 0;
769 }
770
771 /* take ownership on the AUX IF */
772 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
773 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
774
775 do {
776 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
777 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
778 if (val == 0x1) {
779 iwl_write_prph(trans, RSA_ENABLE, 0);
780 return 0;
781 }
782
783 udelay(10);
784 loop--;
785 } while (loop > 0);
786
787 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
788 return -EIO;
789 }
790
iwl_pcie_load_cpu_sections_8000(struct iwl_trans * trans,const struct fw_img * image,int cpu,int * first_ucode_section)791 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
792 const struct fw_img *image,
793 int cpu,
794 int *first_ucode_section)
795 {
796 int shift_param;
797 int i, ret = 0, sec_num = 0x1;
798 u32 val, last_read_idx = 0;
799
800 if (cpu == 1) {
801 shift_param = 0;
802 *first_ucode_section = 0;
803 } else {
804 shift_param = 16;
805 (*first_ucode_section)++;
806 }
807
808 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
809 last_read_idx = i;
810
811 /*
812 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
813 * CPU1 to CPU2.
814 * PAGING_SEPARATOR_SECTION delimiter - separate between
815 * CPU2 non paged to CPU2 paging sec.
816 */
817 if (!image->sec[i].data ||
818 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
819 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
820 IWL_DEBUG_FW(trans,
821 "Break since Data not valid or Empty section, sec = %d\n",
822 i);
823 break;
824 }
825
826 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
827 if (ret)
828 return ret;
829
830 /* Notify ucode of loaded section number and status */
831 if (trans->cfg->use_tfh) {
832 val = iwl_read_prph(trans, UREG_UCODE_LOAD_STATUS);
833 val = val | (sec_num << shift_param);
834 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, val);
835 } else {
836 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
837 val = val | (sec_num << shift_param);
838 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
839 }
840 sec_num = (sec_num << 1) | 0x1;
841 }
842
843 *first_ucode_section = last_read_idx;
844
845 iwl_enable_interrupts(trans);
846
847 if (trans->cfg->use_tfh) {
848 if (cpu == 1)
849 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
850 0xFFFF);
851 else
852 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
853 0xFFFFFFFF);
854 } else {
855 if (cpu == 1)
856 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
857 0xFFFF);
858 else
859 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
860 0xFFFFFFFF);
861 }
862
863 return 0;
864 }
865
iwl_pcie_load_cpu_sections(struct iwl_trans * trans,const struct fw_img * image,int cpu,int * first_ucode_section)866 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
867 const struct fw_img *image,
868 int cpu,
869 int *first_ucode_section)
870 {
871 int i, ret = 0;
872 u32 last_read_idx = 0;
873
874 if (cpu == 1)
875 *first_ucode_section = 0;
876 else
877 (*first_ucode_section)++;
878
879 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
880 last_read_idx = i;
881
882 /*
883 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
884 * CPU1 to CPU2.
885 * PAGING_SEPARATOR_SECTION delimiter - separate between
886 * CPU2 non paged to CPU2 paging sec.
887 */
888 if (!image->sec[i].data ||
889 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
890 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
891 IWL_DEBUG_FW(trans,
892 "Break since Data not valid or Empty section, sec = %d\n",
893 i);
894 break;
895 }
896
897 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
898 if (ret)
899 return ret;
900 }
901
902 *first_ucode_section = last_read_idx;
903
904 return 0;
905 }
906
iwl_pcie_apply_destination(struct iwl_trans * trans)907 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
908 {
909 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
910 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
911 int i;
912
913 if (dest->version)
914 IWL_ERR(trans,
915 "DBG DEST version is %d - expect issues\n",
916 dest->version);
917
918 IWL_INFO(trans, "Applying debug destination %s\n",
919 get_fw_dbg_mode_string(dest->monitor_mode));
920
921 if (dest->monitor_mode == EXTERNAL_MODE)
922 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
923 else
924 IWL_WARN(trans, "PCI should have external buffer debug\n");
925
926 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
927 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
928 u32 val = le32_to_cpu(dest->reg_ops[i].val);
929
930 switch (dest->reg_ops[i].op) {
931 case CSR_ASSIGN:
932 iwl_write32(trans, addr, val);
933 break;
934 case CSR_SETBIT:
935 iwl_set_bit(trans, addr, BIT(val));
936 break;
937 case CSR_CLEARBIT:
938 iwl_clear_bit(trans, addr, BIT(val));
939 break;
940 case PRPH_ASSIGN:
941 iwl_write_prph(trans, addr, val);
942 break;
943 case PRPH_SETBIT:
944 iwl_set_bits_prph(trans, addr, BIT(val));
945 break;
946 case PRPH_CLEARBIT:
947 iwl_clear_bits_prph(trans, addr, BIT(val));
948 break;
949 case PRPH_BLOCKBIT:
950 if (iwl_read_prph(trans, addr) & BIT(val)) {
951 IWL_ERR(trans,
952 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
953 val, addr);
954 goto monitor;
955 }
956 break;
957 default:
958 IWL_ERR(trans, "FW debug - unknown OP %d\n",
959 dest->reg_ops[i].op);
960 break;
961 }
962 }
963
964 monitor:
965 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
966 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
967 trans_pcie->fw_mon_phys >> dest->base_shift);
968 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
969 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
970 (trans_pcie->fw_mon_phys +
971 trans_pcie->fw_mon_size - 256) >>
972 dest->end_shift);
973 else
974 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
975 (trans_pcie->fw_mon_phys +
976 trans_pcie->fw_mon_size) >>
977 dest->end_shift);
978 }
979 }
980
iwl_pcie_load_given_ucode(struct iwl_trans * trans,const struct fw_img * image)981 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
982 const struct fw_img *image)
983 {
984 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
985 int ret = 0;
986 int first_ucode_section;
987
988 IWL_DEBUG_FW(trans, "working with %s CPU\n",
989 image->is_dual_cpus ? "Dual" : "Single");
990
991 /* load to FW the binary non secured sections of CPU1 */
992 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
993 if (ret)
994 return ret;
995
996 if (image->is_dual_cpus) {
997 /* set CPU2 header address */
998 iwl_write_prph(trans,
999 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1000 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
1001
1002 /* load to FW the binary sections of CPU2 */
1003 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1004 &first_ucode_section);
1005 if (ret)
1006 return ret;
1007 }
1008
1009 /* supported for 7000 only for the moment */
1010 if (iwlwifi_mod_params.fw_monitor &&
1011 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1012 iwl_pcie_alloc_fw_monitor(trans, 0);
1013
1014 if (trans_pcie->fw_mon_size) {
1015 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1016 trans_pcie->fw_mon_phys >> 4);
1017 iwl_write_prph(trans, MON_BUFF_END_ADDR,
1018 (trans_pcie->fw_mon_phys +
1019 trans_pcie->fw_mon_size) >> 4);
1020 }
1021 } else if (trans->dbg_dest_tlv) {
1022 iwl_pcie_apply_destination(trans);
1023 }
1024
1025 iwl_enable_interrupts(trans);
1026
1027 /* release CPU reset */
1028 iwl_write32(trans, CSR_RESET, 0);
1029
1030 return 0;
1031 }
1032
iwl_pcie_load_given_ucode_8000(struct iwl_trans * trans,const struct fw_img * image)1033 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1034 const struct fw_img *image)
1035 {
1036 int ret = 0;
1037 int first_ucode_section;
1038
1039 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1040 image->is_dual_cpus ? "Dual" : "Single");
1041
1042 if (trans->dbg_dest_tlv)
1043 iwl_pcie_apply_destination(trans);
1044
1045 /* TODO: remove in the next Si step */
1046 ret = iwl_pcie_rsa_race_bug_wa(trans);
1047 if (ret)
1048 return ret;
1049
1050 /* configure the ucode to be ready to get the secured image */
1051 /* release CPU reset */
1052 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1053
1054 /* load to FW the binary Secured sections of CPU1 */
1055 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1056 &first_ucode_section);
1057 if (ret)
1058 return ret;
1059
1060 /* load to FW the binary sections of CPU2 */
1061 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1062 &first_ucode_section);
1063 }
1064
_iwl_trans_pcie_stop_device(struct iwl_trans * trans,bool low_power)1065 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1066 {
1067 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1068 bool hw_rfkill, was_hw_rfkill;
1069
1070 lockdep_assert_held(&trans_pcie->mutex);
1071
1072 if (trans_pcie->is_down)
1073 return;
1074
1075 trans_pcie->is_down = true;
1076
1077 was_hw_rfkill = iwl_is_rfkill_set(trans);
1078
1079 /* tell the device to stop sending interrupts */
1080 iwl_disable_interrupts(trans);
1081
1082 /* device going down, Stop using ICT table */
1083 iwl_pcie_disable_ict(trans);
1084
1085 /*
1086 * If a HW restart happens during firmware loading,
1087 * then the firmware loading might call this function
1088 * and later it might be called again due to the
1089 * restart. So don't process again if the device is
1090 * already dead.
1091 */
1092 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1093 IWL_DEBUG_INFO(trans,
1094 "DEVICE_ENABLED bit was set and is now cleared\n");
1095 iwl_pcie_tx_stop(trans);
1096 iwl_pcie_rx_stop(trans);
1097
1098 /* Power-down device's busmaster DMA clocks */
1099 if (!trans->cfg->apmg_not_supported) {
1100 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1101 APMG_CLK_VAL_DMA_CLK_RQT);
1102 udelay(5);
1103 }
1104 }
1105
1106 /* Make sure (redundant) we've released our request to stay awake */
1107 iwl_clear_bit(trans, CSR_GP_CNTRL,
1108 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1109
1110 /* Stop the device, and put it in low power state */
1111 iwl_pcie_apm_stop(trans, false);
1112
1113 /* stop and reset the on-board processor */
1114 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1115 usleep_range(1000, 2000);
1116
1117 /*
1118 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1119 * This is a bug in certain verions of the hardware.
1120 * Certain devices also keep sending HW RF kill interrupt all
1121 * the time, unless the interrupt is ACKed even if the interrupt
1122 * should be masked. Re-ACK all the interrupts here.
1123 */
1124 iwl_disable_interrupts(trans);
1125
1126 /* clear all status bits */
1127 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1128 clear_bit(STATUS_INT_ENABLED, &trans->status);
1129 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1130 clear_bit(STATUS_RFKILL, &trans->status);
1131
1132 /*
1133 * Even if we stop the HW, we still want the RF kill
1134 * interrupt
1135 */
1136 iwl_enable_rfkill_int(trans);
1137
1138 /*
1139 * Check again since the RF kill state may have changed while
1140 * all the interrupts were disabled, in this case we couldn't
1141 * receive the RF kill interrupt and update the state in the
1142 * op_mode.
1143 * Don't call the op_mode if the rkfill state hasn't changed.
1144 * This allows the op_mode to call stop_device from the rfkill
1145 * notification without endless recursion. Under very rare
1146 * circumstances, we might have a small recursion if the rfkill
1147 * state changed exactly now while we were called from stop_device.
1148 * This is very unlikely but can happen and is supported.
1149 */
1150 hw_rfkill = iwl_is_rfkill_set(trans);
1151 if (hw_rfkill)
1152 set_bit(STATUS_RFKILL, &trans->status);
1153 else
1154 clear_bit(STATUS_RFKILL, &trans->status);
1155 if (hw_rfkill != was_hw_rfkill)
1156 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1157
1158 /* re-take ownership to prevent other users from stealing the device */
1159 iwl_pcie_prepare_card_hw(trans);
1160 }
1161
iwl_pcie_synchronize_irqs(struct iwl_trans * trans)1162 static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1163 {
1164 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1165
1166 if (trans_pcie->msix_enabled) {
1167 int i;
1168
1169 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1170 synchronize_irq(trans_pcie->msix_entries[i].vector);
1171 } else {
1172 synchronize_irq(trans_pcie->pci_dev->irq);
1173 }
1174 }
1175
iwl_trans_pcie_start_fw(struct iwl_trans * trans,const struct fw_img * fw,bool run_in_rfkill)1176 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1177 const struct fw_img *fw, bool run_in_rfkill)
1178 {
1179 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1180 bool hw_rfkill;
1181 int ret;
1182
1183 /* This may fail if AMT took ownership of the device */
1184 if (iwl_pcie_prepare_card_hw(trans)) {
1185 IWL_WARN(trans, "Exit HW not ready\n");
1186 ret = -EIO;
1187 goto out;
1188 }
1189
1190 iwl_enable_rfkill_int(trans);
1191
1192 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1193
1194 /*
1195 * We enabled the RF-Kill interrupt and the handler may very
1196 * well be running. Disable the interrupts to make sure no other
1197 * interrupt can be fired.
1198 */
1199 iwl_disable_interrupts(trans);
1200
1201 /* Make sure it finished running */
1202 iwl_pcie_synchronize_irqs(trans);
1203
1204 mutex_lock(&trans_pcie->mutex);
1205
1206 /* If platform's RF_KILL switch is NOT set to KILL */
1207 hw_rfkill = iwl_is_rfkill_set(trans);
1208 if (hw_rfkill)
1209 set_bit(STATUS_RFKILL, &trans->status);
1210 else
1211 clear_bit(STATUS_RFKILL, &trans->status);
1212 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1213 if (hw_rfkill && !run_in_rfkill) {
1214 ret = -ERFKILL;
1215 goto out;
1216 }
1217
1218 /* Someone called stop_device, don't try to start_fw */
1219 if (trans_pcie->is_down) {
1220 IWL_WARN(trans,
1221 "Can't start_fw since the HW hasn't been started\n");
1222 ret = -EIO;
1223 goto out;
1224 }
1225
1226 /* make sure rfkill handshake bits are cleared */
1227 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1228 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1229 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1230
1231 /* clear (again), then enable host interrupts */
1232 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1233
1234 ret = iwl_pcie_nic_init(trans);
1235 if (ret) {
1236 IWL_ERR(trans, "Unable to init nic\n");
1237 goto out;
1238 }
1239
1240 /*
1241 * Now, we load the firmware and don't want to be interrupted, even
1242 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1243 * FH_TX interrupt which is needed to load the firmware). If the
1244 * RF-Kill switch is toggled, we will find out after having loaded
1245 * the firmware and return the proper value to the caller.
1246 */
1247 iwl_enable_fw_load_int(trans);
1248
1249 /* really make sure rfkill handshake bits are cleared */
1250 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1251 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1252
1253 /* Load the given image to the HW */
1254 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1255 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1256 else
1257 ret = iwl_pcie_load_given_ucode(trans, fw);
1258
1259 /* re-check RF-Kill state since we may have missed the interrupt */
1260 hw_rfkill = iwl_is_rfkill_set(trans);
1261 if (hw_rfkill)
1262 set_bit(STATUS_RFKILL, &trans->status);
1263 else
1264 clear_bit(STATUS_RFKILL, &trans->status);
1265
1266 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1267 if (hw_rfkill && !run_in_rfkill)
1268 ret = -ERFKILL;
1269
1270 out:
1271 mutex_unlock(&trans_pcie->mutex);
1272 return ret;
1273 }
1274
iwl_trans_pcie_fw_alive(struct iwl_trans * trans,u32 scd_addr)1275 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1276 {
1277 iwl_pcie_reset_ict(trans);
1278 iwl_pcie_tx_start(trans, scd_addr);
1279 }
1280
iwl_trans_pcie_stop_device(struct iwl_trans * trans,bool low_power)1281 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1282 {
1283 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1284
1285 mutex_lock(&trans_pcie->mutex);
1286 _iwl_trans_pcie_stop_device(trans, low_power);
1287 mutex_unlock(&trans_pcie->mutex);
1288 }
1289
iwl_trans_pcie_rf_kill(struct iwl_trans * trans,bool state)1290 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1291 {
1292 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1293 IWL_TRANS_GET_PCIE_TRANS(trans);
1294
1295 lockdep_assert_held(&trans_pcie->mutex);
1296
1297 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1298 _iwl_trans_pcie_stop_device(trans, true);
1299 }
1300
iwl_trans_pcie_d3_suspend(struct iwl_trans * trans,bool test,bool reset)1301 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1302 bool reset)
1303 {
1304 if (!reset) {
1305 /* Enable persistence mode to avoid reset */
1306 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1307 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1308 }
1309
1310 iwl_disable_interrupts(trans);
1311
1312 /*
1313 * in testing mode, the host stays awake and the
1314 * hardware won't be reset (not even partially)
1315 */
1316 if (test)
1317 return;
1318
1319 iwl_pcie_disable_ict(trans);
1320
1321 iwl_pcie_synchronize_irqs(trans);
1322
1323 iwl_clear_bit(trans, CSR_GP_CNTRL,
1324 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1325 iwl_clear_bit(trans, CSR_GP_CNTRL,
1326 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1327
1328 iwl_pcie_enable_rx_wake(trans, false);
1329
1330 if (reset) {
1331 /*
1332 * reset TX queues -- some of their registers reset during S3
1333 * so if we don't reset everything here the D3 image would try
1334 * to execute some invalid memory upon resume
1335 */
1336 iwl_trans_pcie_tx_reset(trans);
1337 }
1338
1339 iwl_pcie_set_pwr(trans, true);
1340 }
1341
iwl_trans_pcie_d3_resume(struct iwl_trans * trans,enum iwl_d3_status * status,bool test,bool reset)1342 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1343 enum iwl_d3_status *status,
1344 bool test, bool reset)
1345 {
1346 u32 val;
1347 int ret;
1348
1349 if (test) {
1350 iwl_enable_interrupts(trans);
1351 *status = IWL_D3_STATUS_ALIVE;
1352 return 0;
1353 }
1354
1355 iwl_pcie_enable_rx_wake(trans, true);
1356
1357 /*
1358 * Also enables interrupts - none will happen as the device doesn't
1359 * know we're waking it up, only when the opmode actually tells it
1360 * after this call.
1361 */
1362 iwl_pcie_reset_ict(trans);
1363 iwl_enable_interrupts(trans);
1364
1365 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1366 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1367
1368 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1369 udelay(2);
1370
1371 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1372 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1373 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1374 25000);
1375 if (ret < 0) {
1376 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1377 return ret;
1378 }
1379
1380 iwl_pcie_set_pwr(trans, false);
1381
1382 if (!reset) {
1383 iwl_clear_bit(trans, CSR_GP_CNTRL,
1384 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1385 } else {
1386 iwl_trans_pcie_tx_reset(trans);
1387
1388 ret = iwl_pcie_rx_init(trans);
1389 if (ret) {
1390 IWL_ERR(trans,
1391 "Failed to resume the device (RX reset)\n");
1392 return ret;
1393 }
1394 }
1395
1396 val = iwl_read32(trans, CSR_RESET);
1397 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1398 *status = IWL_D3_STATUS_RESET;
1399 else
1400 *status = IWL_D3_STATUS_ALIVE;
1401
1402 return 0;
1403 }
1404
1405 struct iwl_causes_list {
1406 u32 cause_num;
1407 u32 mask_reg;
1408 u8 addr;
1409 };
1410
1411 static struct iwl_causes_list causes_list[] = {
1412 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1413 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1414 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1415 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1416 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1417 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1418 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1419 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1420 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1421 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1422 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1423 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1424 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1425 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1426 };
1427
iwl_pcie_map_non_rx_causes(struct iwl_trans * trans)1428 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1429 {
1430 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1431 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1432 int i;
1433
1434 /*
1435 * Access all non RX causes and map them to the default irq.
1436 * In case we are missing at least one interrupt vector,
1437 * the first interrupt vector will serve non-RX and FBQ causes.
1438 */
1439 for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1440 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1441 iwl_clear_bit(trans, causes_list[i].mask_reg,
1442 causes_list[i].cause_num);
1443 }
1444 }
1445
iwl_pcie_map_rx_causes(struct iwl_trans * trans)1446 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1447 {
1448 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1449 u32 offset =
1450 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1451 u32 val, idx;
1452
1453 /*
1454 * The first RX queue - fallback queue, which is designated for
1455 * management frame, command responses etc, is always mapped to the
1456 * first interrupt vector. The other RX queues are mapped to
1457 * the other (N - 2) interrupt vectors.
1458 */
1459 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1460 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1461 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1462 MSIX_FH_INT_CAUSES_Q(idx - offset));
1463 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1464 }
1465 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1466
1467 val = MSIX_FH_INT_CAUSES_Q(0);
1468 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1469 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1470 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1471
1472 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1473 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1474 }
1475
iwl_pcie_init_msix(struct iwl_trans_pcie * trans_pcie)1476 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1477 {
1478 struct iwl_trans *trans = trans_pcie->trans;
1479
1480 if (!trans_pcie->msix_enabled) {
1481 if (trans->cfg->mq_rx_supported)
1482 iwl_write_prph(trans, UREG_CHICK,
1483 UREG_CHICK_MSI_ENABLE);
1484 return;
1485 }
1486
1487 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1488
1489 /*
1490 * Each cause from the causes list above and the RX causes is
1491 * represented as a byte in the IVAR table. The first nibble
1492 * represents the bound interrupt vector of the cause, the second
1493 * represents no auto clear for this cause. This will be set if its
1494 * interrupt vector is bound to serve other causes.
1495 */
1496 iwl_pcie_map_rx_causes(trans);
1497
1498 iwl_pcie_map_non_rx_causes(trans);
1499
1500 trans_pcie->fh_init_mask =
1501 ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1502 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1503 trans_pcie->hw_init_mask =
1504 ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1505 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1506 }
1507
iwl_pcie_set_interrupt_capa(struct pci_dev * pdev,struct iwl_trans * trans)1508 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1509 struct iwl_trans *trans)
1510 {
1511 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1512 int max_irqs, num_irqs, i, ret, nr_online_cpus;
1513 u16 pci_cmd;
1514
1515 if (!trans->cfg->mq_rx_supported)
1516 goto enable_msi;
1517
1518 nr_online_cpus = num_online_cpus();
1519 max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES);
1520 for (i = 0; i < max_irqs; i++)
1521 trans_pcie->msix_entries[i].entry = i;
1522
1523 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1524 MSIX_MIN_INTERRUPT_VECTORS,
1525 max_irqs);
1526 if (num_irqs < 0) {
1527 IWL_DEBUG_INFO(trans,
1528 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1529 num_irqs);
1530 goto enable_msi;
1531 }
1532 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1533
1534 IWL_DEBUG_INFO(trans,
1535 "MSI-X enabled. %d interrupt vectors were allocated\n",
1536 num_irqs);
1537
1538 /*
1539 * In case the OS provides fewer interrupts than requested, different
1540 * causes will share the same interrupt vector as follows:
1541 * One interrupt less: non rx causes shared with FBQ.
1542 * Two interrupts less: non rx causes shared with FBQ and RSS.
1543 * More than two interrupts: we will use fewer RSS queues.
1544 */
1545 if (num_irqs <= nr_online_cpus) {
1546 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1547 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1548 IWL_SHARED_IRQ_FIRST_RSS;
1549 } else if (num_irqs == nr_online_cpus + 1) {
1550 trans_pcie->trans->num_rx_queues = num_irqs;
1551 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1552 } else {
1553 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1554 }
1555
1556 trans_pcie->alloc_vecs = num_irqs;
1557 trans_pcie->msix_enabled = true;
1558 return;
1559
1560 enable_msi:
1561 ret = pci_enable_msi(pdev);
1562 if (ret) {
1563 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1564 /* enable rfkill interrupt: hw bug w/a */
1565 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1566 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1567 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1568 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1569 }
1570 }
1571 }
1572
iwl_pcie_irq_set_affinity(struct iwl_trans * trans)1573 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1574 {
1575 int iter_rx_q, i, ret, cpu, offset;
1576 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1577
1578 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1579 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1580 offset = 1 + i;
1581 for (; i < iter_rx_q ; i++) {
1582 /*
1583 * Get the cpu prior to the place to search
1584 * (i.e. return will be > i - 1).
1585 */
1586 cpu = cpumask_next(i - offset, cpu_online_mask);
1587 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1588 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1589 &trans_pcie->affinity_mask[i]);
1590 if (ret)
1591 IWL_ERR(trans_pcie->trans,
1592 "Failed to set affinity mask for IRQ %d\n",
1593 i);
1594 }
1595 }
1596
iwl_pcie_init_msix_handler(struct pci_dev * pdev,struct iwl_trans_pcie * trans_pcie)1597 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1598 struct iwl_trans_pcie *trans_pcie)
1599 {
1600 int i;
1601
1602 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1603 int ret;
1604 struct msix_entry *msix_entry;
1605
1606 msix_entry = &trans_pcie->msix_entries[i];
1607 ret = devm_request_threaded_irq(&pdev->dev,
1608 msix_entry->vector,
1609 iwl_pcie_msix_isr,
1610 (i == trans_pcie->def_irq) ?
1611 iwl_pcie_irq_msix_handler :
1612 iwl_pcie_irq_rx_msix_handler,
1613 IRQF_SHARED,
1614 DRV_NAME,
1615 msix_entry);
1616 if (ret) {
1617 IWL_ERR(trans_pcie->trans,
1618 "Error allocating IRQ %d\n", i);
1619
1620 return ret;
1621 }
1622 }
1623 iwl_pcie_irq_set_affinity(trans_pcie->trans);
1624
1625 return 0;
1626 }
1627
_iwl_trans_pcie_start_hw(struct iwl_trans * trans,bool low_power)1628 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1629 {
1630 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1631 bool hw_rfkill;
1632 int err;
1633
1634 lockdep_assert_held(&trans_pcie->mutex);
1635
1636 err = iwl_pcie_prepare_card_hw(trans);
1637 if (err) {
1638 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1639 return err;
1640 }
1641
1642 /* Reset the entire device */
1643 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1644 usleep_range(1000, 2000);
1645
1646 iwl_pcie_apm_init(trans);
1647
1648 iwl_pcie_init_msix(trans_pcie);
1649 /* From now on, the op_mode will be kept updated about RF kill state */
1650 iwl_enable_rfkill_int(trans);
1651
1652 /* Set is_down to false here so that...*/
1653 trans_pcie->is_down = false;
1654
1655 hw_rfkill = iwl_is_rfkill_set(trans);
1656 if (hw_rfkill)
1657 set_bit(STATUS_RFKILL, &trans->status);
1658 else
1659 clear_bit(STATUS_RFKILL, &trans->status);
1660 /* ... rfkill can call stop_device and set it false if needed */
1661 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1662
1663 /* Make sure we sync here, because we'll need full access later */
1664 if (low_power)
1665 pm_runtime_resume(trans->dev);
1666
1667 return 0;
1668 }
1669
iwl_trans_pcie_start_hw(struct iwl_trans * trans,bool low_power)1670 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1671 {
1672 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1673 int ret;
1674
1675 mutex_lock(&trans_pcie->mutex);
1676 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1677 mutex_unlock(&trans_pcie->mutex);
1678
1679 return ret;
1680 }
1681
iwl_trans_pcie_op_mode_leave(struct iwl_trans * trans)1682 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1683 {
1684 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1685
1686 mutex_lock(&trans_pcie->mutex);
1687
1688 /* disable interrupts - don't enable HW RF kill interrupt */
1689 iwl_disable_interrupts(trans);
1690
1691 iwl_pcie_apm_stop(trans, true);
1692
1693 iwl_disable_interrupts(trans);
1694
1695 iwl_pcie_disable_ict(trans);
1696
1697 mutex_unlock(&trans_pcie->mutex);
1698
1699 iwl_pcie_synchronize_irqs(trans);
1700 }
1701
iwl_trans_pcie_write8(struct iwl_trans * trans,u32 ofs,u8 val)1702 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1703 {
1704 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1705 }
1706
iwl_trans_pcie_write32(struct iwl_trans * trans,u32 ofs,u32 val)1707 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1708 {
1709 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1710 }
1711
iwl_trans_pcie_read32(struct iwl_trans * trans,u32 ofs)1712 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1713 {
1714 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1715 }
1716
iwl_trans_pcie_read_prph(struct iwl_trans * trans,u32 reg)1717 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1718 {
1719 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1720 ((reg & 0x000FFFFF) | (3 << 24)));
1721 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1722 }
1723
iwl_trans_pcie_write_prph(struct iwl_trans * trans,u32 addr,u32 val)1724 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1725 u32 val)
1726 {
1727 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1728 ((addr & 0x000FFFFF) | (3 << 24)));
1729 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1730 }
1731
iwl_trans_pcie_configure(struct iwl_trans * trans,const struct iwl_trans_config * trans_cfg)1732 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1733 const struct iwl_trans_config *trans_cfg)
1734 {
1735 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1736
1737 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1738 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1739 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1740 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1741 trans_pcie->n_no_reclaim_cmds = 0;
1742 else
1743 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1744 if (trans_pcie->n_no_reclaim_cmds)
1745 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1746 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1747
1748 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1749 trans_pcie->rx_page_order =
1750 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1751
1752 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1753 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1754 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1755
1756 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1757 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1758
1759 trans->command_groups = trans_cfg->command_groups;
1760 trans->command_groups_size = trans_cfg->command_groups_size;
1761
1762 /* Initialize NAPI here - it should be before registering to mac80211
1763 * in the opmode but after the HW struct is allocated.
1764 * As this function may be called again in some corner cases don't
1765 * do anything if NAPI was already initialized.
1766 */
1767 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1768 init_dummy_netdev(&trans_pcie->napi_dev);
1769 }
1770
iwl_trans_pcie_free(struct iwl_trans * trans)1771 void iwl_trans_pcie_free(struct iwl_trans *trans)
1772 {
1773 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1774 int i;
1775
1776 iwl_pcie_synchronize_irqs(trans);
1777
1778 iwl_pcie_tx_free(trans);
1779 iwl_pcie_rx_free(trans);
1780
1781 if (trans_pcie->msix_enabled) {
1782 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1783 irq_set_affinity_hint(
1784 trans_pcie->msix_entries[i].vector,
1785 NULL);
1786 }
1787
1788 trans_pcie->msix_enabled = false;
1789 } else {
1790 iwl_pcie_free_ict(trans);
1791 }
1792
1793 iwl_pcie_free_fw_monitor(trans);
1794
1795 for_each_possible_cpu(i) {
1796 struct iwl_tso_hdr_page *p =
1797 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1798
1799 if (p->page)
1800 __free_page(p->page);
1801 }
1802
1803 free_percpu(trans_pcie->tso_hdr_page);
1804 mutex_destroy(&trans_pcie->mutex);
1805 iwl_trans_free(trans);
1806 }
1807
iwl_trans_pcie_set_pmi(struct iwl_trans * trans,bool state)1808 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1809 {
1810 if (state)
1811 set_bit(STATUS_TPOWER_PMI, &trans->status);
1812 else
1813 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1814 }
1815
iwl_trans_pcie_grab_nic_access(struct iwl_trans * trans,unsigned long * flags)1816 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1817 unsigned long *flags)
1818 {
1819 int ret;
1820 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1821
1822 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1823
1824 if (trans_pcie->cmd_hold_nic_awake)
1825 goto out;
1826
1827 /* this bit wakes up the NIC */
1828 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1829 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1830 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1831 udelay(2);
1832
1833 /*
1834 * These bits say the device is running, and should keep running for
1835 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1836 * but they do not indicate that embedded SRAM is restored yet;
1837 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1838 * to/from host DRAM when sleeping/waking for power-saving.
1839 * Each direction takes approximately 1/4 millisecond; with this
1840 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1841 * series of register accesses are expected (e.g. reading Event Log),
1842 * to keep device from sleeping.
1843 *
1844 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1845 * SRAM is okay/restored. We don't check that here because this call
1846 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1847 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1848 *
1849 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1850 * and do not save/restore SRAM when power cycling.
1851 */
1852 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1853 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1854 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1855 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1856 if (unlikely(ret < 0)) {
1857 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1858 WARN_ONCE(1,
1859 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1860 iwl_read32(trans, CSR_GP_CNTRL));
1861 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1862 return false;
1863 }
1864
1865 out:
1866 /*
1867 * Fool sparse by faking we release the lock - sparse will
1868 * track nic_access anyway.
1869 */
1870 __release(&trans_pcie->reg_lock);
1871 return true;
1872 }
1873
iwl_trans_pcie_release_nic_access(struct iwl_trans * trans,unsigned long * flags)1874 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1875 unsigned long *flags)
1876 {
1877 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1878
1879 lockdep_assert_held(&trans_pcie->reg_lock);
1880
1881 /*
1882 * Fool sparse by faking we acquiring the lock - sparse will
1883 * track nic_access anyway.
1884 */
1885 __acquire(&trans_pcie->reg_lock);
1886
1887 if (trans_pcie->cmd_hold_nic_awake)
1888 goto out;
1889
1890 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1891 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1892 /*
1893 * Above we read the CSR_GP_CNTRL register, which will flush
1894 * any previous writes, but we need the write that clears the
1895 * MAC_ACCESS_REQ bit to be performed before any other writes
1896 * scheduled on different CPUs (after we drop reg_lock).
1897 */
1898 mmiowb();
1899 out:
1900 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1901 }
1902
iwl_trans_pcie_read_mem(struct iwl_trans * trans,u32 addr,void * buf,int dwords)1903 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1904 void *buf, int dwords)
1905 {
1906 unsigned long flags;
1907 int offs, ret = 0;
1908 u32 *vals = buf;
1909
1910 if (iwl_trans_grab_nic_access(trans, &flags)) {
1911 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1912 for (offs = 0; offs < dwords; offs++)
1913 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1914 iwl_trans_release_nic_access(trans, &flags);
1915 } else {
1916 ret = -EBUSY;
1917 }
1918 return ret;
1919 }
1920
iwl_trans_pcie_write_mem(struct iwl_trans * trans,u32 addr,const void * buf,int dwords)1921 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1922 const void *buf, int dwords)
1923 {
1924 unsigned long flags;
1925 int offs, ret = 0;
1926 const u32 *vals = buf;
1927
1928 if (iwl_trans_grab_nic_access(trans, &flags)) {
1929 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1930 for (offs = 0; offs < dwords; offs++)
1931 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1932 vals ? vals[offs] : 0);
1933 iwl_trans_release_nic_access(trans, &flags);
1934 } else {
1935 ret = -EBUSY;
1936 }
1937 return ret;
1938 }
1939
iwl_trans_pcie_freeze_txq_timer(struct iwl_trans * trans,unsigned long txqs,bool freeze)1940 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1941 unsigned long txqs,
1942 bool freeze)
1943 {
1944 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1945 int queue;
1946
1947 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1948 struct iwl_txq *txq = &trans_pcie->txq[queue];
1949 unsigned long now;
1950
1951 spin_lock_bh(&txq->lock);
1952
1953 now = jiffies;
1954
1955 if (txq->frozen == freeze)
1956 goto next_queue;
1957
1958 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1959 freeze ? "Freezing" : "Waking", queue);
1960
1961 txq->frozen = freeze;
1962
1963 if (txq->read_ptr == txq->write_ptr)
1964 goto next_queue;
1965
1966 if (freeze) {
1967 if (unlikely(time_after(now,
1968 txq->stuck_timer.expires))) {
1969 /*
1970 * The timer should have fired, maybe it is
1971 * spinning right now on the lock.
1972 */
1973 goto next_queue;
1974 }
1975 /* remember how long until the timer fires */
1976 txq->frozen_expiry_remainder =
1977 txq->stuck_timer.expires - now;
1978 del_timer(&txq->stuck_timer);
1979 goto next_queue;
1980 }
1981
1982 /*
1983 * Wake a non-empty queue -> arm timer with the
1984 * remainder before it froze
1985 */
1986 mod_timer(&txq->stuck_timer,
1987 now + txq->frozen_expiry_remainder);
1988
1989 next_queue:
1990 spin_unlock_bh(&txq->lock);
1991 }
1992 }
1993
iwl_trans_pcie_block_txq_ptrs(struct iwl_trans * trans,bool block)1994 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1995 {
1996 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1997 int i;
1998
1999 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
2000 struct iwl_txq *txq = &trans_pcie->txq[i];
2001
2002 if (i == trans_pcie->cmd_queue)
2003 continue;
2004
2005 spin_lock_bh(&txq->lock);
2006
2007 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2008 txq->block--;
2009 if (!txq->block) {
2010 iwl_write32(trans, HBUS_TARG_WRPTR,
2011 txq->write_ptr | (i << 8));
2012 }
2013 } else if (block) {
2014 txq->block++;
2015 }
2016
2017 spin_unlock_bh(&txq->lock);
2018 }
2019 }
2020
2021 #define IWL_FLUSH_WAIT_MS 2000
2022
iwl_trans_pcie_log_scd_error(struct iwl_trans * trans,struct iwl_txq * txq)2023 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2024 {
2025 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2026 u32 scd_sram_addr;
2027 u8 buf[16];
2028 int cnt;
2029
2030 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
2031 txq->read_ptr, txq->write_ptr);
2032
2033 if (trans->cfg->use_tfh)
2034 /* TODO: access new SCD registers and dump them */
2035 return;
2036
2037 scd_sram_addr = trans_pcie->scd_base_addr +
2038 SCD_TX_STTS_QUEUE_OFFSET(txq->id);
2039 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
2040
2041 iwl_print_hex_error(trans, buf, sizeof(buf));
2042
2043 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
2044 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
2045 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
2046
2047 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2048 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
2049 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2050 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2051 u32 tbl_dw =
2052 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
2053 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
2054
2055 if (cnt & 0x1)
2056 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
2057 else
2058 tbl_dw = tbl_dw & 0x0000FFFF;
2059
2060 IWL_ERR(trans,
2061 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
2062 cnt, active ? "" : "in", fifo, tbl_dw,
2063 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
2064 (TFD_QUEUE_SIZE_MAX - 1),
2065 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
2066 }
2067 }
2068
iwl_trans_pcie_wait_txq_empty(struct iwl_trans * trans,u32 txq_bm)2069 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
2070 {
2071 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2072 struct iwl_txq *txq;
2073 int cnt;
2074 unsigned long now = jiffies;
2075 int ret = 0;
2076
2077 /* waiting for all the tx frames complete might take a while */
2078 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2079 u8 wr_ptr;
2080
2081 if (cnt == trans_pcie->cmd_queue)
2082 continue;
2083 if (!test_bit(cnt, trans_pcie->queue_used))
2084 continue;
2085 if (!(BIT(cnt) & txq_bm))
2086 continue;
2087
2088 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
2089 txq = &trans_pcie->txq[cnt];
2090 wr_ptr = ACCESS_ONCE(txq->write_ptr);
2091
2092 while (txq->read_ptr != ACCESS_ONCE(txq->write_ptr) &&
2093 !time_after(jiffies,
2094 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2095 u8 write_ptr = ACCESS_ONCE(txq->write_ptr);
2096
2097 if (WARN_ONCE(wr_ptr != write_ptr,
2098 "WR pointer moved while flushing %d -> %d\n",
2099 wr_ptr, write_ptr))
2100 return -ETIMEDOUT;
2101 usleep_range(1000, 2000);
2102 }
2103
2104 if (txq->read_ptr != txq->write_ptr) {
2105 IWL_ERR(trans,
2106 "fail to flush all tx fifo queues Q %d\n", cnt);
2107 ret = -ETIMEDOUT;
2108 break;
2109 }
2110 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
2111 }
2112
2113 if (ret)
2114 iwl_trans_pcie_log_scd_error(trans, txq);
2115
2116 return ret;
2117 }
2118
iwl_trans_pcie_set_bits_mask(struct iwl_trans * trans,u32 reg,u32 mask,u32 value)2119 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2120 u32 mask, u32 value)
2121 {
2122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2123 unsigned long flags;
2124
2125 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2126 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2127 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2128 }
2129
iwl_trans_pcie_ref(struct iwl_trans * trans)2130 static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2131 {
2132 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2133
2134 if (iwlwifi_mod_params.d0i3_disable)
2135 return;
2136
2137 pm_runtime_get(&trans_pcie->pci_dev->dev);
2138
2139 #ifdef CONFIG_PM
2140 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2141 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2142 #endif /* CONFIG_PM */
2143 }
2144
iwl_trans_pcie_unref(struct iwl_trans * trans)2145 static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2146 {
2147 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2148
2149 if (iwlwifi_mod_params.d0i3_disable)
2150 return;
2151
2152 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2153 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2154
2155 #ifdef CONFIG_PM
2156 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2157 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2158 #endif /* CONFIG_PM */
2159 }
2160
get_csr_string(int cmd)2161 static const char *get_csr_string(int cmd)
2162 {
2163 #define IWL_CMD(x) case x: return #x
2164 switch (cmd) {
2165 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2166 IWL_CMD(CSR_INT_COALESCING);
2167 IWL_CMD(CSR_INT);
2168 IWL_CMD(CSR_INT_MASK);
2169 IWL_CMD(CSR_FH_INT_STATUS);
2170 IWL_CMD(CSR_GPIO_IN);
2171 IWL_CMD(CSR_RESET);
2172 IWL_CMD(CSR_GP_CNTRL);
2173 IWL_CMD(CSR_HW_REV);
2174 IWL_CMD(CSR_EEPROM_REG);
2175 IWL_CMD(CSR_EEPROM_GP);
2176 IWL_CMD(CSR_OTP_GP_REG);
2177 IWL_CMD(CSR_GIO_REG);
2178 IWL_CMD(CSR_GP_UCODE_REG);
2179 IWL_CMD(CSR_GP_DRIVER_REG);
2180 IWL_CMD(CSR_UCODE_DRV_GP1);
2181 IWL_CMD(CSR_UCODE_DRV_GP2);
2182 IWL_CMD(CSR_LED_REG);
2183 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2184 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2185 IWL_CMD(CSR_ANA_PLL_CFG);
2186 IWL_CMD(CSR_HW_REV_WA_REG);
2187 IWL_CMD(CSR_MONITOR_STATUS_REG);
2188 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2189 default:
2190 return "UNKNOWN";
2191 }
2192 #undef IWL_CMD
2193 }
2194
iwl_pcie_dump_csr(struct iwl_trans * trans)2195 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2196 {
2197 int i;
2198 static const u32 csr_tbl[] = {
2199 CSR_HW_IF_CONFIG_REG,
2200 CSR_INT_COALESCING,
2201 CSR_INT,
2202 CSR_INT_MASK,
2203 CSR_FH_INT_STATUS,
2204 CSR_GPIO_IN,
2205 CSR_RESET,
2206 CSR_GP_CNTRL,
2207 CSR_HW_REV,
2208 CSR_EEPROM_REG,
2209 CSR_EEPROM_GP,
2210 CSR_OTP_GP_REG,
2211 CSR_GIO_REG,
2212 CSR_GP_UCODE_REG,
2213 CSR_GP_DRIVER_REG,
2214 CSR_UCODE_DRV_GP1,
2215 CSR_UCODE_DRV_GP2,
2216 CSR_LED_REG,
2217 CSR_DRAM_INT_TBL_REG,
2218 CSR_GIO_CHICKEN_BITS,
2219 CSR_ANA_PLL_CFG,
2220 CSR_MONITOR_STATUS_REG,
2221 CSR_HW_REV_WA_REG,
2222 CSR_DBG_HPET_MEM_REG
2223 };
2224 IWL_ERR(trans, "CSR values:\n");
2225 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2226 "CSR_INT_PERIODIC_REG)\n");
2227 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2228 IWL_ERR(trans, " %25s: 0X%08x\n",
2229 get_csr_string(csr_tbl[i]),
2230 iwl_read32(trans, csr_tbl[i]));
2231 }
2232 }
2233
2234 #ifdef CONFIG_IWLWIFI_DEBUGFS
2235 /* create and remove of files */
2236 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
2237 if (!debugfs_create_file(#name, mode, parent, trans, \
2238 &iwl_dbgfs_##name##_ops)) \
2239 goto err; \
2240 } while (0)
2241
2242 /* file operation */
2243 #define DEBUGFS_READ_FILE_OPS(name) \
2244 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2245 .read = iwl_dbgfs_##name##_read, \
2246 .open = simple_open, \
2247 .llseek = generic_file_llseek, \
2248 };
2249
2250 #define DEBUGFS_WRITE_FILE_OPS(name) \
2251 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2252 .write = iwl_dbgfs_##name##_write, \
2253 .open = simple_open, \
2254 .llseek = generic_file_llseek, \
2255 };
2256
2257 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
2258 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2259 .write = iwl_dbgfs_##name##_write, \
2260 .read = iwl_dbgfs_##name##_read, \
2261 .open = simple_open, \
2262 .llseek = generic_file_llseek, \
2263 };
2264
iwl_dbgfs_tx_queue_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2265 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2266 char __user *user_buf,
2267 size_t count, loff_t *ppos)
2268 {
2269 struct iwl_trans *trans = file->private_data;
2270 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2271 struct iwl_txq *txq;
2272 char *buf;
2273 int pos = 0;
2274 int cnt;
2275 int ret;
2276 size_t bufsz;
2277
2278 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2279
2280 if (!trans_pcie->txq)
2281 return -EAGAIN;
2282
2283 buf = kzalloc(bufsz, GFP_KERNEL);
2284 if (!buf)
2285 return -ENOMEM;
2286
2287 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2288 txq = &trans_pcie->txq[cnt];
2289 pos += scnprintf(buf + pos, bufsz - pos,
2290 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2291 cnt, txq->read_ptr, txq->write_ptr,
2292 !!test_bit(cnt, trans_pcie->queue_used),
2293 !!test_bit(cnt, trans_pcie->queue_stopped),
2294 txq->need_update, txq->frozen,
2295 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2296 }
2297 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2298 kfree(buf);
2299 return ret;
2300 }
2301
iwl_dbgfs_rx_queue_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2302 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2303 char __user *user_buf,
2304 size_t count, loff_t *ppos)
2305 {
2306 struct iwl_trans *trans = file->private_data;
2307 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2308 char *buf;
2309 int pos = 0, i, ret;
2310 size_t bufsz = sizeof(buf);
2311
2312 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2313
2314 if (!trans_pcie->rxq)
2315 return -EAGAIN;
2316
2317 buf = kzalloc(bufsz, GFP_KERNEL);
2318 if (!buf)
2319 return -ENOMEM;
2320
2321 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2322 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2323
2324 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2325 i);
2326 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2327 rxq->read);
2328 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2329 rxq->write);
2330 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2331 rxq->write_actual);
2332 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2333 rxq->need_update);
2334 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2335 rxq->free_count);
2336 if (rxq->rb_stts) {
2337 pos += scnprintf(buf + pos, bufsz - pos,
2338 "\tclosed_rb_num: %u\n",
2339 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2340 0x0FFF);
2341 } else {
2342 pos += scnprintf(buf + pos, bufsz - pos,
2343 "\tclosed_rb_num: Not Allocated\n");
2344 }
2345 }
2346 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2347 kfree(buf);
2348
2349 return ret;
2350 }
2351
iwl_dbgfs_interrupt_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2352 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2353 char __user *user_buf,
2354 size_t count, loff_t *ppos)
2355 {
2356 struct iwl_trans *trans = file->private_data;
2357 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2358 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2359
2360 int pos = 0;
2361 char *buf;
2362 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2363 ssize_t ret;
2364
2365 buf = kzalloc(bufsz, GFP_KERNEL);
2366 if (!buf)
2367 return -ENOMEM;
2368
2369 pos += scnprintf(buf + pos, bufsz - pos,
2370 "Interrupt Statistics Report:\n");
2371
2372 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2373 isr_stats->hw);
2374 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2375 isr_stats->sw);
2376 if (isr_stats->sw || isr_stats->hw) {
2377 pos += scnprintf(buf + pos, bufsz - pos,
2378 "\tLast Restarting Code: 0x%X\n",
2379 isr_stats->err_code);
2380 }
2381 #ifdef CONFIG_IWLWIFI_DEBUG
2382 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2383 isr_stats->sch);
2384 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2385 isr_stats->alive);
2386 #endif
2387 pos += scnprintf(buf + pos, bufsz - pos,
2388 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2389
2390 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2391 isr_stats->ctkill);
2392
2393 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2394 isr_stats->wakeup);
2395
2396 pos += scnprintf(buf + pos, bufsz - pos,
2397 "Rx command responses:\t\t %u\n", isr_stats->rx);
2398
2399 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2400 isr_stats->tx);
2401
2402 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2403 isr_stats->unhandled);
2404
2405 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2406 kfree(buf);
2407 return ret;
2408 }
2409
iwl_dbgfs_interrupt_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)2410 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2411 const char __user *user_buf,
2412 size_t count, loff_t *ppos)
2413 {
2414 struct iwl_trans *trans = file->private_data;
2415 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2416 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2417
2418 char buf[8];
2419 int buf_size;
2420 u32 reset_flag;
2421
2422 memset(buf, 0, sizeof(buf));
2423 buf_size = min(count, sizeof(buf) - 1);
2424 if (copy_from_user(buf, user_buf, buf_size))
2425 return -EFAULT;
2426 if (sscanf(buf, "%x", &reset_flag) != 1)
2427 return -EFAULT;
2428 if (reset_flag == 0)
2429 memset(isr_stats, 0, sizeof(*isr_stats));
2430
2431 return count;
2432 }
2433
iwl_dbgfs_csr_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)2434 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2435 const char __user *user_buf,
2436 size_t count, loff_t *ppos)
2437 {
2438 struct iwl_trans *trans = file->private_data;
2439 char buf[8];
2440 int buf_size;
2441 int csr;
2442
2443 memset(buf, 0, sizeof(buf));
2444 buf_size = min(count, sizeof(buf) - 1);
2445 if (copy_from_user(buf, user_buf, buf_size))
2446 return -EFAULT;
2447 if (sscanf(buf, "%d", &csr) != 1)
2448 return -EFAULT;
2449
2450 iwl_pcie_dump_csr(trans);
2451
2452 return count;
2453 }
2454
iwl_dbgfs_fh_reg_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2455 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2456 char __user *user_buf,
2457 size_t count, loff_t *ppos)
2458 {
2459 struct iwl_trans *trans = file->private_data;
2460 char *buf = NULL;
2461 ssize_t ret;
2462
2463 ret = iwl_dump_fh(trans, &buf);
2464 if (ret < 0)
2465 return ret;
2466 if (!buf)
2467 return -EINVAL;
2468 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2469 kfree(buf);
2470 return ret;
2471 }
2472
2473 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2474 DEBUGFS_READ_FILE_OPS(fh_reg);
2475 DEBUGFS_READ_FILE_OPS(rx_queue);
2476 DEBUGFS_READ_FILE_OPS(tx_queue);
2477 DEBUGFS_WRITE_FILE_OPS(csr);
2478
2479 /* Create the debugfs files and directories */
iwl_trans_pcie_dbgfs_register(struct iwl_trans * trans)2480 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2481 {
2482 struct dentry *dir = trans->dbgfs_dir;
2483
2484 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2485 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2486 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2487 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2488 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2489 return 0;
2490
2491 err:
2492 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2493 return -ENOMEM;
2494 }
2495 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2496
iwl_trans_pcie_get_cmdlen(struct iwl_trans * trans,void * tfd)2497 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2498 {
2499 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2500 u32 cmdlen = 0;
2501 int i;
2502
2503 for (i = 0; i < trans_pcie->max_tbs; i++)
2504 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
2505
2506 return cmdlen;
2507 }
2508
iwl_trans_pcie_dump_rbs(struct iwl_trans * trans,struct iwl_fw_error_dump_data ** data,int allocated_rb_nums)2509 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2510 struct iwl_fw_error_dump_data **data,
2511 int allocated_rb_nums)
2512 {
2513 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2514 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2515 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2516 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2517 u32 i, r, j, rb_len = 0;
2518
2519 spin_lock(&rxq->lock);
2520
2521 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2522
2523 for (i = rxq->read, j = 0;
2524 i != r && j < allocated_rb_nums;
2525 i = (i + 1) & RX_QUEUE_MASK, j++) {
2526 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2527 struct iwl_fw_error_dump_rb *rb;
2528
2529 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2530 DMA_FROM_DEVICE);
2531
2532 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2533
2534 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2535 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2536 rb = (void *)(*data)->data;
2537 rb->index = cpu_to_le32(i);
2538 memcpy(rb->data, page_address(rxb->page), max_len);
2539 /* remap the page for the free benefit */
2540 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2541 max_len,
2542 DMA_FROM_DEVICE);
2543
2544 *data = iwl_fw_error_next_data(*data);
2545 }
2546
2547 spin_unlock(&rxq->lock);
2548
2549 return rb_len;
2550 }
2551 #define IWL_CSR_TO_DUMP (0x250)
2552
iwl_trans_pcie_dump_csr(struct iwl_trans * trans,struct iwl_fw_error_dump_data ** data)2553 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2554 struct iwl_fw_error_dump_data **data)
2555 {
2556 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2557 __le32 *val;
2558 int i;
2559
2560 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2561 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2562 val = (void *)(*data)->data;
2563
2564 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2565 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2566
2567 *data = iwl_fw_error_next_data(*data);
2568
2569 return csr_len;
2570 }
2571
iwl_trans_pcie_fh_regs_dump(struct iwl_trans * trans,struct iwl_fw_error_dump_data ** data)2572 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2573 struct iwl_fw_error_dump_data **data)
2574 {
2575 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2576 unsigned long flags;
2577 __le32 *val;
2578 int i;
2579
2580 if (!iwl_trans_grab_nic_access(trans, &flags))
2581 return 0;
2582
2583 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2584 (*data)->len = cpu_to_le32(fh_regs_len);
2585 val = (void *)(*data)->data;
2586
2587 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2588 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2589
2590 iwl_trans_release_nic_access(trans, &flags);
2591
2592 *data = iwl_fw_error_next_data(*data);
2593
2594 return sizeof(**data) + fh_regs_len;
2595 }
2596
2597 static u32
iwl_trans_pci_dump_marbh_monitor(struct iwl_trans * trans,struct iwl_fw_error_dump_fw_mon * fw_mon_data,u32 monitor_len)2598 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2599 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2600 u32 monitor_len)
2601 {
2602 u32 buf_size_in_dwords = (monitor_len >> 2);
2603 u32 *buffer = (u32 *)fw_mon_data->data;
2604 unsigned long flags;
2605 u32 i;
2606
2607 if (!iwl_trans_grab_nic_access(trans, &flags))
2608 return 0;
2609
2610 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2611 for (i = 0; i < buf_size_in_dwords; i++)
2612 buffer[i] = iwl_read_prph_no_grab(trans,
2613 MON_DMARB_RD_DATA_ADDR);
2614 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2615
2616 iwl_trans_release_nic_access(trans, &flags);
2617
2618 return monitor_len;
2619 }
2620
2621 static u32
iwl_trans_pcie_dump_monitor(struct iwl_trans * trans,struct iwl_fw_error_dump_data ** data,u32 monitor_len)2622 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2623 struct iwl_fw_error_dump_data **data,
2624 u32 monitor_len)
2625 {
2626 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2627 u32 len = 0;
2628
2629 if ((trans_pcie->fw_mon_page &&
2630 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2631 trans->dbg_dest_tlv) {
2632 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2633 u32 base, write_ptr, wrap_cnt;
2634
2635 /* If there was a dest TLV - use the values from there */
2636 if (trans->dbg_dest_tlv) {
2637 write_ptr =
2638 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2639 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2640 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2641 } else {
2642 base = MON_BUFF_BASE_ADDR;
2643 write_ptr = MON_BUFF_WRPTR;
2644 wrap_cnt = MON_BUFF_CYCLE_CNT;
2645 }
2646
2647 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2648 fw_mon_data = (void *)(*data)->data;
2649 fw_mon_data->fw_mon_wr_ptr =
2650 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2651 fw_mon_data->fw_mon_cycle_cnt =
2652 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2653 fw_mon_data->fw_mon_base_ptr =
2654 cpu_to_le32(iwl_read_prph(trans, base));
2655
2656 len += sizeof(**data) + sizeof(*fw_mon_data);
2657 if (trans_pcie->fw_mon_page) {
2658 /*
2659 * The firmware is now asserted, it won't write anything
2660 * to the buffer. CPU can take ownership to fetch the
2661 * data. The buffer will be handed back to the device
2662 * before the firmware will be restarted.
2663 */
2664 dma_sync_single_for_cpu(trans->dev,
2665 trans_pcie->fw_mon_phys,
2666 trans_pcie->fw_mon_size,
2667 DMA_FROM_DEVICE);
2668 memcpy(fw_mon_data->data,
2669 page_address(trans_pcie->fw_mon_page),
2670 trans_pcie->fw_mon_size);
2671
2672 monitor_len = trans_pcie->fw_mon_size;
2673 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2674 /*
2675 * Update pointers to reflect actual values after
2676 * shifting
2677 */
2678 base = iwl_read_prph(trans, base) <<
2679 trans->dbg_dest_tlv->base_shift;
2680 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2681 monitor_len / sizeof(u32));
2682 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2683 monitor_len =
2684 iwl_trans_pci_dump_marbh_monitor(trans,
2685 fw_mon_data,
2686 monitor_len);
2687 } else {
2688 /* Didn't match anything - output no monitor data */
2689 monitor_len = 0;
2690 }
2691
2692 len += monitor_len;
2693 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2694 }
2695
2696 return len;
2697 }
2698
2699 static struct iwl_trans_dump_data
iwl_trans_pcie_dump_data(struct iwl_trans * trans,const struct iwl_fw_dbg_trigger_tlv * trigger)2700 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2701 const struct iwl_fw_dbg_trigger_tlv *trigger)
2702 {
2703 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2704 struct iwl_fw_error_dump_data *data;
2705 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2706 struct iwl_fw_error_dump_txcmd *txcmd;
2707 struct iwl_trans_dump_data *dump_data;
2708 u32 len, num_rbs;
2709 u32 monitor_len;
2710 int i, ptr;
2711 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2712 !trans->cfg->mq_rx_supported;
2713
2714 /* transport dump header */
2715 len = sizeof(*dump_data);
2716
2717 /* host commands */
2718 len += sizeof(*data) +
2719 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2720
2721 /* FW monitor */
2722 if (trans_pcie->fw_mon_page) {
2723 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2724 trans_pcie->fw_mon_size;
2725 monitor_len = trans_pcie->fw_mon_size;
2726 } else if (trans->dbg_dest_tlv) {
2727 u32 base, end;
2728
2729 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2730 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2731
2732 base = iwl_read_prph(trans, base) <<
2733 trans->dbg_dest_tlv->base_shift;
2734 end = iwl_read_prph(trans, end) <<
2735 trans->dbg_dest_tlv->end_shift;
2736
2737 /* Make "end" point to the actual end */
2738 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2739 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2740 end += (1 << trans->dbg_dest_tlv->end_shift);
2741 monitor_len = end - base;
2742 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2743 monitor_len;
2744 } else {
2745 monitor_len = 0;
2746 }
2747
2748 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2749 dump_data = vzalloc(len);
2750 if (!dump_data)
2751 return NULL;
2752
2753 data = (void *)dump_data->data;
2754 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2755 dump_data->len = len;
2756
2757 return dump_data;
2758 }
2759
2760 /* CSR registers */
2761 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2762
2763 /* FH registers */
2764 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2765
2766 if (dump_rbs) {
2767 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2768 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2769 /* RBs */
2770 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
2771 & 0x0FFF;
2772 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2773 len += num_rbs * (sizeof(*data) +
2774 sizeof(struct iwl_fw_error_dump_rb) +
2775 (PAGE_SIZE << trans_pcie->rx_page_order));
2776 }
2777
2778 dump_data = vzalloc(len);
2779 if (!dump_data)
2780 return NULL;
2781
2782 len = 0;
2783 data = (void *)dump_data->data;
2784 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2785 txcmd = (void *)data->data;
2786 spin_lock_bh(&cmdq->lock);
2787 ptr = cmdq->write_ptr;
2788 for (i = 0; i < cmdq->n_window; i++) {
2789 u8 idx = get_cmd_index(cmdq, ptr);
2790 u32 caplen, cmdlen;
2791
2792 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2793 trans_pcie->tfd_size * ptr);
2794 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2795
2796 if (cmdlen) {
2797 len += sizeof(*txcmd) + caplen;
2798 txcmd->cmdlen = cpu_to_le32(cmdlen);
2799 txcmd->caplen = cpu_to_le32(caplen);
2800 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2801 txcmd = (void *)((u8 *)txcmd->data + caplen);
2802 }
2803
2804 ptr = iwl_queue_dec_wrap(ptr);
2805 }
2806 spin_unlock_bh(&cmdq->lock);
2807
2808 data->len = cpu_to_le32(len);
2809 len += sizeof(*data);
2810 data = iwl_fw_error_next_data(data);
2811
2812 len += iwl_trans_pcie_dump_csr(trans, &data);
2813 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2814 if (dump_rbs)
2815 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2816
2817 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2818
2819 dump_data->len = len;
2820
2821 return dump_data;
2822 }
2823
2824 #ifdef CONFIG_PM_SLEEP
iwl_trans_pcie_suspend(struct iwl_trans * trans)2825 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2826 {
2827 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
2828 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
2829 return iwl_pci_fw_enter_d0i3(trans);
2830
2831 return 0;
2832 }
2833
iwl_trans_pcie_resume(struct iwl_trans * trans)2834 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2835 {
2836 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
2837 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
2838 iwl_pci_fw_exit_d0i3(trans);
2839 }
2840 #endif /* CONFIG_PM_SLEEP */
2841
2842 static const struct iwl_trans_ops trans_ops_pcie = {
2843 .start_hw = iwl_trans_pcie_start_hw,
2844 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2845 .fw_alive = iwl_trans_pcie_fw_alive,
2846 .start_fw = iwl_trans_pcie_start_fw,
2847 .stop_device = iwl_trans_pcie_stop_device,
2848
2849 .d3_suspend = iwl_trans_pcie_d3_suspend,
2850 .d3_resume = iwl_trans_pcie_d3_resume,
2851
2852 #ifdef CONFIG_PM_SLEEP
2853 .suspend = iwl_trans_pcie_suspend,
2854 .resume = iwl_trans_pcie_resume,
2855 #endif /* CONFIG_PM_SLEEP */
2856
2857 .send_cmd = iwl_trans_pcie_send_hcmd,
2858
2859 .tx = iwl_trans_pcie_tx,
2860 .reclaim = iwl_trans_pcie_reclaim,
2861
2862 .txq_disable = iwl_trans_pcie_txq_disable,
2863 .txq_enable = iwl_trans_pcie_txq_enable,
2864
2865 .get_txq_byte_table = iwl_trans_pcie_get_txq_byte_table,
2866
2867 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
2868
2869 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2870 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2871 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2872
2873 .write8 = iwl_trans_pcie_write8,
2874 .write32 = iwl_trans_pcie_write32,
2875 .read32 = iwl_trans_pcie_read32,
2876 .read_prph = iwl_trans_pcie_read_prph,
2877 .write_prph = iwl_trans_pcie_write_prph,
2878 .read_mem = iwl_trans_pcie_read_mem,
2879 .write_mem = iwl_trans_pcie_write_mem,
2880 .configure = iwl_trans_pcie_configure,
2881 .set_pmi = iwl_trans_pcie_set_pmi,
2882 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2883 .release_nic_access = iwl_trans_pcie_release_nic_access,
2884 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2885
2886 .ref = iwl_trans_pcie_ref,
2887 .unref = iwl_trans_pcie_unref,
2888
2889 .dump_data = iwl_trans_pcie_dump_data,
2890 };
2891
iwl_trans_pcie_alloc(struct pci_dev * pdev,const struct pci_device_id * ent,const struct iwl_cfg * cfg)2892 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2893 const struct pci_device_id *ent,
2894 const struct iwl_cfg *cfg)
2895 {
2896 struct iwl_trans_pcie *trans_pcie;
2897 struct iwl_trans *trans;
2898 int ret, addr_size;
2899
2900 ret = pcim_enable_device(pdev);
2901 if (ret)
2902 return ERR_PTR(ret);
2903
2904 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2905 &pdev->dev, cfg, &trans_ops_pcie, 0);
2906 if (!trans)
2907 return ERR_PTR(-ENOMEM);
2908
2909 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2910
2911 trans_pcie->trans = trans;
2912 spin_lock_init(&trans_pcie->irq_lock);
2913 spin_lock_init(&trans_pcie->reg_lock);
2914 mutex_init(&trans_pcie->mutex);
2915 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2916 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2917 if (!trans_pcie->tso_hdr_page) {
2918 ret = -ENOMEM;
2919 goto out_no_pci;
2920 }
2921
2922
2923 if (!cfg->base_params->pcie_l1_allowed) {
2924 /*
2925 * W/A - seems to solve weird behavior. We need to remove this
2926 * if we don't want to stay in L1 all the time. This wastes a
2927 * lot of power.
2928 */
2929 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2930 PCIE_LINK_STATE_L1 |
2931 PCIE_LINK_STATE_CLKPM);
2932 }
2933
2934 if (cfg->use_tfh) {
2935 addr_size = 64;
2936 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
2937 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
2938 } else {
2939 addr_size = 36;
2940 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
2941 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
2942 }
2943 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
2944
2945 pci_set_master(pdev);
2946
2947 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
2948 if (!ret)
2949 ret = pci_set_consistent_dma_mask(pdev,
2950 DMA_BIT_MASK(addr_size));
2951 if (ret) {
2952 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2953 if (!ret)
2954 ret = pci_set_consistent_dma_mask(pdev,
2955 DMA_BIT_MASK(32));
2956 /* both attempts failed: */
2957 if (ret) {
2958 dev_err(&pdev->dev, "No suitable DMA available\n");
2959 goto out_no_pci;
2960 }
2961 }
2962
2963 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
2964 if (ret) {
2965 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
2966 goto out_no_pci;
2967 }
2968
2969 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
2970 if (!trans_pcie->hw_base) {
2971 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
2972 ret = -ENODEV;
2973 goto out_no_pci;
2974 }
2975
2976 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2977 * PCI Tx retries from interfering with C3 CPU state */
2978 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2979
2980 trans->dev = &pdev->dev;
2981 trans_pcie->pci_dev = pdev;
2982 iwl_disable_interrupts(trans);
2983
2984 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2985 /*
2986 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2987 * changed, and now the revision step also includes bit 0-1 (no more
2988 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2989 * in the old format.
2990 */
2991 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2992 unsigned long flags;
2993
2994 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2995 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2996
2997 ret = iwl_pcie_prepare_card_hw(trans);
2998 if (ret) {
2999 IWL_WARN(trans, "Exit HW not ready\n");
3000 goto out_no_pci;
3001 }
3002
3003 /*
3004 * in-order to recognize C step driver should read chip version
3005 * id located at the AUX bus MISC address space.
3006 */
3007 iwl_set_bit(trans, CSR_GP_CNTRL,
3008 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3009 udelay(2);
3010
3011 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3012 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3013 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3014 25000);
3015 if (ret < 0) {
3016 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
3017 goto out_no_pci;
3018 }
3019
3020 if (iwl_trans_grab_nic_access(trans, &flags)) {
3021 u32 hw_step;
3022
3023 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
3024 hw_step |= ENABLE_WFPM;
3025 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3026 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
3027 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3028 if (hw_step == 0x3)
3029 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3030 (SILICON_C_STEP << 2);
3031 iwl_trans_release_nic_access(trans, &flags);
3032 }
3033 }
3034
3035 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3036
3037 iwl_pcie_set_interrupt_capa(pdev, trans);
3038 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3039 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3040 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3041
3042 /* Initialize the wait queue for commands */
3043 init_waitqueue_head(&trans_pcie->wait_command_queue);
3044
3045 init_waitqueue_head(&trans_pcie->d0i3_waitq);
3046
3047 if (trans_pcie->msix_enabled) {
3048 if (iwl_pcie_init_msix_handler(pdev, trans_pcie))
3049 goto out_no_pci;
3050 } else {
3051 ret = iwl_pcie_alloc_ict(trans);
3052 if (ret)
3053 goto out_no_pci;
3054
3055 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3056 iwl_pcie_isr,
3057 iwl_pcie_irq_handler,
3058 IRQF_SHARED, DRV_NAME, trans);
3059 if (ret) {
3060 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3061 goto out_free_ict;
3062 }
3063 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3064 }
3065
3066 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
3067 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3068 #else
3069 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3070 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3071
3072 return trans;
3073
3074 out_free_ict:
3075 iwl_pcie_free_ict(trans);
3076 out_no_pci:
3077 free_percpu(trans_pcie->tso_hdr_page);
3078 iwl_trans_free(trans);
3079 return ERR_PTR(ret);
3080 }
3081