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Searched refs:DCACHE (Results 1 – 12 of 12) sorted by relevance

/arch/metag/kernel/
Dcachepart.c20 #define DCACHE 1 macro
64 isEnabled = (cache == DCACHE ? metag_in32(MMCU_DCACHE_CTRL_ADDR) & 0x1 : in get_thread_cache_size()
70 cache_size = (cache == DCACHE ? get_global_dcache_size() : in get_thread_cache_size()
74 cache_size = (cache == DCACHE ? get_dcache_size() : in get_thread_cache_size()
77 t_cache_part = (cache == DCACHE ? in get_thread_cache_size()
99 for (cache_type = ICACHE; cache_type <= DCACHE; cache_type++) { in check_for_cache_aliasing()
Duser_gateway.S79 DCACHE [D1Ar3], D0Re0
/arch/tile/include/uapi/asm/
Dcachectl.h39 #define DCACHE (1<<1) /* flush and invalidate data cache */ macro
40 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
/arch/blackfin/include/uapi/asm/
Dcachectl.h17 #define DCACHE (1<<1) /* writeback and flush data cache */ macro
18 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
/arch/mips/include/uapi/asm/
Dcachectl.h15 #define DCACHE (1<<1) /* writeback and flush data cache */ macro
16 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
/arch/m32r/include/asm/
Dcachectl.h15 #define DCACHE (1<<1) /* writeback and flush data cache */ macro
16 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
/arch/sh/include/uapi/asm/
Dcachectl.h16 #define DCACHE CACHEFLUSH_D_PURGE /* writeback and flush data cache */ macro
17 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
/arch/arc/include/uapi/asm/
Dcachectl.h25 #define DCACHE CF_D_FLUSH macro
/arch/metag/tbx/
Dtbicore.S119 DCACHE [D1Ar1],A0.3 /* Flush Cache line */
121 DCACHE [D1Ar1],A0.3 /* Flush Cache line */
/arch/blackfin/kernel/
Dsys_bfin.c82 if (op & DCACHE) in SYSCALL_DEFINE3()
/arch/tile/kernel/
Dsys.c43 if (flags & DCACHE) in SYSCALL_DEFINE3()
/arch/blackfin/
DKconfig1047 bool "Enable DCACHE"
1050 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1054 bool "Enable DCACHE for external memory"
1058 prompt "External memory DCACHE policy"
1100 bool "Enable DCACHE for L2 SRAM"
1105 prompt "L2 SRAM DCACHE policy"