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Searched refs:DIV4 (Results 1 – 12 of 12) sorted by relevance

/arch/sh/kernel/cpu/sh4a/
Dclock-sh7785.c69 #define DIV4(_bit, _mask, _flags) \ macro
73 [DIV4_P] = DIV4(0, 0x0f80, 0),
74 [DIV4_DU] = DIV4(4, 0x0ff0, 0),
75 [DIV4_GA] = DIV4(8, 0x0030, 0),
76 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
77 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
78 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
79 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
80 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
Dclock-shx3.c64 #define DIV4(_bit, _mask, _flags) \ macro
68 [DIV4_P] = DIV4(0, 0x0f80, 0),
69 [DIV4_SHA] = DIV4(4, 0x0ff0, 0),
70 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
71 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
72 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
73 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
Dclock-sh7722.c120 #define DIV4(_reg, _bit, _mask, _flags) \ macro
126 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
127 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
128 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
129 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
130 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
131 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
137 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
143 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
144 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
Dclock-sh7786.c70 #define DIV4(_bit, _mask, _flags) \ macro
74 [DIV4_P] = DIV4(0, 0x0b40, 0),
75 [DIV4_DU] = DIV4(4, 0x0010, 0),
76 [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
77 [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
78 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
79 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
Dclock-sh7723.c123 #define DIV4(_reg, _bit, _mask, _flags) \ macro
127 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
128 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
129 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
130 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
131 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
132 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
138 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),
144 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),
145 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),
Dclock-sh7366.c120 #define DIV4(_reg, _bit, _mask, _flags) \ macro
124 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
125 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
126 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
127 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
128 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
129 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
130 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
131 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
Dclock-sh7343.c117 #define DIV4(_reg, _bit, _mask, _flags) \ macro
121 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
122 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
123 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
124 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
125 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
126 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
127 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
128 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
Dclock-sh7757.c65 #define DIV4(_bit, _mask, _flags) \ macro
73 [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
74 [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
75 [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
Dclock-sh7734.c72 #define DIV4(_reg, _bit, _mask, _flags) \ macro
76 [DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),
77 [DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT),
78 [DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT),
79 [DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT),
80 [DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT),
81 [DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT),
Dclock-sh7724.c162 #define DIV4(_reg, _bit, _mask, _flags) \ macro
166 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
167 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
168 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
169 [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
170 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
/arch/sh/kernel/cpu/sh2a/
Dclock-sh7264.c80 #define DIV4(_reg, _bit, _mask, _flags) \ macro
85 [DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT
87 [DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),
Dclock-sh7269.c108 #define DIV4(_reg, _bit, _mask, _flags) \ macro
113 [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
115 [DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT