Searched refs:LINE (Results 1 – 7 of 7) sorted by relevance
88 #define FLOWCTL_QUERY(LINE) \ in __debug_to_serial() argument89 ({ GDBPORT_SERIAL_MSR & UART_MSR_##LINE; }) in __debug_to_serial()90 #define FLOWCTL_WAIT_FOR(LINE) \ in __debug_to_serial() argument91 do {} while (!(GDBPORT_SERIAL_MSR & UART_MSR_##LINE)) in __debug_to_serial()92 #define FLOWCTL_CLEAR(LINE) \ in __debug_to_serial() argument93 do { GDBPORT_SERIAL_MCR &= ~UART_MCR_##LINE; } while (0) in __debug_to_serial()94 #define FLOWCTL_SET(LINE) \ in __debug_to_serial() argument95 do { GDBPORT_SERIAL_MCR |= UART_MCR_##LINE; } while (0) in __debug_to_serial()
85 #define FLOWCTL_WAIT_FOR(LINE) \ argument87 while (!(TTYS0_MSR & UART_MSR_##LINE)) {} \89 #define FLOWCTL_CLEAR(LINE) \ argument91 TTYS0_MCR &= ~UART_MCR_##LINE; \93 #define FLOWCTL_SET(LINE) \ argument95 TTYS0_MCR |= UART_MCR_##LINE; \97 #define FLOWCTL_QUERY(LINE) ({ TTYS0_MSR & UART_MSR_##LINE; }) argument
40 #define FLOWCTL_QUERY(LINE) ({ __UART(MSR) & UART_MSR_##LINE; }) argument41 #define FLOWCTL_CLEAR(LINE) do { __UART(MCR) &= ~UART_MCR_##LINE; mb(); } while (0) argument42 #define FLOWCTL_SET(LINE) do { __UART(MCR) |= UART_MCR_##LINE; mb(); } while (0) argument44 #define FLOWCTL_WAIT_FOR(LINE) \ argument47 } while(!FLOWCTL_QUERY(LINE))
33 #define FLOWCTL_QUERY0(LINE) ({ __UART0(MSR) & UART_MSR_##LINE; }) argument34 #define FLOWCTL_CLEAR0(LINE) do { __UART0(MCR) &= ~UART_MCR_##LINE; } while (0) argument35 #define FLOWCTL_SET0(LINE) do { __UART0(MCR) |= UART_MCR_##LINE; } while (0) argument37 #define FLOWCTL_WAIT_FOR0(LINE) \ argument40 } while(!FLOWCTL_QUERY(LINE))
101 #define FLOWCTL_WAIT_FOR(LINE) \ argument103 while (!(GDBPORT_SERIAL_MSR & UART_MSR_##LINE)) {} \105 #define FLOWCTL_CLEAR(LINE) \ argument107 GDBPORT_SERIAL_MCR &= ~UART_MCR_##LINE; \109 #define FLOWCTL_SET(LINE) \ argument111 GDBPORT_SERIAL_MCR |= UART_MCR_##LINE; \113 #define FLOWCTL_QUERY(LINE) ({ GDBPORT_SERIAL_MSR & UART_MSR_##LINE; }) argument
38 #define FLOWCTL_QUERY(LINE) \ argument39 ({ CYG_DEV_MSR & SIO_MSR_##LINE; })40 #define FLOWCTL_WAIT_FOR(LINE) \ argument41 do { while (!(CYG_DEV_MSR & SIO_MSR_##LINE)) {} } while (0)42 #define FLOWCTL_CLEAR(LINE) \ argument43 do { CYG_DEV_MCR &= ~SIO_MCR_##LINE; } while (0)44 #define FLOWCTL_SET(LINE) \ argument45 do { CYG_DEV_MCR |= SIO_MCR_##LINE; } while (0)
259 __EPPI(LINE, line); in bfin_debug_mmrs_eppi()