Home
last modified time | relevance | path

Searched refs:Op2 (Results 1 – 9 of 9) sorted by relevance

/arch/arm64/kvm/
Dsys_regs.c554 if (!(p->Op2 & 1)) in access_pmceid()
586 if (r->Op2 == 2) { in access_pmu_evcntr()
593 } else if (r->Op2 == 0) { in access_pmu_evcntr()
613 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); in access_pmu_evcntr()
644 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { in access_pmu_evtyper()
649 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); in access_pmu_evtyper()
686 if (r->Op2 & 0x1) { in access_pmcnten()
716 if (r->Op2 & 0x1) in access_pminten()
797 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100), \
800 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101), \
[all …]
Dsys_regs.h30 u8 Op2; member
43 u8 Op2; member
70 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); in print_sys_reg_instr()
136 return i1->Op2 - i2->Op2; in cmp_sys_reg()
144 #define Op2(_x) .Op2 = _x macro
Dsys_regs_generic_v8.c56 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
62 { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
/arch/arm/kvm/
Dcoproc.c296 { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
300 { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
304 { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
308 { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
313 { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32,
315 { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32,
317 { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
323 { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
327 { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
329 { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
[all …]
Dcoproc.h26 unsigned long Op2; member
38 unsigned long Op2; member
66 p->CRn, p->CRm, p->Op1, p->Op2, in print_cp_instr()
142 if (i1->Op2 != i2->Op2) in cmp_reg()
143 return i1->Op2 - i2->Op2; in cmp_reg()
152 #define Op2(_x) .Op2 = _x macro
Dtrace.h139 unsigned long CRm, unsigned long Op2, bool is_write),
140 TP_ARGS(Op1, Rt1, CRn, CRm, Op2, is_write),
147 __field( unsigned int, Op2 )
157 __entry->Op2 = Op2;
163 __entry->CRm, __entry->Op2)
Dcoproc_a7.c39 { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
Dcoproc_a15.c36 { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
/arch/arm/include/asm/
Dcp15.h52 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ argument
53 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32