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/arch/hexagon/kernel/
Dvm_entry.S50 memd(R0 + #_PT_R3130) = R31:30; \
51 { memw(R0 + #_PT_R2928) = R28; \
52 R31 = memw(R0 + #_PT_ER_VMPSP); }\
53 { memw(R0 + #(_PT_R2928 + 4)) = R31; \
55 { memd(R0 + #_PT_R2726) = R27:26; \
57 memd(R0 + #_PT_R2524) = R25:24; \
58 memd(R0 + #_PT_R2322) = R23:22; \
59 memd(R0 + #_PT_R2120) = R21:20; \
60 memd(R0 + #_PT_R1918) = R19:18; \
61 memd(R0 + #_PT_R1716) = R17:16; \
[all …]
/arch/blackfin/lib/
Ddivsi3.S39 R3 = R0 ^ R1;
40 R0 = ABS R0; define
57 DIVS(R0, R1);
58 DIVQ(R0, R1);
59 DIVQ(R0, R1);
60 DIVQ(R0, R1);
61 DIVQ(R0, R1);
62 DIVQ(R0, R1);
63 DIVQ(R0, R1);
64 DIVQ(R0, R1);
[all …]
Dudivsi3.S20 CC = R0 < R1 (IU); /* If X < Y, always return 0 */
24 CC = R2 <= R0 (IU);
27 R2 = R0 >> 31; /* if X is a 31-bit number */
46 R0 <<= 1;
47 DIVQ(R0, R1); // 1
48 DIVQ(R0, R1); // 2
49 DIVQ(R0, R1); // 3
50 DIVQ(R0, R1); // 4
51 DIVQ(R0, R1); // 5
52 DIVQ(R0, R1); // 6
[all …]
Dins.S76 P0 = R0; /* P0 = port */ \
92 R0 = [P0]; \
93 [P1++] = R0; \
97 R0 = W[P0]; \
98 W[P1++] = R0; \
102 R0 = W[P0]; \
103 B[P1++] = R0; \
104 R0 = R0 >> 8; \
105 B[P1++] = R0; \
109 R0 = B[P0]; \
[all …]
Dumulsi3_highpart.S18 R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU);
19 R0 = R1.L * R0.L, R1 = R1.H * R0.L (FU); define
20 R0 >>= 16;
23 R0 = R0 + R3; define
24 R0 = R0 + R1; define
27 R1 = PACK(R1.l,R0.h);
28 R0 = R1 + R2; define
Douts.S18 P0 = R0; /* P0 = port */
23 .Llong_loop_s: R0 = [P1++];
24 .Llong_loop_e: [P0] = R0;
31 P0 = R0; /* P0 = port */
36 .Lword_loop_s: R0 = W[P1++];
37 .Lword_loop_e: W[P0] = R0;
44 P0 = R0; /* P0 = port */
49 .Lbyte_loop_s: R0 = B[P1++];
50 .Lbyte_loop_e: B[P0] = R0;
57 P0 = R0; /* P0 = port */
[all …]
Dstrncmp.S28 P0 = R0 ; /* s1 */
31 R0 = B[P0++] (Z); /* get *s1 */ define
33 CC = R0 == R1; /* compare a byte */
35 CC = R0; /* at end of s1? */
41 R0 = 0; /* strings are equal */ define
44 R0 = R0 - R1; /* *s1 - *s2 */ define
49 R0 = 0; define
Dmemcmp.S23 P0 = R0; /* P0 = s1 address */
29 R1 = R1 | R0; /* OR addresses together */
42 R0 = [P0++]; define
45 MNOP || R0 = [P0++] || R1 = [I0++];
47 CC = R0 == R1;
61 R0 = B[P0++](Z); /* *s1 */ define
62 CC = R0 == R1;
68 R0 = R0 - R1; define
88 R0 = 0; define
Dmuldi3.S52 A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4; /* E1 */
55 A0 = R0.l * R3.l (FU); /* E2 */
58 A1 = R2.L * R0.L (FU); /* E4 */
61 A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU); /* E2, E3c */
62 A1 += R0.L * R2.H (FU); /* E3c */
63 R0 = A1.w; define
69 R0 = PACK (R0.l, R3.l); define
Dumodsi3.S21 CC=R0==0;
25 CC=R0==R1;
29 CC = R0<R1 (IU);
34 R7 = R0; /* Copy of R0 */
39 R0 *= R6; /* Quotient * divisor */
40 R0 = R7 - R0; /* Dividend - (quotient * divisor) */ define
45 R0 = 0; define
Dstrncpy.S31 P0 = R0 ; /* dst*/
68 I1 = R0;
69 R0 = RETS; define
70 I0 = R0;
71 R0 = P0; define
73 R0 = I0; define
74 RETS = R0;
75 R0 = I1; define
Dstrcmp.S27 P0 = R0 ; /* s1 */
31 R0 = B[P0++] (Z); /* get *s1 */ define
33 CC = R0 == R1; /* compare a byte */
35 CC = R0; /* at end of s1? */
39 R0 = R0 - R1; /* *s1 - *s2 */ define
Dsmulsi3_highpart.S18 R2 = R1.L * R0.L (FU);
19 R3 = R1.H * R0.L (IS,M);
20 R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M); define
35 R0 = R0 + R1; define
Dmodsi3.S25 CC=R0==0;
29 CC=R0==R1;
41 R7 = R0; /* Copy of R0 */
46 R0 *= R6; /* Quotient * divisor */
47 R0 = R7 - R0; /* Dividend - (quotient * divisor) */ define
53 R0 = 0; define
Dmemset.S27 P0 = R0 ; /* P0 = address */
29 R3 = R0 + R2; /* end */
34 R2 = R0 & R2; /* addr bottom two bits */
72 CC = BITTST (R0, 0); /* odd byte */
73 R0 = 4; define
74 R0 = R0 - R2; define
75 P1 = R0;
76 R0 = P0; /* Recover return address */ define
Dmemchr.S22 P0 = R0; /* P0 = address */
39 R0=0;
43 R0 = P0; define
44 R0 += -1;
Dmemcpy.S35 P0 = R0 ; /* dst*/
40 CC = R1 < R0; /* src < dst */
43 CC = R0 < R3; /* and dst < src+len */
49 R3 = R1 | R0;
Dmemmove.S21 P0 = R0; /* P0 = To address */
27 CC = R1 < R0 (IU); /* From < To */
30 CC = R0 <= R3 (IU); /* (From+len) >= To */
36 R3 = R1 | R0; /* OR addresses together */
/arch/blackfin/kernel/
Dfixed_code.S40 R0 = [P0]; define
56 R0 = [P0]; define
57 CC = R0 == R1;
74 R0 = R1 + R0; define
75 [P0] = R0;
89 R0 = R1 - R0; define
90 [P0] = R0;
104 R0 = R1 | R0; define
105 [P0] = R0;
119 R0 = R1 & R0; define
[all …]
/arch/blackfin/include/asm/
Dentry.h60 [--sp] = R0; /*orig_r0*/ \
62 R0 = (N); \
69 [--sp] = R0; /*orig_r0*/ \
74 R0 = (N); \
85 [--sp] = R0; /*orig_r0*/ \
90 R0 = (N); \
111 [--sp] = R0; /*orig_r0*/ \
120 R0 = [P0]; \
121 CC = BITTST(R0, EVT_IVHW_P); \
127 R0 = (N); \
[all …]
/arch/x86/crypto/
Dtwofish-x86_64-asm_64.S42 #define R0 %rax macro
239 encrypt_round(R0,R1,R2,R3,0);
240 encrypt_round(R2,R3,R0,R1,8);
241 encrypt_round(R0,R1,R2,R3,2*8);
242 encrypt_round(R2,R3,R0,R1,3*8);
243 encrypt_round(R0,R1,R2,R3,4*8);
244 encrypt_round(R2,R3,R0,R1,5*8);
245 encrypt_round(R0,R1,R2,R3,6*8);
246 encrypt_round(R2,R3,R0,R1,7*8);
247 encrypt_round(R0,R1,R2,R3,8*8);
[all …]
Dtwofish-i586-asm_32.S244 encrypt_round(R0,R1,R2,R3,0);
245 encrypt_round(R2,R3,R0,R1,8);
246 encrypt_round(R0,R1,R2,R3,2*8);
247 encrypt_round(R2,R3,R0,R1,3*8);
248 encrypt_round(R0,R1,R2,R3,4*8);
249 encrypt_round(R2,R3,R0,R1,5*8);
250 encrypt_round(R0,R1,R2,R3,6*8);
251 encrypt_round(R2,R3,R0,R1,7*8);
252 encrypt_round(R0,R1,R2,R3,8*8);
253 encrypt_round(R2,R3,R0,R1,9*8);
[all …]
/arch/blackfin/mach-common/
Ddpmc_modes.S32 R0 = IWR_ENABLE(0); define
66 R4 = R0;
71 R0 = IWR_DISABLE_ALL; define
95 P3 = R0;
99 R0 = IWR_ENABLE(0); define
109 R0.L = 0xF;
110 W[P0] = R0.l; /* Set Max VCO to SCLK divider */
115 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
116 W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
139 R0 = P3; define
[all …]
Dcache.S34 R0 = R0 & R2; define
42 R2 = R1 - R0;
49 P0 = R0;
/arch/blackfin/mach-bf561/
Dsecondary.S28 R0 = SYSCFG_SNEN; define
30 R0 = SYSCFG_SNEN | SYSCFG_CCEN; define
32 SYSCFG = R0;
145 R0 = IWR_DISABLE_ALL; define
148 [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
149 [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;

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