| /arch/alpha/math-emu/ |
| D | math.c | 101 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in alpha_fp_emul()
135 FP_SUB_S(SR, SA, SB); in alpha_fp_emul()
139 FP_ADD_S(SR, SA, SB); in alpha_fp_emul()
143 FP_MUL_S(SR, SA, SB); in alpha_fp_emul()
147 FP_DIV_S(SR, SA, SB); in alpha_fp_emul()
151 FP_SQRT_S(SR, SB); in alpha_fp_emul()
221 FP_CONV(S,D,1,1,SR,DB); in alpha_fp_emul()
259 FP_FROM_INT_S(SR, ((long)vb), 64, long); in alpha_fp_emul()
271 FP_PACK_SP(&vc, SR); in alpha_fp_emul()
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| /arch/avr32/include/asm/ |
| D | irqflags.h | 16 return sysreg_read(SR); in arch_local_save_flags()
28 sysreg_write(SR, flags); in arch_local_irq_restore()
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| /arch/sparc/math-emu/ |
| D | math_32.c | 285 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in do_one_mathemu()
427 case FADDS: FP_ADD_S (SR, SA, SB); break; in do_one_mathemu()
431 case FSUBS: FP_SUB_S (SR, SA, SB); break; in do_one_mathemu()
435 case FMULS: FP_MUL_S (SR, SA, SB); break; in do_one_mathemu()
443 case FDIVS: FP_DIV_S (SR, SA, SB); break; in do_one_mathemu()
447 case FSQRTS: FP_SQRT_S (SR, SB); break; in do_one_mathemu()
459 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; in do_one_mathemu()
466 case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break; in do_one_mathemu()
467 case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break; in do_one_mathemu()
506 case 5: FP_PACK_SP (rd, SR); break; in do_one_mathemu()
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| D | math_64.c | 180 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in do_mathemu()
432 case FADDS: FP_ADD_S (SR, SA, SB); break; in do_mathemu()
436 case FSUBS: FP_SUB_S (SR, SA, SB); break; in do_mathemu()
440 case FMULS: FP_MUL_S (SR, SA, SB); break; in do_mathemu()
448 case FDIVS: FP_DIV_S (SR, SA, SB); break; in do_mathemu()
452 case FSQRTS: FP_SQRT_S (SR, SB); break; in do_mathemu()
470 case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break; in do_mathemu()
473 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; in do_mathemu()
480 case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break; in do_mathemu()
481 case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break; in do_mathemu()
[all …]
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| /arch/avr32/mach-at32ap/ |
| D | intc.c | 79 status_reg = sysreg_read(SR); in do_IRQ()
82 sysreg_write(SR, status_reg); in do_IRQ()
134 sysreg_write(SR, (sysreg_read(SR) in init_IRQ()
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| /arch/sh/kernel/ |
| D | head_64.S | 168 getcon SR, r29
170 putcon r20, SR
257 getcon SR, r21
300 getcon SR, r21
303 putcon r22, SR /* Try to enable */
304 getcon SR, r22
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| /arch/sh/include/cpu-sh5/cpu/ |
| D | registers.h | 25 #define SR cr0
87 #define __SR __str(SR)
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| /arch/sh/kernel/cpu/sh2a/ |
| D | entry.S | 49 bld.b #6,@(0,r2) !previus SR.MD
50 bst.b #6,@(4*4,r15) !set cpu mode to SR.MD
53 bset.b #6,@(0,r2) !set SR.MD
66 mov.l r0,@-r15 ! original SR
94 mov.l @r8+,r11 ! old SR
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| /arch/sh/kernel/cpu/sh3/ |
| D | entry.S | 217 ! r8 passes SR bitmask, overwritten with restored data on return
245 mov.l @r15+, k3 ! original SR
259 ! Calculate new SR value
260 mov k3, k2 ! original SR value
264 and k1, k2 ! Mask original SR value
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| D | swsusp.S | 109 mov.l 2f, r3 ! get new SR value for bank1
117 mov.l 3f, k4 ! SR bits to clear in k4
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| /arch/m68k/ifpsp060/ |
| D | CHANGES | 79 SR = SR at time of exception
101 SR = SR at time of exception
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| D | iskeleton.S | 72 btst #0x5,%sp@ | supervisor bit set in saved SR?
107 | * SR * * SR *
147 | * SR * * SR *
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| /arch/powerpc/math-emu/ |
| D | math_efp.c | 219 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in do_spe_mathemu()
250 FP_ADD_S(SR, SA, SB); in do_spe_mathemu()
254 FP_SUB_S(SR, SA, SB); in do_spe_mathemu()
258 FP_MUL_S(SR, SA, SB); in do_spe_mathemu()
262 FP_DIV_S(SR, SA, SB); in do_spe_mathemu()
297 FP_CONV(S, D, 1, 2, SR, DB); in do_spe_mathemu()
331 FP_PACK_SP(vc.wp + 1, SR); in do_spe_mathemu()
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| /arch/sh/ |
| D | Kconfig.cpu | 92 This will enable the use of SR.RB register bank usage. Processors
97 information on SR.RB and register banking in the kernel in general.
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| D | Kconfig.debug | 83 bool "Debug: set SR.WATCH to enable hardware watchpoints and trace"
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| /arch/sh/kernel/cpu/sh2/ |
| D | entry.S | 58 mov.l @(5*4,r15),r3 ! previous SR
62 mov.l r3,@(5*4,r15) ! update SR
85 mov.l r0,@-r15 ! original SR
129 mov.l @r2+,r0 ! old SR
135 mov.l r0,@-r2 ! save old SR
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| /arch/sh/kernel/cpu/sh5/ |
| D | entry.S | 83 getcon SR, r6; \
85 putcon r6, SR;
88 getcon SR, r6; \
90 putcon r6, SR;
606 ! construct useful SR for handle_exception
613 ! SSR is now the current SR with the MD and MMU bits set
831 getcon SR, r6
834 putcon r6, SR
837 putcon r6, SR
909 getcon SR, r7
[all …]
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| /arch/mips/include/asm/emma/ |
| D | emma2rh.h | 232 #define SR 0x000000ff macro
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| /arch/avr32/kernel/ |
| D | kprobes.c | 73 BUG_ON(!(sysreg_read(SR) & SYSREG_BIT(SR_D))); in prepare_singlestep()
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| D | signal.c | 278 if ((sysreg_read(SR) & MODE_MASK) == MODE_SUPERVISOR) in do_notify_resume()
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| /arch/frv/kernel/ |
| D | cmode.S | 117 # (7) Set '1' to the DRCN.SR bit, and change SDRAM to the
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| /arch/m68k/kernel/ |
| D | entry.S | 269 bclr #7,%sp@(PT_OFF_SR) | clear trace bit in SR
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| /arch/m68k/ifpsp060/src/ |
| D | pfpsp.S | 2052 # * SR * * SR *
3001 mov.w 0xc(%sp),0x4(%sp) # move SR
3026 mov.l 0x8(%sp),(%sp) # store SR,hi(PC)
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| D | fpsp.S | 2053 # * SR * * SR *
3002 mov.w 0xc(%sp),0x4(%sp) # move SR
3027 mov.l 0x8(%sp),(%sp) # store SR,hi(PC)
4372 mov.l 0x2(%sp),(%sp) # shift SR,hi(PC) "down"
4378 mov.l 0x2(%sp),(%sp) # shift SR,hi(PC) "down"
4397 # ** Next PC ** * SR *
4399 # * SR * (4 words)
4406 mov.w EXC_SR(%a6),2+EXC_PC(%a6) # shift SR "up"
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| /arch/powerpc/xmon/ |
| D | ppc-opc.c | 482 #define SR SPRG + 1 macro
486 #define STRM SR + 1
3482 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3610 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
4324 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
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