Searched refs:SYSC_REG_CPLL_CONFIG1 (Results 1 – 2 of 2) sorted by relevance
| /arch/mips/include/asm/mach-ralink/ | ||
| D | mt7620.h | 27 #define SYSC_REG_CPLL_CONFIG1 0x58 macro |
| /arch/mips/ralink/ | ||
| D | mt7620.c | 438 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); in mt7620_get_pll_rate() |