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/arch/alpha/lib/
Dev6-csum_ipv6_magic.S64 inslh $18,7,$4 # U : 0000000000AABBCC
66 sll $19,8,$7 # U : U L U L : 0x00000000 00aabb00
70 zapnot $20,15,$20 # U : zero extend incoming csum
71 ldq_u $2,0($17) # L : U L U L : Latency: 3
73 extql $0,$6,$0 # U :
74 extqh $1,$6,$22 # U :
76 sll $19,24,$19 # U : U U L U : 0x000000aa bb000000
80 inswl $18,3,$18 # U : 000000CCDD000000
81 addl $19,$7,$19 # E : U L U L : <sign bits>bbaabb00
84 extql $1,$6,$1 # U :
[all …]
Dev6-copy_user.S64 beq $0, $zerolength # U .. .. .. : U L U L
67 ble $1, $onebyteloop # .. .. U .. : 1st branch : small amount of data
68 beq $3, $destaligned # .. U .. .. : 2nd (one cycle fetcher stall)
69 subq $3, 8, $3 # E .. .. .. : L U U L : trip counter
79 nop # E .. .. .. : U L U L
88 bne $3, $aligndest # U .. .. .. : U L U L
98 beq $1,$quadaligned # U .. .. .. : U L U L
109 extql $3,$7,$3 # .. U .. .. :
110 extqh $2,$7,$1 # U .. .. .. : U U L L
115 subq $0,8,$0 # E .. .. .. : U L L U
[all …]
Dev6-clear_user.S67 beq $0, $zerolength # U .. .. .. : U L U L
74 beq $4, $headalign # U .. .. .. : U L U L
81 beq $1, $onebyte # .. .. U .. : sub-word store?
82 mskql $5, $6, $5 # .. U .. .. : take care of misaligned head
83 addq $6, 8, $6 # E .. .. .. : L U U L
88 subq $0, 8, $0 # E .. .. .. : U L U L
102 blt $4, $trailquad # U .. .. .. : U L U L
114 beq $3, $bigalign # U .. .. .. : U L U L : Aligned 0mod64
120 nop # E .. .. .. : U L U L
125 blt $3, $alignmod64 # U .. .. .. : U L U L
[all …]
Dev6-memchr.S46 zap $18, 0x80, $5 # U : Bound length
47 beq $18, $not_found # U :
49 and $17, 0xff, $17 # E : L L U U : 00000000000000ch
51 insbl $17, 1, $2 # U : 000000000000ch00
54 lda $3, -1($31) # E : U L L U
56 sll $17, 16, $2 # U : 00000000chch0000
59 sll $17, 32, $2 # U : U L L U : chchchch00000000
62 extql $1, $16, $7 # U : $7 is upper bits
63 beq $4, $first_quad # U :
64 ldq_u $6, -1($5) # L : L U U L : eight or less bytes to search Latency=3
[all …]
Dev6-divide.S114 stq $2, 8($30) # L : L U L U
119 LONGIFY(divisor) # E : U L L U
124 DIV_ONLY(stq tmp2,32($30)) # L : L U U L
146 bne compare,1b # U : U L U L
151 blt divisor, 2f # U : U L U L
156 bne compare,1b # U : U L U L
170 srl mask,1,mask # U :
177 srl divisor,1,divisor # U :
178 nop # E : L U L U
183 bne mask,2b # U : U L U L
[all …]
Dev6-memset.S53 insbl $17,1,$2 # U : 000000000000ch00
55 ble $18,end_b # U : zero length requested?
59 insbl $1,2,$3 # U : 0000000000ch0000
60 insbl $1,3,$4 # U : 00000000ch000000
63 inswl $17,4,$5 # U : 0000chch00000000
65 inswl $17,6,$2 # U : chch000000000000
73 beq $1,within_quad_b # U :
75 beq $3,aligned_b # U : target is 0mod8
82 insql $17,$16,$2 # U : Insert new bytes
86 mskql $4,$16,$4 # U : clear relevant parts of the quad
[all …]
Dev6-stxcpy.S58 mskqh t2, a1, t2 # U : detection in the src word (stall)
59 mskqh t1, a1, t3 # U :
62 mskql t0, a1, t0 # U : assemble the first output word
65 bne t8, $a_eos # U : (stall)
81 beq t8, $a_loop # U : (stall for t8)
93 bne t6, 1f # U : (stall)
99 zapnot t1, t6, t1 # U : clear src bytes >= null (stall)
125 bne t0, $unaligned # U : (stall)
131 beq t0, stxcpy_aligned # U : ... if we wont need it (stall)
156 extql t1, a1, t1 # U : (stall on a1)
[all …]
Dev6-stxncpy.S66 mskqh t2, a1, t2 # U : detection in the src word (stall)
67 mskqh t1, a1, t3 # U :
70 mskql t0, a1, t0 # U : assemble the first output word
73 beq a2, $a_eoc # U :
75 bne t8, $a_eos # U :
97 beq a2, $a_eoc # U :
99 beq t8, $a_loop # U :
117 bne t6, 1f # U : (stall)
124 zapnot t0, t8, t0 # U : clear src bytes > null (stall)
160 srl a2, 3, a2 # U : a2 = loop counter = (count - 1)/8 (stall)
[all …]
Dev67-strncat.S34 beq $18, $zerocount # U :
39 insqh $2, $0, $2 # U :
47 bne $2, $found # U :
52 beq $2, $loop # U :
61 zapnot $1, $27, $2 # U : was last byte a null?
63 bne $2, 0f # U :
68 bne $2, 2f # U :
72 bne $3, 1f # U :
77 2: zap $1, $24, $1 # U :
Dev6-memcpy.S34 ble $18, $nomoredata # U : done with the copy?
38 bne $1, $misaligned # U : Nope - gotta do this the slow way
41 beq $1, $both_0mod8 # U : Yes
57 ble $18, $nomoredata # U : done with the copy?
58 bne $1, $head_align # U :
62 bne $1, $no_unroll # U :
64 beq $1, $do_unroll # U : no single quads to fiddle
75 bne $1, $single_head_quad # U : still not fully aligned
80 bne $1, $tail_quads # U : Nope
140 blt $18, $less_than_8 # U : Nope
[all …]
/arch/parisc/kernel/
Dcompat_audit.c5 ~0U
10 ~0U
15 ~0U
20 ~0U
25 ~0U
Daudit.c8 ~0U
13 ~0U
18 ~0U
23 ~0U
28 ~0U
/arch/x86/ia32/
Daudit.c5 ~0U
10 ~0U
15 ~0U
20 ~0U
25 ~0U
/arch/sparc/kernel/
Dcompat_audit.c7 ~0U
12 ~0U
17 ~0U
22 ~0U
27 ~0U
Daudit.c10 ~0U
15 ~0U
20 ~0U
25 ~0U
30 ~0U
/arch/s390/kernel/
Dcompat_audit.c7 ~0U
12 ~0U
17 ~0U
22 ~0U
27 ~0U
Daudit.c9 ~0U
14 ~0U
19 ~0U
24 ~0U
29 ~0U
/arch/powerpc/kernel/
Dcompat_audit.c6 ~0U
11 ~0U
16 ~0U
21 ~0U
26 ~0U
Daudit.c8 ~0U
13 ~0U
18 ~0U
23 ~0U
28 ~0U
Dalign.c44 #define U 8 /* update index register */ macro
80 { 4, LD+U }, /* 00 1 0000: lwzu */
82 { 4, ST+U }, /* 00 1 0010: stwu */
84 { 2, LD+U }, /* 00 1 0100: lhzu */
85 { 2, LD+SE+U }, /* 00 1 0101: lhau */
86 { 2, ST+U }, /* 00 1 0110: sthu */
88 { 4, LD+F+S+U }, /* 00 1 1000: lfsu */
89 { 8, LD+F+U }, /* 00 1 1001: lfdu */
90 { 4, ST+F+S+U }, /* 00 1 1010: stfsu */
91 { 8, ST+F+U }, /* 00 1 1011: stfdu */
[all …]
/arch/ia64/kernel/
Daudit.c8 ~0U
13 ~0U
18 ~0U
23 ~0U
28 ~0U
/arch/alpha/kernel/
Daudit.c8 ~0U
13 ~0U
18 ~0U
23 ~0U
28 ~0U
/arch/m68k/fpsp040/
Dslogn.S346 |--NOTE THAT U = (Y-F)/F IS VERY SMALL AND THUS APPROXIMATING
347 |--LOG(1+U) CAN BE VERY EFFICIENT.
381 fmulx (%a0),%fp0 | ...FP0 IS U = (Y-F)/F
384 fmulx %fp2,%fp2 | ...FP2 IS V=U*U
387 |--LOG(1+U) IS APPROXIMATED BY
388 |--U + V*(A1+U*(A2+U*(A3+U*(A4+U*(A5+U*A6))))) WHICH IS
389 |--[U + V*(A1+V*(A3+V*A5))] + [U*V*(A2+V*(A4+V*A6))]
410 fmulx %fp0,%fp1 | ...U*V*(A2+V*(A4+V*A6))
411 faddx %fp2,%fp0 | ...U+V*(A1+V*(A3+V*A5)), FP2 RELEASED
413 faddx (%a0),%fp1 | ...LOG(F)+U*V*(A2+V*(A4+V*A6))
[all …]
/arch/x86/kernel/
Daudit_64.c8 ~0U
13 ~0U
18 ~0U
23 ~0U
28 ~0U
/arch/arm/mm/
Dtlb-v7.S50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
52 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
54 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
81 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
83 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA

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