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Searched refs:XCHAL_DCACHE_LINEWIDTH (Results 1 – 9 of 9) sorted by relevance

/arch/xtensa/include/asm/
Dcacheasm.h75 __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
93 __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
102 __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
112 XCHAL_DCACHE_LINEWIDTH
132 __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
141 __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
150 __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
169 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
178 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
187 __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
Dcache.h16 #define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH
22 #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
/arch/xtensa/variants/fsf/include/variant/
Dcore.h117 #define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */ macro
/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
Dcore.h132 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/arch/xtensa/variants/dc232b/include/variant/
Dcore.h124 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/arch/xtensa/variants/dc233c/include/variant/
Dcore.h163 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dcore.h183 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/arch/xtensa/variants/de212/include/variant/
Dcore.h211 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/arch/xtensa/variants/csp/include/variant/
Dcore.h211 #define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ macro