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Searched refs:XCHAL_HAVE_TLBS (Results 1 – 9 of 9) sorted by relevance

/arch/xtensa/include/asm/
Dmmu_context.h29 #if (XCHAL_HAVE_TLBS != 1)
Dinitialize_mmu.h180 #if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS && \
/arch/xtensa/variants/fsf/include/variant/
Dcore.h338 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
Dcore.h363 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/arch/xtensa/variants/dc232b/include/variant/
Dcore.h403 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/arch/xtensa/variants/dc233c/include/variant/
Dcore.h453 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dcore.h510 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/arch/xtensa/variants/de212/include/variant/
Dcore.h574 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/arch/xtensa/variants/csp/include/variant/
Dcore.h553 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro