Home
last modified time | relevance | path

Searched refs:XCHAL_ICACHE_SIZE (Results 1 – 11 of 11) sorted by relevance

/arch/xtensa/include/asm/
Dcacheasm.h83 #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
84 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
120 #if XCHAL_ICACHE_SIZE
158 #if XCHAL_ICACHE_SIZE
195 #if XCHAL_ICACHE_SIZE
Dcache.h21 #define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
Dinitialize_mmu.h181 (XCHAL_DCACHE_SIZE || XCHAL_ICACHE_SIZE)
201 #if XCHAL_ICACHE_SIZE
/arch/xtensa/variants/fsf/include/variant/
Dcore.h119 #define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */ macro
/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
Dcore.h134 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/arch/xtensa/variants/dc232b/include/variant/
Dcore.h126 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/arch/xtensa/variants/dc233c/include/variant/
Dcore.h165 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dcore.h185 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/arch/xtensa/variants/de212/include/variant/
Dcore.h213 #define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */ macro
/arch/xtensa/variants/csp/include/variant/
Dcore.h213 #define XCHAL_ICACHE_SIZE 65536 /* I-cache size in bytes or 0 */ macro
/arch/xtensa/kernel/
Dsetup.c812 XCHAL_ICACHE_SIZE, in c_show()