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/arch/xtensa/include/asm/
Dcacheasm.h34 .macro __loop_cache_all ar at insn size line_width
36 movi \ar, 0
38 __loopi \ar, \at, \size, (4 << (\line_width))
39 \insn \ar, 0 << (\line_width)
40 \insn \ar, 1 << (\line_width)
41 \insn \ar, 2 << (\line_width)
42 \insn \ar, 3 << (\line_width)
43 __endla \ar, \at, 4 << (\line_width)
48 .macro __loop_cache_range ar as at insn line_width
50 extui \at, \ar, 0, \line_width
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Dasmmacro.h49 .macro __loopi ar, at, size, incr
55 addi \at, \ar, \size
65 .macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
91 add \at, \ar, \at
93 add \at, \ar, \as
104 .macro __loopt ar, as, at, incr_log2
107 sub \at, \as, \ar
137 .macro __endl ar, as
139 bltu \ar, \as, 98b
148 .macro __endla ar, as, incr
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/arch/ia64/lib/
Dxor.S22 .save ar.pfs, r31
23 alloc r31 = ar.pfs, 3, 0, 13, 16
24 .save ar.lc, r30
25 mov r30 = ar.lc
31 mov ar.ec = 6 + 2
38 mov ar.lc = in0
51 mov ar.lc = r30
60 .save ar.pfs, r31
61 alloc r31 = ar.pfs, 4, 0, 20, 24
62 .save ar.lc, r30
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Dflush.S28 alloc r2=ar.pfs,2,0,0,0
42 .save ar.lc,r3
43 mov r3=ar.lc // save ar.lc
47 mov ar.lc=r8
61 mov ar.lc=r3 // restore ar.lc
81 alloc r2=ar.pfs,2,0,0,0
97 .save ar.lc,r3
98 mov r3=ar.lc // save ar.lc
102 mov ar.lc=r8
117 mov ar.lc=r3 // restore ar.lc
Dstrnlen_user.S20 alloc r2=ar.pfs,2,0,0,0
21 .save ar.lc, r16
22 mov r16=ar.lc // preserve ar.lc
28 mov ar.lc=r3
44 mov ar.lc=r16 // restore ar.lc
Dcopy_user.S76 .save ar.pfs, saved_pfs
77 alloc saved_pfs=ar.pfs,3,((2*PIPE_DEPTH+7)&~7),0,((2*PIPE_DEPTH+7)&~7)
87 .save ar.lc, saved_lc
88 mov saved_lc=ar.lc // preserve ar.lc (slow)
99 mov ar.ec=PIPE_DEPTH
103 mov ar.lc=len2 // initialize lc for small count
118 mov ar.lc=saved_lc
120 mov ar.pfs=saved_pfs // restore ar.ec
191 mov ar.ec=PIPE_DEPTH
193 mov ar.lc=cnt
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Dmemcpy.S49 .save ar.pfs, saved_pfs
50 alloc saved_pfs=ar.pfs,3,Nrot,0,Nrot
51 .save ar.lc, saved_lc
52 mov saved_lc=ar.lc
74 mov ar.ec=N
78 mov ar.lc=cnt
107 mov ar.lc=saved_lc
109 mov ar.pfs=saved_pfs
121 mov ar.ec=MEM_LAT
124 mov ar.lc=cnt
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Dcopy_page.S40 .save ar.pfs, saved_pfs
41 alloc saved_pfs=ar.pfs,3,Nrot-3,0,Nrot
47 .save ar.lc, saved_lc
48 mov saved_lc=ar.lc
49 mov ar.ec=PIPE_DEPTH
64 mov ar.lc=lcount
96 mov ar.pfs=saved_pfs
97 mov ar.lc=saved_lc
Dclear_user.S57 .save ar.pfs, saved_pfs
58 alloc saved_pfs=ar.pfs,2,0,0,0
60 .save ar.lc, saved_lc
61 mov saved_lc=ar.lc // preserve ar.lc (slow)
69 mov ar.lc=tmp // initialize lc for small count
90 mov ar.lc=saved_lc
126 mov ar.lc=tmp
154 mov ar.lc=saved_lc
208 mov ar.lc=saved_lc
Dclear_page.S37 .save ar.lc, saved_lc
38 mov saved_lc = ar.lc
41 mov ar.lc = (PREFETCH_LINES - 1)
51 mov ar.lc = r16 // one L3 line per iteration
75 mov ar.lc = saved_lc // restore lc
Dcopy_page_mck.S103 alloc r8 = ar.pfs, 2, Nrot-2, 0, Nrot
108 .save ar.lc, saved_lc
109 mov saved_lc = ar.lc
116 mov ar.ec = 1 // special unrolled loop
119 mov ar.lc = 2*PREFETCH_DIST - 1
138 mov ar.lc = t1 // with 64KB pages, t1 is too big to fit in 8 bits!
139 mov ar.ec = N // # of stages in pipeline
183 mov ar.lc = saved_lc
/arch/ia64/kernel/
Drelocate_kernel.S23 alloc r31=ar.pfs,4,0,0,0
41 mov ar.rsc=0 // put RSE in enforced lazy mode
46 mov r18=ar.rnat
47 mov ar.bspstore=r8
54 mov ar.rnat=r18
83 mov ar.lc=r20
156 mov ar.lc=r14;;
191 alloc loc0=ar.pfs,1,2,0,0
193 mov ar.rsc=0 // put RSE in enforced lazy mode
205 mov r4=ar.rnat
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Dpal.S33 alloc r3=ar.pfs,1,0,0,0
58 alloc loc1 = ar.pfs,4,5,0,0
68 mov loc4=ar.rsc // save RSE configuration
70 mov ar.rsc=0 // put RSE in enforced lazy, LE mode
84 mov ar.rsc = loc4 // restore RSE configuration
85 mov ar.pfs = loc1
102 alloc loc1 = ar.pfs,4,4,4,0
121 mov ar.pfs = loc1
150 alloc loc1 = ar.pfs,4,7,0,0
167 mov loc4=ar.rsc // save RSE configuration
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Dgate.S104 .savesp ar.unat, UNAT_OFF+SIGCONTEXT_OFF; \
105 .savesp ar.fpsr, FPSR_OFF+SIGCONTEXT_OFF; \
108 .savesp ar.pfs, CFM_OFF+SIGCONTEXT_OFF; \
128 mov.m r9=ar.bsp // fetch ar.bsp
129 .spillsp.p p1, ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
132 alloc r8=ar.pfs,0,0,3,0
143 .spillsp ar.bsp, BSP_OFF+SIGCONTEXT_OFF
167 mov r14=ar.bsp
197 mov ar.rsc=0 // put RSE into enforced lazy mode
199 .save ar.rnat, r19
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Dminstate.h10 (pUStk) mov.m r20=ar.itc;
49 mov r27=ar.rsc; /* M */ \
51 mov r25=ar.unat; /* M */ \
53 mov r26=ar.pfs; /* I */ \
55 mov r21=ar.fpsr; /* M */ \
69 (pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \
71 (pUStk) mov.m r24=ar.rnat; \
77 (pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \
79 (pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \
82 (pUStk) mov r18=ar.bsp; \
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Desi_stub.S50 alloc loc1=ar.pfs,2,7,8,0
71 mov loc4=ar.rsc // save RSE configuration
72 mov ar.rsc=0 // put RSE in enforced lazy, LE mode
87 .ret1: mov ar.rsc=0 // put RSE in enforced lazy, LE mode
92 .ret2: mov ar.rsc=loc4 // restore RSE configuration
93 mov ar.pfs=loc1
Defi_stub.S47 alloc loc1=ar.pfs,8,7,7,0
53 mov loc4=ar.rsc // save RSE configuration
54 mov ar.rsc=0 // put RSE in enforced lazy, LE mode
76 .ret1: mov ar.rsc=0 // put RSE in enforced lazy, LE mode
81 .ret2: mov ar.rsc=loc4 // restore RSE configuration
82 mov ar.pfs=loc1
Dentry.h31 .spillsp ar.pfs, PT(CR_IFS)+16+(off); \
32 .spillsp ar.unat, PT(AR_UNAT)+16+(off); \
33 .spillsp ar.fpsr, PT(AR_FPSR)+16+(off); \
42 .savesp ar.unat,SW(CALLER_UNAT)+16+(off); \
43 .savesp ar.fpsr,SW(AR_FPSR)+16+(off); \
59 .spillsp ar.pfs,SW(AR_PFS)+16+(off); .spillsp ar.lc,SW(AR_LC)+16+(off); \
61 .spillsp ar.rnat,SW(AR_RNAT)+16+(off); \
62 .spillsp ar.bspstore,SW(AR_BSPSTORE)+16+(off); \
Dmca_drv_asm.S20 alloc r16=ar.pfs,0,2,3,0 // make a new frame
21 mov ar.rsc=0
28 mov ar.bspstore=r22
50 mov ar.pfs=loc0
Djprobes.S73 mov r16=ar.rsc
75 mov ar.rsc=r0
79 mov ar.rsc=r16
Dentry.S64 alloc loc1=ar.pfs,8,2,3,0
74 mov ar.pfs=loc1 // restore ar.pfs
79 (p6) mov ar.pfs=r0 // clear ar.pfs on success
88 mov ar.unat=0; mov ar.lc=0
112 alloc r16=ar.pfs,8,2,6,0
129 mov ar.pfs=loc1
143 alloc r16=ar.pfs,8,2,6,0
160 mov ar.pfs=loc1
173 alloc r16=ar.pfs,1,0,0,0
246 mov r17=ar.unat // preserve caller's
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Dmca_asm.S82 mov ar.lc=r20
262 mov ar.rsc=3 // set eager mode for C handler
267 alloc r14=ar.pfs,0,0,3,0
283 alloc r14=ar.pfs,0,0,0,0 // remove the MCA handler frame
371 mov ar.rsc=3 // set eager mode for C handler
376 alloc r14=ar.pfs,0,0,3,0
397 alloc r14=ar.pfs,0,0,0,0 // remove the INIT handler frame
524 mov temp3=ar.csd
525 mov temp4=ar.ssd
530 mov temp3=ar.unat
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/arch/ia64/include/asm/
Dmca_asm.h87 mov ar.rsc = 0 ; \
90 mov temp2 = ar.bspstore; \
94 mov temp1 = ar.rnat; \
96 mov ar.bspstore = temp2; \
98 mov ar.rnat = temp1; \
170 mov ar.rsc = 0; \
173 mov r13 = ar.k6; \
174 mov temp2 = ar.bspstore; \
178 mov temp1 = ar.rnat; \
180 mov ar.bspstore = temp2; \
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/arch/s390/kvm/
Dgaccess.h165 ar_t ar, unsigned long *gpa, enum gacc_mode mode);
166 int check_gva_range(struct kvm_vcpu *vcpu, unsigned long gva, ar_t ar,
169 int access_guest(struct kvm_vcpu *vcpu, unsigned long ga, ar_t ar, void *data,
221 int write_guest(struct kvm_vcpu *vcpu, unsigned long ga, ar_t ar, void *data, in write_guest() argument
224 return access_guest(vcpu, ga, ar, data, len, GACC_STORE); in write_guest()
241 int read_guest(struct kvm_vcpu *vcpu, unsigned long ga, ar_t ar, void *data, in read_guest() argument
244 return access_guest(vcpu, ga, ar, data, len, GACC_FETCH); in read_guest()
Dpriv.c57 ar_t ar; in handle_set_clock() local
63 op2 = kvm_s390_get_base_disp_s(vcpu, &ar); in handle_set_clock()
66 rc = read_guest(vcpu, op2, ar, &val, sizeof(val)); in handle_set_clock()
82 ar_t ar; in handle_set_prefix() local
89 operand2 = kvm_s390_get_base_disp_s(vcpu, &ar); in handle_set_prefix()
96 rc = read_guest(vcpu, operand2, ar, &address, sizeof(address)); in handle_set_prefix()
120 ar_t ar; in handle_store_prefix() local
127 operand2 = kvm_s390_get_base_disp_s(vcpu, &ar); in handle_store_prefix()
136 rc = write_guest(vcpu, operand2, ar, &address, sizeof(address)); in handle_store_prefix()
150 ar_t ar; in handle_store_cpu_address() local
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