/arch/arm/mach-omap1/ |
D | clock.h | 22 struct clk; 35 .clk = ck, \ 48 #define __clk_get_name(clk) (clk->name) argument 49 #define __clk_get_parent(clk) (clk->parent) argument 50 #define __clk_get_rate(clk) (clk->rate) argument 71 int (*enable)(struct clk *); 72 void (*disable)(struct clk *); 73 void (*find_idlest)(struct clk *, void __iomem **, 75 void (*find_companion)(struct clk *, void __iomem **, 77 void (*allow_idle)(struct clk *); [all …]
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D | clock.c | 34 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; 44 unsigned long omap1_uart_recalc(struct clk *clk) in omap1_uart_recalc() argument 46 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc() 47 return val & clk->enable_bit ? 48000000 : 12000000; in omap1_uart_recalc() 50 unsigned long omap1_sossi_recalc(struct clk *clk) in omap1_sossi_recalc() argument 57 return clk->parent->rate / div; in omap1_sossi_recalc() 60 static void omap1_clk_allow_idle(struct clk *clk) in omap1_clk_allow_idle() argument 62 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; in omap1_clk_allow_idle() 64 if (!(clk->flags & CLOCK_IDLE_CONTROL)) in omap1_clk_allow_idle() 71 static void omap1_clk_deny_idle(struct clk *clk) in omap1_clk_deny_idle() argument [all …]
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/arch/c6x/platforms/ |
D | pll.c | 31 static void __clk_enable(struct clk *clk) in __clk_enable() argument 33 if (clk->parent) in __clk_enable() 34 __clk_enable(clk->parent); in __clk_enable() 35 clk->usecount++; in __clk_enable() 38 static void __clk_disable(struct clk *clk) in __clk_disable() argument 40 if (WARN_ON(clk->usecount == 0)) in __clk_disable() 42 --clk->usecount; in __clk_disable() 44 if (clk->parent) in __clk_disable() 45 __clk_disable(clk->parent); in __clk_disable() 48 int clk_enable(struct clk *clk) in clk_enable() argument [all …]
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/arch/mips/lantiq/ |
D | clk.c | 29 static struct clk cpu_clk_generic[4]; 40 struct clk *clk_get_cpu(void) in clk_get_cpu() 45 struct clk *clk_get_fpi(void) in clk_get_fpi() 51 struct clk *clk_get_io(void) in clk_get_io() 56 struct clk *clk_get_ppe(void) in clk_get_ppe() 62 static inline int clk_good(struct clk *clk) in clk_good() argument 64 return clk && !IS_ERR(clk); in clk_good() 67 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument 69 if (unlikely(!clk_good(clk))) in clk_get_rate() 72 if (clk->rate != 0) in clk_get_rate() [all …]
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/arch/arm/mach-davinci/ |
D | clock.c | 34 static void __clk_enable(struct clk *clk) in __clk_enable() argument 36 if (clk->parent) in __clk_enable() 37 __clk_enable(clk->parent); in __clk_enable() 38 if (clk->usecount++ == 0) { in __clk_enable() 39 if (clk->flags & CLK_PSC) in __clk_enable() 40 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, in __clk_enable() 41 true, clk->flags); in __clk_enable() 42 else if (clk->clk_enable) in __clk_enable() 43 clk->clk_enable(clk); in __clk_enable() 47 static void __clk_disable(struct clk *clk) in __clk_disable() argument [all …]
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/arch/m68k/coldfire/ |
D | clk.c | 30 void __clk_init_enabled(struct clk *clk) in __clk_init_enabled() argument 32 clk->enabled = 1; in __clk_init_enabled() 33 clk->clk_ops->enable(clk); in __clk_init_enabled() 36 void __clk_init_disabled(struct clk *clk) in __clk_init_disabled() argument 38 clk->enabled = 0; in __clk_init_disabled() 39 clk->clk_ops->disable(clk); in __clk_init_disabled() 42 static void __clk_enable0(struct clk *clk) in __clk_enable0() argument 44 __raw_writeb(clk->slot, MCFPM_PPMCR0); in __clk_enable0() 47 static void __clk_disable0(struct clk *clk) in __clk_disable0() argument 49 __raw_writeb(clk->slot, MCFPM_PPMSR0); in __clk_disable0() [all …]
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/arch/avr32/mach-at32ap/ |
D | clock.c | 31 void at32_clk_register(struct clk *clk) in at32_clk_register() argument 35 list_add_tail(&clk->list, &at32_clock_list); in at32_clk_register() 39 static struct clk *__clk_get(struct device *dev, const char *id) in __clk_get() 41 struct clk *clk; in __clk_get() local 43 list_for_each_entry(clk, &at32_clock_list, list) { in __clk_get() 44 if (clk->dev == dev && strcmp(id, clk->name) == 0) { in __clk_get() 45 return clk; in __clk_get() 52 struct clk *clk_get(struct device *dev, const char *id) in clk_get() 54 struct clk *clk; in clk_get() local 57 clk = __clk_get(dev, id); in clk_get() [all …]
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D | clock.h | 18 void at32_clk_register(struct clk *clk); 20 struct clk { struct 24 struct clk *parent; /* Parent clock, if any */ argument 25 void (*mode)(struct clk *clk, int enabled); argument 26 unsigned long (*get_rate)(struct clk *clk); argument 27 long (*set_rate)(struct clk *clk, unsigned long rate, argument 29 int (*set_parent)(struct clk *clk, struct clk *parent); argument 34 unsigned long pba_clk_get_rate(struct clk *clk); argument 35 void pba_clk_mode(struct clk *clk, int enabled);
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/arch/mips/ralink/ |
D | clk.c | 19 struct clk { struct 26 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); in ralink_clk_add() argument 28 if (!clk) in ralink_clk_add() 31 clk->cl.dev_id = dev; in ralink_clk_add() 32 clk->cl.clk = clk; in ralink_clk_add() 34 clk->rate = rate; in ralink_clk_add() 36 clkdev_add(&clk->cl); in ralink_clk_add() 42 int clk_enable(struct clk *clk) in clk_enable() argument 48 void clk_disable(struct clk *clk) in clk_disable() argument 53 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument [all …]
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/arch/arm/mach-mmp/ |
D | clock.c | 19 static void apbc_clk_enable(struct clk *clk) in apbc_clk_enable() argument 23 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel); in apbc_clk_enable() 24 __raw_writel(clk_rst, clk->clk_rst); in apbc_clk_enable() 27 static void apbc_clk_disable(struct clk *clk) in apbc_clk_disable() argument 29 __raw_writel(0, clk->clk_rst); in apbc_clk_disable() 37 static void apmu_clk_enable(struct clk *clk) in apmu_clk_enable() argument 39 __raw_writel(clk->enable_val, clk->clk_rst); in apmu_clk_enable() 42 static void apmu_clk_disable(struct clk *clk) in apmu_clk_disable() argument 44 __raw_writel(0, clk->clk_rst); in apmu_clk_disable() 54 int clk_enable(struct clk *clk) in clk_enable() argument [all …]
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/arch/arm/mach-sa1100/ |
D | clock.c | 21 void (*enable)(struct clk *); 22 void (*disable)(struct clk *); 23 unsigned long (*get_rate)(struct clk *); 26 struct clk { struct 32 struct clk clk_##_name = { \ argument 38 static void clk_gpio27_enable(struct clk *clk) in clk_gpio27_enable() argument 49 static void clk_gpio27_disable(struct clk *clk) in clk_gpio27_disable() argument 56 static void clk_cpu_enable(struct clk *clk) in clk_cpu_enable() argument 60 static void clk_cpu_disable(struct clk *clk) in clk_cpu_disable() argument 64 static unsigned long clk_cpu_get_rate(struct clk *clk) in clk_cpu_get_rate() argument [all …]
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/arch/mips/bcm63xx/ |
D | clk.c | 19 struct clk { struct 20 void (*set)(struct clk *, int); argument 29 static void clk_enable_unlocked(struct clk *clk) in clk_enable_unlocked() argument 31 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked() 32 clk->set(clk, 1); in clk_enable_unlocked() 35 static void clk_disable_unlocked(struct clk *clk) in clk_disable_unlocked() argument 37 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked() 38 clk->set(clk, 0); in clk_disable_unlocked() 56 static void enet_misc_set(struct clk *clk, int enable) in enet_misc_set() argument 72 static struct clk clk_enet_misc = { [all …]
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/arch/arm/boot/dts/ |
D | stih418-clock.dtsi | 15 compatible = "st,stih418-clk", "simple-bus"; 20 clk_sysin: clk-sysin { 30 arm_periph_clk: clk-m-a9-periphs { 58 clk_m_a9: clk-m-a9@92b0000 { 72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { 78 clock-output-names = "clk-m-a9-ext2f-div2"; 92 clock-output-names = "clk-s-icn-reg-0"; 99 clk_s_a0_pll: clk-s-a0-pll { 105 clock-output-names = "clk-s-a0-pll-ofd-0"; 108 clk_s_a0_flexgen: clk-s-a0-flexgen { [all …]
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D | stih410-clock.dtsi | 15 compatible = "st,stih410-clk", "simple-bus"; 20 clk_sysin: clk-sysin { 30 arm_periph_clk: clk-m-a9-periphs { 58 clk_m_a9: clk-m-a9@92b0000 { 72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { 78 clock-output-names = "clk-m-a9-ext2f-div2"; 92 clock-output-names = "clk-s-icn-reg-0"; 99 clk_s_a0_pll: clk-s-a0-pll { 105 clock-output-names = "clk-s-a0-pll-ofd-0"; 106 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ [all …]
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D | stih407-clock.dtsi | 18 clk_sysin: clk-sysin { 27 arm_periph_clk: clk-m-a9-periphs { 56 clk_m_a9: clk-m-a9@92b0000 { 70 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { 76 clock-output-names = "clk-m-a9-ext2f-div2"; 90 clock-output-names = "clk-s-icn-reg-0"; 97 clk_s_a0_pll: clk-s-a0-pll { 103 clock-output-names = "clk-s-a0-pll-ofd-0"; 106 clk_s_a0_flexgen: clk-s-a0-flexgen { 114 clock-output-names = "clk-ic-lmi0"; [all …]
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D | stih415-clock.dtsi | 20 clk_sysin: clk-sysin { 32 clk_s_a0_pll: clk-s-a0-pll { 38 clock-output-names = "clk-s-a0-pll0-hs", 39 "clk-s-a0-pll0-ls", 40 "clk-s-a0-pll1"; 43 clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { 50 clock-output-names = "clk-s-a0-osc-prediv"; 53 clk_s_a0_hs: clk-s-a0-hs { 62 clock-output-names = "clk-s-fdma-0", 63 "clk-s-fdma-1", [all …]
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D | stih416-clock.dtsi | 21 clk_sysin: clk-sysin { 33 clk_s_a0_pll: clk-s-a0-pll { 39 clock-output-names = "clk-s-a0-pll0-hs", 40 "clk-s-a0-pll0-ls", 41 "clk-s-a0-pll1"; 44 clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { 51 clock-output-names = "clk-s-a0-osc-prediv"; 54 clk_s_a0_hs: clk-s-a0-hs { 63 clock-output-names = "clk-s-fdma-0", 64 "clk-s-fdma-1", [all …]
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/arch/blackfin/mach-bf609/ |
D | clock.c | 57 .clk = &_clk, \ 89 int clk_enable(struct clk *clk) in clk_enable() argument 92 if (clk->ops && clk->ops->enable) in clk_enable() 93 ret = clk->ops->enable(clk); in clk_enable() 98 void clk_disable(struct clk *clk) in clk_disable() argument 100 if (clk->ops && clk->ops->disable) in clk_disable() 101 clk->ops->disable(clk); in clk_disable() 106 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument 109 if (clk->ops && clk->ops->get_rate) in clk_get_rate() 110 ret = clk->ops->get_rate(clk); in clk_get_rate() [all …]
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/arch/mips/include/asm/ |
D | clock.h | 9 struct clk; 12 void (*init) (struct clk *clk); 13 void (*enable) (struct clk *clk); 14 void (*disable) (struct clk *clk); 15 void (*recalc) (struct clk *clk); 16 int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id); 17 long (*round_rate) (struct clk *clk, unsigned long rate); 20 struct clk { struct 26 struct clk *parent; argument 40 int __clk_enable(struct clk *); argument [all …]
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/arch/mips/lantiq/xway/ |
D | clk.c | 59 unsigned long clk; in ltq_danube_pp32_hz() local 63 clk = CLOCK_240M; in ltq_danube_pp32_hz() 66 clk = CLOCK_222M; in ltq_danube_pp32_hz() 69 clk = CLOCK_133M; in ltq_danube_pp32_hz() 72 clk = CLOCK_266M; in ltq_danube_pp32_hz() 76 return clk; in ltq_danube_pp32_hz() 107 unsigned long clk; in ltq_vr9_cpu_hz() local 113 clk = CLOCK_600M; in ltq_vr9_cpu_hz() 116 clk = CLOCK_500M; in ltq_vr9_cpu_hz() 119 clk = CLOCK_393M; in ltq_vr9_cpu_hz() [all …]
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/arch/arm/mach-ep93xx/ |
D | clock.c | 30 struct clk { struct 31 struct clk *parent; argument 38 unsigned long (*get_rate)(struct clk *clk); argument 39 int (*set_rate)(struct clk *clk, unsigned long rate); argument 43 static unsigned long get_uart_rate(struct clk *clk); 45 static int set_keytchclk_rate(struct clk *clk, unsigned long rate); 46 static int set_div_rate(struct clk *clk, unsigned long rate); 47 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate); 48 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate); 50 static struct clk clk_xtali = { [all …]
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/arch/sh/kernel/cpu/sh4/ |
D | clock-sh4-202.c | 25 static unsigned long emi_clk_recalc(struct clk *clk) in emi_clk_recalc() argument 28 return clk->parent->rate / frqcr3_divisors[idx]; in emi_clk_recalc() 31 static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) in frqcr3_lookup() argument 33 int divisor = clk->parent->rate / rate; in frqcr3_lookup() 48 static struct clk sh4202_emi_clk = { 53 static unsigned long femi_clk_recalc(struct clk *clk) in femi_clk_recalc() argument 56 return clk->parent->rate / frqcr3_divisors[idx]; in femi_clk_recalc() 63 static struct clk sh4202_femi_clk = { 68 static void shoc_clk_init(struct clk *clk) in shoc_clk_init() argument 84 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) in shoc_clk_init() [all …]
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/arch/mips/lantiq/falcon/ |
D | sysctrl.c | 82 static inline void sysctl_wait(struct clk *clk, in sysctl_wait() argument 87 do {} while (--err && ((sysctl_r32(clk->module, reg) in sysctl_wait() 88 & clk->bits) != test)); in sysctl_wait() 91 clk->module, clk->bits, test, in sysctl_wait() 92 sysctl_r32(clk->module, reg) & clk->bits); in sysctl_wait() 95 static int sysctl_activate(struct clk *clk) in sysctl_activate() argument 97 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); in sysctl_activate() 98 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); in sysctl_activate() 99 sysctl_wait(clk, clk->bits, SYSCTL_ACTS); in sysctl_activate() 103 static void sysctl_deactivate(struct clk *clk) in sysctl_deactivate() argument [all …]
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/arch/mips/loongson64/lemote-2f/ |
D | clock.c | 44 static struct clk cpu_clk = { 50 struct clk *clk_get(struct device *dev, const char *id) in clk_get() 56 static void propagate_rate(struct clk *clk) in propagate_rate() argument 58 struct clk *clkp; in propagate_rate() 61 if (likely(clkp->parent != clk)) in propagate_rate() 70 int clk_enable(struct clk *clk) in clk_enable() argument 76 void clk_disable(struct clk *clk) in clk_disable() argument 81 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument 83 return (unsigned long)clk->rate; in clk_get_rate() 87 void clk_put(struct clk *clk) in clk_put() argument [all …]
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/arch/arm/mach-w90x900/ |
D | clock.c | 32 int clk_enable(struct clk *clk) in clk_enable() argument 37 if (clk->enabled++ == 0) in clk_enable() 38 (clk->enable)(clk, 1); in clk_enable() 45 void clk_disable(struct clk *clk) in clk_disable() argument 49 WARN_ON(clk->enabled == 0); in clk_disable() 52 if (--clk->enabled == 0) in clk_disable() 53 (clk->enable)(clk, 0); in clk_disable() 58 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument 64 void nuc900_clk_enable(struct clk *clk, int enable) in nuc900_clk_enable() argument 66 unsigned int clocks = clk->cken; in nuc900_clk_enable() [all …]
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