Home
last modified time | relevance | path

Searched refs:cntval_mask (Results 1 – 9 of 9) sorted by relevance

/arch/x86/events/intel/
Dp6.c225 .cntval_mask = (1ULL << 32) - 1,
Dknc.c307 .cntval_mask = (1ULL << 40) - 1,
Dp4.c1322 .cntval_mask = ARCH_P4_CNTRVAL_MASK,
Dds.c924 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; in intel_pmu_pebs_enable()
Dcore.c3604 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in intel_pmu_init()
4040 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; in intel_pmu_init()
/arch/tile/kernel/
Dperf_event.c75 u64 cntval_mask; /* counter width mask */ member
336 .cntval_mask = (1ULL << 32) - 1,
581 write_counter(idx, (u64)(-left) & tile_pmu->cntval_mask); in tile_event_set_period()
/arch/x86/events/amd/
Dcore.c638 .cntval_mask = (1ULL << 48) - 1,
/arch/x86/events/
Dcore.c1160 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); in x86_perf_event_set_period()
1170 (u64)(-left) & x86_pmu.cntval_mask); in x86_perf_event_set_period()
1818 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); in init_hw_perf_events()
Dperf_event.h525 u64 cntval_mask; member