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/arch/m68k/sun3x/
Ddvma.c44 #define dvma_entry_paddr(index) (iommu_pte[index] & IOMMU_ADDR_MASK) argument
45 #define dvma_entry_vaddr(index,paddr) ((index << DVMA_PAGE_SHIFT) | \ argument
48 #define dvma_entry_set(index,addr) (iommu_pte[index] = \
52 #define dvma_entry_set(index,addr) (iommu_pte[index] = \ argument
56 #define dvma_entry_clr(index) (iommu_pte[index] = IOMMU_DT_INVALID) argument
68 unsigned long index; in dvma_print() local
70 index = dvma_addr >> DVMA_PAGE_SHIFT; in dvma_print()
72 printk("idx %lx dvma_addr %08lx paddr %08lx\n", index, dvma_addr, in dvma_print()
73 dvma_entry_paddr(index)); in dvma_print()
154 unsigned long end, index; in dvma_map_iommu() local
[all …]
/arch/mips/cavium-octeon/executive/
Dcvmx-helper-sgmii.c44 void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
45 void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
55 static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index) in __cvmx_helper_sgmii_hardware_init_one_time() argument
63 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time()
65 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); in __cvmx_helper_sgmii_hardware_init_one_time()
73 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time()
75 cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time()
85 cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_one_time()
101 cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time()
106 cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_one_time()
[all …]
Dcvmx-helper-rgmii.c104 int index = port & 0xf; in cvmx_helper_rgmii_internal_loopback() local
112 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); in cvmx_helper_rgmii_internal_loopback()
113 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); in cvmx_helper_rgmii_internal_loopback()
114 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); in cvmx_helper_rgmii_internal_loopback()
115 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); in cvmx_helper_rgmii_internal_loopback()
117 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp); in cvmx_helper_rgmii_internal_loopback()
119 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp); in cvmx_helper_rgmii_internal_loopback()
121 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp); in cvmx_helper_rgmii_internal_loopback()
123 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); in cvmx_helper_rgmii_internal_loopback()
270 int index = cvmx_helper_get_interface_index_num(ipd_port); in __cvmx_helper_rgmii_link_get() local
[all …]
/arch/m68k/coldfire/
Dintc-5272.c40 unsigned char index; member
45 /*MCF_IRQ_SPURIOUS*/ { .icr = 0, .index = 0, .ack = 0, },
46 /*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
47 /*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
48 /*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
49 /*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
50 /*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
51 /*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, },
52 /*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, },
53 /*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, },
[all …]
/arch/mips/cavium-octeon/crypto/
Docteon-crypto.h31 #define write_octeon_64bit_hash_dword(value, index) \ argument
34 "dmtc2 %[rt],0x0048+" STR(index) \
42 #define read_octeon_64bit_hash_dword(index) \ argument
47 "dmfc2 %[rt],0x0048+" STR(index) \
57 #define write_octeon_64bit_block_dword(value, index) \ argument
60 "dmtc2 %[rt],0x0040+" STR(index) \
105 #define write_octeon_64bit_hash_sha512(value, index) \ argument
108 "dmtc2 %[rt],0x0250+" STR(index) \
116 #define read_octeon_64bit_hash_sha512(index) \ argument
121 "dmfc2 %[rt],0x0250+" STR(index) \
[all …]
/arch/powerpc/xmon/
Dspu-dis.c57 const struct spu_opcode *index; in get_index_for_opcode() local
65 if ((index = spu_disassemble_table[opcode & 0x780]) != 0 in get_index_for_opcode()
66 && index->insn_type == RRR) in get_index_for_opcode()
67 return index; in get_index_for_opcode()
69 if ((index = spu_disassemble_table[opcode & 0x7f0]) != 0 in get_index_for_opcode()
70 && (index->insn_type == RI18 || index->insn_type == LBT)) in get_index_for_opcode()
71 return index; in get_index_for_opcode()
73 if ((index = spu_disassemble_table[opcode & 0x7f8]) != 0 in get_index_for_opcode()
74 && index->insn_type == RI10) in get_index_for_opcode()
75 return index; in get_index_for_opcode()
[all …]
/arch/ia64/include/uapi/asm/
Dintel_intrin.h81 #define __ia64_set_dbr(index, val) \ argument
82 __setIndReg(_IA64_REG_INDR_DBR, index, val)
83 #define ia64_set_ibr(index, val) \ argument
84 __setIndReg(_IA64_REG_INDR_IBR, index, val)
85 #define ia64_set_pkr(index, val) \ argument
86 __setIndReg(_IA64_REG_INDR_PKR, index, val)
87 #define ia64_set_pmc(index, val) \ argument
88 __setIndReg(_IA64_REG_INDR_PMC, index, val)
89 #define ia64_set_pmd(index, val) \ argument
90 __setIndReg(_IA64_REG_INDR_PMD, index, val)
[all …]
Dgcc_intrin.h424 #define __ia64_set_dbr(index, val) \ argument
425 asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory")
427 #define ia64_set_ibr(index, val) \ argument
428 asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory")
430 #define ia64_set_pkr(index, val) \ argument
431 asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory")
433 #define ia64_set_pmc(index, val) \ argument
434 asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory")
436 #define ia64_set_pmd(index, val) \ argument
437 asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory")
[all …]
/arch/s390/crypto/
Dsha_common.c25 unsigned int index, n; in s390_sha_update() local
28 index = ctx->count & (bsize - 1); in s390_sha_update()
31 if ((index + len) < bsize) in s390_sha_update()
35 if (index) { in s390_sha_update()
36 memcpy(ctx->buf + index, data, bsize - index); in s390_sha_update()
38 data += bsize - index; in s390_sha_update()
39 len -= bsize - index; in s390_sha_update()
40 index = 0; in s390_sha_update()
52 memcpy(ctx->buf + index , data, len); in s390_sha_update()
63 unsigned int index, end, plen; in s390_sha_final() local
[all …]
/arch/powerpc/kernel/
Dlegacy_serial.c80 int index; in add_legacy_port() local
97 index = want_index; in add_legacy_port()
99 index = legacy_serial_count; in add_legacy_port()
105 if (index >= MAX_LEGACY_SERIAL_PORTS) in add_legacy_port()
107 if (index >= legacy_serial_count) in add_legacy_port()
108 legacy_serial_count = index + 1; in add_legacy_port()
111 if (legacy_serial_infos[index].np != NULL) { in add_legacy_port()
115 index, legacy_serial_count); in add_legacy_port()
117 legacy_serial_ports[index]; in add_legacy_port()
119 legacy_serial_infos[index]; in add_legacy_port()
[all …]
Dptrace32.c86 int index; in compat_arch_ptrace() local
91 index = (unsigned long) addr >> 2; in compat_arch_ptrace()
92 if ((addr & 3) || (index > PT_FPSCR32)) in compat_arch_ptrace()
96 if (index < PT_FPR0) { in compat_arch_ptrace()
97 ret = ptrace_get_reg(child, index, &tmp); in compat_arch_ptrace()
108 [FPRINDEX(index)]; in compat_arch_ptrace()
123 u32 index; in compat_arch_ptrace() local
131 index = (u64)addr >> 2; in compat_arch_ptrace()
132 numReg = index / 2; in compat_arch_ptrace()
134 if (index % 2) in compat_arch_ptrace()
[all …]
/arch/ia64/sn/pci/pcibr/
Dpcibr_ate.c24 int index; in mark_ate() local
27 for (index = start; length < number; index++, length++) in mark_ate()
28 ate[index] = value; in mark_ate()
39 int index; in find_free_ate() local
42 for (index = start; index < ate_resource->num_ate;) { in find_free_ate()
43 if (!ate[index]) { in find_free_ate()
47 start_free = index; /* Found start free ate */ in find_free_ate()
53 index = i + 1; in find_free_ate()
60 index++; /* Try next ate */ in find_free_ate()
160 void pcibr_ate_free(struct pcibus_info *pcibus_info, int index) in pcibr_ate_free() argument
[all …]
/arch/alpha/kernel/
Dcore_tsunami.c179 tsunami_pchip *pchip = hose->index ? TSUNAMI_pchip1 : TSUNAMI_pchip0; in tsunami_pci_tbi()
246 tsunami_init_one_pchip(tsunami_pchip *pchip, int index) in tsunami_init_one_pchip() argument
254 if (index == 0) in tsunami_init_one_pchip()
266 = (TSUNAMI_MEM(index) & 0xffffffffffL) | 0x80000000000L; in tsunami_init_one_pchip()
268 = (TSUNAMI_IO(index) & 0xffffffffffL) | 0x80000000000L; in tsunami_init_one_pchip()
270 hose->config_space_base = TSUNAMI_CONF(index); in tsunami_init_one_pchip()
271 hose->index = index; in tsunami_init_one_pchip()
273 hose->io_space->start = TSUNAMI_IO(index) - TSUNAMI_IO_BIAS; in tsunami_init_one_pchip()
275 hose->io_space->name = pci_io_names[index]; in tsunami_init_one_pchip()
278 hose->mem_space->start = TSUNAMI_MEM(index) - TSUNAMI_MEM_BIAS; in tsunami_init_one_pchip()
[all …]
/arch/parisc/math-emu/
Ddecode_exc.c69 #define Excp_type(index) Exceptiontype(Fpu_register[index]) argument
70 #define Excp_instr(index) Instructionfield(Fpu_register[index]) argument
71 #define Clear_excp_register(index) Allexception(Fpu_register[index]) = 0 argument
76 #define Fpu_sgl(index) Fpu_register[index*2] argument
78 #define Fpu_dblp1(index) Fpu_register[index*2] argument
79 #define Fpu_dblp2(index) Fpu_register[(index*2)+1] argument
81 #define Fpu_quadp1(index) Fpu_register[index*2] argument
82 #define Fpu_quadp2(index) Fpu_register[(index*2)+1] argument
83 #define Fpu_quadp3(index) Fpu_register[(index*2)+2] argument
84 #define Fpu_quadp4(index) Fpu_register[(index*2)+3] argument
/arch/powerpc/mm/
Dmmu_context_book3s64.c35 int index; in __init_new_context() local
43 err = ida_get_new_above(&mmu_context_ida, 1, &index); in __init_new_context()
51 if (index > MAX_USER_CONTEXT) { in __init_new_context()
53 ida_remove(&mmu_context_ida, index); in __init_new_context()
58 return index; in __init_new_context()
61 static int radix__init_new_context(struct mm_struct *mm, int index) in radix__init_new_context() argument
69 process_tb[index].prtb0 = cpu_to_be64(rts_field | __pa(mm->pgd) | RADIX_PGD_INDEX_SIZE); in radix__init_new_context()
75 int index; in init_new_context() local
77 index = __init_new_context(); in init_new_context()
78 if (index < 0) in init_new_context()
[all …]
Dfsl_booke_mmu.c110 static void settlbcam(int index, unsigned long virt, phys_addr_t phys, in settlbcam() argument
122 TLBCAM[index].MAS0 = MAS0_TLBSEL(1) | MAS0_ESEL(index) | MAS0_NV(index+1); in settlbcam()
123 TLBCAM[index].MAS1 = MAS1_VALID | MAS1_IPROT | MAS1_TSIZE(tsize) | MAS1_TID(pid); in settlbcam()
124 TLBCAM[index].MAS2 = virt & PAGE_MASK; in settlbcam()
126 TLBCAM[index].MAS2 |= (flags & _PAGE_WRITETHRU) ? MAS2_W : 0; in settlbcam()
127 TLBCAM[index].MAS2 |= (flags & _PAGE_NO_CACHE) ? MAS2_I : 0; in settlbcam()
128 TLBCAM[index].MAS2 |= (flags & _PAGE_COHERENT) ? MAS2_M : 0; in settlbcam()
129 TLBCAM[index].MAS2 |= (flags & _PAGE_GUARDED) ? MAS2_G : 0; in settlbcam()
130 TLBCAM[index].MAS2 |= (flags & _PAGE_ENDIAN) ? MAS2_E : 0; in settlbcam()
132 TLBCAM[index].MAS3 = (phys & MAS3_RPN) | MAS3_SX | MAS3_SR; in settlbcam()
[all …]
/arch/mips/fw/lib/
Dcmdline.c60 int i, yamon, index = 0; in fw_getenv() local
62 yamon = (strchr(fw_envp(index), '=') == NULL); in fw_getenv()
65 while (fw_envp(index)) { in fw_getenv()
66 if (strncmp(envname, fw_envp(index), i) == 0) { in fw_getenv()
68 result = fw_envp(index + 1); in fw_getenv()
70 } else if (fw_envp(index)[i] == '=') { in fw_getenv() local
71 result = fw_envp(index) + i + 1; in fw_getenv()
78 index += 2; in fw_getenv()
80 index += 1; in fw_getenv()
/arch/powerpc/sysdev/
Dmmio_nvram.c37 static ssize_t mmio_nvram_read(char *buf, size_t count, loff_t *index) in mmio_nvram_read() argument
41 if (*index >= mmio_nvram_len) in mmio_nvram_read()
43 if (*index + count > mmio_nvram_len) in mmio_nvram_read()
44 count = mmio_nvram_len - *index; in mmio_nvram_read()
48 memcpy_fromio(buf, mmio_nvram_start + *index, count); in mmio_nvram_read()
52 *index += count; in mmio_nvram_read()
73 static ssize_t mmio_nvram_write(char *buf, size_t count, loff_t *index) in mmio_nvram_write() argument
77 if (*index >= mmio_nvram_len) in mmio_nvram_write()
79 if (*index + count > mmio_nvram_len) in mmio_nvram_write()
80 count = mmio_nvram_len - *index; in mmio_nvram_write()
[all …]
/arch/arm/mach-tegra/
Dcpuidle-tegra30.c40 int index);
69 int index) in tegra30_cpu_cluster_power_down() argument
91 int index) in tegra30_cpu_core_power_down() argument
106 int index) in tegra30_cpu_core_power_down() argument
114 int index) in tegra30_idle_lp2() argument
127 index); in tegra30_idle_lp2()
131 entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index); in tegra30_idle_lp2()
141 return (entered_lp2) ? index : 0; in tegra30_idle_lp2()
/arch/mips/include/asm/octeon/
Dcvmx-cmd-queue.h142 uint64_t index:13; member
356 if (likely(qptr->index + cmd_count < qptr->pool_size_m1)) { in cvmx_cmd_queue_write()
360 ptr += qptr->index; in cvmx_cmd_queue_write()
361 qptr->index += cmd_count; in cvmx_cmd_queue_write()
386 count = qptr->pool_size_m1 - qptr->index; in cvmx_cmd_queue_write()
387 ptr += qptr->index; in cvmx_cmd_queue_write()
398 qptr->index = cmd_count; in cvmx_cmd_queue_write()
454 if (likely(qptr->index + 2 < qptr->pool_size_m1)) { in cvmx_cmd_queue_write2()
458 ptr += qptr->index; in cvmx_cmd_queue_write2()
459 qptr->index += 2; in cvmx_cmd_queue_write2()
[all …]
/arch/x86/kvm/
Dmtrr.c286 int index; in fixed_mtrr_addr_seg_to_range_index() local
289 index = mtrr_seg->range_start; in fixed_mtrr_addr_seg_to_range_index()
290 index += (addr - mtrr_seg->start) >> mtrr_seg->range_shift; in fixed_mtrr_addr_seg_to_range_index()
291 return index; in fixed_mtrr_addr_seg_to_range_index()
294 static u64 fixed_mtrr_range_end_addr(int seg, int index) in fixed_mtrr_range_end_addr() argument
297 int pos = index - mtrr_seg->range_start; in fixed_mtrr_range_end_addr()
320 int index; in update_mtrr() local
338 index = (msr - 0x200) / 2; in update_mtrr()
339 var_mtrr_range(&mtrr_state->var_ranges[index], &start, &end); in update_mtrr()
354 int index, is_mtrr_mask; in set_var_mtrr_msr() local
[all …]
/arch/mips/kernel/
Drtlx.c89 int rtlx_open(int index, int can_sleep) in rtlx_open() argument
96 if (index >= RTLX_CHANNELS) { in rtlx_open()
101 if (atomic_inc_return(&channel_wqs[index].in_open) > 1) { in rtlx_open()
102 pr_debug("rtlx_open channel %d already opened\n", index); in rtlx_open()
112 channel_wqs[index].lx_queue, in rtlx_open()
130 &channel_wqs[index].lx_queue, in rtlx_open()
142 finish_wait(&channel_wqs[index].lx_queue, in rtlx_open()
163 chan = &rtlx->channel[index]; in rtlx_open()
173 atomic_dec(&channel_wqs[index].in_open); in rtlx_open()
180 int rtlx_release(int index) in rtlx_release() argument
[all …]
/arch/powerpc/include/asm/book3s/64/
Dhash-64k.h69 static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index) in __rpte_to_hidx() argument
72 return (rpte.hidx >> (index<<2)) & 0xf; in __rpte_to_hidx()
77 extern bool __rpte_sub_valid(real_pte_t rpte, unsigned long index);
82 #define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift) \ argument
88 for (index = 0; vpn < __end; index++, \
90 if (!__split || __rpte_sub_valid(rpte, index)) \
147 static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index) in hpte_valid() argument
149 return hpte_slot_array[index] & 0x1; in hpte_valid()
153 int index) in hpte_hash_index() argument
155 return hpte_slot_array[index] >> 1; in hpte_hash_index()
[all …]
/arch/s390/kernel/
Dirq.c120 int index = *(loff_t *) v; in show_interrupts() local
124 if (index == 0) { in show_interrupts()
130 if (index < NR_IRQS_BASE) { in show_interrupts()
131 seq_printf(p, "%s: ", irqclass_main_desc[index].name); in show_interrupts()
132 irq = irqclass_main_desc[index].irq; in show_interrupts()
138 if (index > NR_IRQS_BASE) in show_interrupts()
141 for (index = 0; index < NR_ARCH_IRQS; index++) { in show_interrupts()
142 seq_printf(p, "%s: ", irqclass_sub_desc[index].name); in show_interrupts()
143 irq = irqclass_sub_desc[index].irq; in show_interrupts()
147 if (irqclass_sub_desc[index].desc) in show_interrupts()
[all …]
/arch/powerpc/platforms/powernv/
Dopal-nvram.c30 static ssize_t opal_nvram_read(char *buf, size_t count, loff_t *index) in opal_nvram_read() argument
35 if (*index >= nvram_size) in opal_nvram_read()
37 off = *index; in opal_nvram_read()
43 *index += count; in opal_nvram_read()
47 static ssize_t opal_nvram_write(char *buf, size_t count, loff_t *index) in opal_nvram_write() argument
52 if (*index >= nvram_size) in opal_nvram_write()
54 off = *index; in opal_nvram_write()
71 *index += count; in opal_nvram_write()

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