| /arch/parisc/lib/ |
| D | io.c | 168 unsigned int l = 0, l2; in insw() local
220 l2 = cpu_to_le16(inw(port)); in insw()
221 *(unsigned short *)p = (l & 0xff) << 8 | (l2 >> 8); in insw()
223 l = l2; in insw()
240 unsigned int l = 0, l2; in insl() local
267 l2 = cpu_to_le32(inl(port)); in insl()
268 *(unsigned int *)p = (l & 0xffff) << 16 | (l2 >> 16); in insl()
270 l = l2; in insl()
284 l2 = cpu_to_le32(inl(port)); in insl()
285 *(unsigned int *)p = (l & 0xff) << 24 | (l2 >> 8); in insl()
[all …]
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| /arch/sparc/lib/ |
| D | PeeCeeI.c | 36 u32 l, l2; in outsl() local
64 l2 = *(u32 *)src; in outsl()
65 l |= (l2 >> 24); in outsl()
67 l = l2 << 8; in outsl()
76 l2 = *(u32 *)src; in outsl()
77 l |= (l2 >> 8); in outsl()
79 l = l2 << 24; in outsl()
153 u32 l = 0, l2, *pi; in insl() local
165 l2 = __raw_readl(addr); in insl()
166 *pi++ = (l << 16) | (l2 >> 16); in insl()
[all …]
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| D | muldi3.S | 63 add %g1, %g2, %l2
74 mov %l2, %i0
75 add %l2, %l0, %i0
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| D | xor.S | 374 ldda [%i0 + 0x30] %asi, %l2 /* %l2/%l3 = dest + 0x30 */
388 xor %l2, %l0, %l2
390 stxa %l2, [%i0 + 0x30] %asi
567 ldda [%i0 + 0x00] %asi, %l2 /* %l2/%l3 = dest + 0x00 */
577 xor %l2, %l0, %l2
579 stxa %l2, [%i0 + 0x00] %asi
582 ldda [%i0 + 0x10] %asi, %l2 /* %l2/%l3 = dest + 0x10 */
593 xor %l2, %l0, %l2
595 stxa %l2, [%i0 + 0x10] %asi
598 ldda [%i0 + 0x20] %asi, %l2 /* %l2/%l3 = dest + 0x20 */
[all …]
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| D | NGpage.S | 30 ldda [%i1 + 0x20] %asi, %l2
36 stxa %l2, [%i0 + 0x20] %asi
42 ldda [%i1 + 0x60] %asi, %l2
48 stxa %l2, [%i0 + 0x60] %asi
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| /arch/c6x/lib/ |
| D | strasgi.S | 36 || cmpltu .l2 B2, B7, B0
42 || mv .l2 B7, B6
46 || cmpltu .l2 B1, B6, B0
51 || cmpltu .l2 12, B6, B0
56 || cmpltu .l2 8, B6, B0
61 || cmpltu .l2 4, B6, B0
66 || cmpltu .l2 0, B6, B0
71 || cmpltu .l2 B2, B7, B0
75 cmpltu .l2 B1, B6, B0
79 || cmpltu .l2 12, B6, B0
[all …]
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| /arch/s390/lib/ |
| D | string.c | 240 const char *s2, unsigned long l2) in clcle() argument
245 register unsigned long r5 asm("5") = (unsigned long) l2; in clcle()
264 int l1, l2; in strstr() local
266 l2 = __strend(s2) - s2; in strstr()
267 if (!l2) in strstr()
270 while (l1-- >= l2) { in strstr()
273 cc = clcle(s1, l2, s2, l2); in strstr()
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| /arch/sparc/prom/ |
| D | cif.S | 17 ldx [%o1 + 0x0008], %l2 ! prom_cif_handler
21 call %l2
39 ldx [%i1 + 0x000], %l2
40 call %l2
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| /arch/x86/boot/ |
| D | string.c | 154 size_t l1, l2; in strstr() local
156 l2 = strlen(s2); in strstr()
157 if (!l2) in strstr()
160 while (l1 >= l2) { in strstr()
162 if (!memcmp(s1, s2, l2)) in strstr()
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| /arch/sparc/include/asm/ |
| D | head_32.h | 24 jmpl %l2, %g0; rett %l2 + 4; nop; nop;
66 rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;
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| D | ttable.h | 19 clr %l0; clr %l1; clr %l2; clr %l3; \
178 add %l1, 4, %l2; \
181 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC];
237 stx %l2, [%sp + STACK_BIAS + 0x10]; \
258 stx %l2, [%sp + STACK_BIAS + 0x10]; \
286 stxa %l2, [%g1 + %g0] ASI; \
316 stxa %l2, [%sp + STACK_BIAS + 0x10] %asi; \
350 stx %l2, [%g3 + TI_REG_WINDOW + 0x10]; \
382 stwa %l2, [%g1 + %g0] ASI; \
415 stwa %l2, [%sp + 0x08] %asi; \
[all …]
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| /arch/microblaze/lib/ |
| D | mulsi3.S | 27 l2: label
32 beqi r7, l2
33 bneid r6, l2
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| /arch/sparc/kernel/ |
| D | head_64.S | 169 mov 0, %l2
176 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
187 mov (1b - prom_compatible_name), %l2
190 sub %l0, %l2, %l2
202 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
211 mov (1b - prom_chosen_path), %l2
214 sub %l0, %l2, %l2
224 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
232 mov (1b - prom_mmu_name), %l2
235 sub %l0, %l2, %l2
[all …]
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| D | rtrap_64.S | 162 mov %g6, %l2
179 mov %l2, %g6
190 ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
199 wrpr %l2, %g0, %tpc
224 rdpr %otherwin, %l2
227 wrpr %l2, %g0, %canrestore
229 brnz,pt %l2, user_rtt_restore
291 ldub [%l6 + %o0], %l2
295 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
297 and %l2, FPRS_DL, %l6
[all …]
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| D | entry.S | 162 rett %l2
448 mov %l2, %o2
455 jmpl %l2, %g0
456 rett %l2 + 4
468 mov %l2, %o2
516 mov %l2, %o2
555 mov %l2, %o2
572 mov %l2, %o2
589 mov %l2, %o2
606 mov %l2, %o2
[all …]
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| /arch/powerpc/boot/dts/fsl/ |
| D | p4080si-pre.dtsi | 100 L2_0: l2-cache {
110 L2_1: l2-cache {
120 L2_2: l2-cache {
130 L2_3: l2-cache {
140 L2_4: l2-cache {
150 L2_5: l2-cache {
160 L2_6: l2-cache {
170 L2_7: l2-cache {
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| D | t104xsi-pre.dtsi | 80 L2_1: l2-cache {
90 L2_2: l2-cache {
100 L2_3: l2-cache {
110 L2_4: l2-cache {
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| /arch/sparc/power/ |
| D | hibernate_asm.S | 75 ldxa [%l0 + 8] %asi, %l2 /* orig_address */
79 sub %l2, %g7, %l2
84 stxa %g2, [%l2 + %l3] ASI_PHYS_USE_EC
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| /arch/blackfin/include/asm/ |
| D | context.S | 39 [--sp] = l2;
86 l2 = r0; define
111 [--sp] = l2;
146 l2 = r0; define
170 [--sp] = l2;
221 l2 = r0; define
257 l2 = [sp++]; define
327 l2 = [sp++]; define
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| /arch/blackfin/kernel/ |
| D | vmlinux.lds.S | 105 *(.l2.data)
229 *(.l2.text)
235 *(.l2.data)
243 *(.l2.bss)
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| D | kgdb_test.c | 39 static int num2 __attribute__((l2));
40 void kgdb_l2_test(void) __attribute__((l2));
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| /arch/mips/boot/dts/brcm/ |
| D | bcm3384_zephyr.dtsi | 63 compatible = "brcm,bcm3380-l2-intc";
75 compatible = "brcm,bcm3380-l2-intc";
87 compatible = "brcm,bcm3380-l2-intc";
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| /arch/x86/kernel/cpu/ |
| D | intel_cacheinfo.c | 231 union l2_cache l2; in amd_cpuid4() local
240 cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val); in amd_cpuid4()
254 if (!l2.val) in amd_cpuid4()
256 assoc = assocs[l2.assoc]; in amd_cpuid4()
257 line_size = l2.line_size; in amd_cpuid4()
258 lines_per_tag = l2.lines_per_tag; in amd_cpuid4()
653 unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; in init_intel_cacheinfo() local
749 l2 += cache_table[k].size; in init_intel_cacheinfo()
775 l2 = new_l2; in init_intel_cacheinfo()
800 c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d)); in init_intel_cacheinfo()
[all …]
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| D | intel.c | 526 unsigned int l2 = 0; in init_intel() local
550 l2 = init_intel_cacheinfo(c); in init_intel()
553 if (l2 == 0) { in init_intel()
555 l2 = c->x86_cache_size; in init_intel()
570 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); in init_intel()
601 if (l2 == 0) in init_intel()
603 else if (l2 == 256) in init_intel()
608 if (l2 == 128) in init_intel()
615 if (l2 == 128) in init_intel()
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| /arch/arm/boot/dts/ |
| D | uniphier-pxs2.dtsi | 60 next-level-cache = <&l2>;
68 next-level-cache = <&l2>;
76 next-level-cache = <&l2>;
84 next-level-cache = <&l2>;
98 l2: l2-cache@500c0000 { label
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