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Searched refs:r18 (Results 1 – 25 of 110) sorted by relevance

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/arch/ia64/kernel/
Divt.S115 movl r18=PAGE_SHIFT
129 cmp.ne p8,p0=r18,r26
130 sub r27=r26,r18
132 (p8) dep r25=r18,r25,2,6
137 shr.u r18=r22,PGDIR_SHIFT // get bottom portion of pgd index bit
148 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
149 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
154 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
163 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
167 dep r17=r18,r29,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
[all …]
Dgate.S203 mov r18=ar.bspstore
215 extr.u r20=r18,3,6
222 (p8) st8 [r18]=r19 // if bspstore points at RNaT slot, store RNaT there now
246 adds r18=(RNAT_OFF+SIGCONTEXT_OFF),sp
249 ld8 r16=[r18] // get new rnat
250 extr.u r18=r15,3,6 // r18 <- rse_slot_num(bsp0)
268 add r18=r18,r14 // r18 (delta) <- rse_slot_num(bsp0) - rse_num_regs(bspstore1,bsp1)
272 (p7) adds r18=-62,r18 // delta -= 62
274 setf.sig f6=r18
280 add r17=r17,r18
[all …]
Drelocate_kernel.S46 mov r18=ar.rnat
54 mov ar.rnat=r18
69 ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));; // r18=ptce_base
85 ptc.e r18
87 add r18=r22,r18
90 add r18=r21,r18
99 mov r18=KERNEL_TR_PAGE_SHIFT<<2
101 ptr.i r16, r18
102 ptr.d r16, r18
109 mov r18=IA64_GRANULE_SHIFT<<2
[all …]
Dmca_asm.S67 ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));; // r18=ptce_base
84 ptc.e r18
86 add r18=r22,r18
89 add r18=r21,r18
100 mov r18=KERNEL_TR_PAGE_SHIFT<<2
102 ptr.i r16, r18
103 ptr.d r16, r18
113 mov r18=IA64_GRANULE_SHIFT<<2
115 ptr.i r16,r18
126 mov r18=IA64_GRANULE_SHIFT<<2
[all …]
Dminstate.h82 (pUStk) mov r18=ar.bsp; \
97 (pKStk) mov r18=r0; /* make sure r18 isn't NaT */ \
107 (pUStk) sub r18=r18,r22; /* r18=RSE.ndirty*8 */ \
115 shl r18=r18,16; /* compute ar.rsc to be used for "loadrs" */ \
126 st8 [r17]=r18,16; /* save ar.rsc value for "loadrs" */ \
170 .mem.offset 0,0; st8.spill [r2]=r18,16; \
175 mov r18=b6; \
207 st8 [r24]=r18,16; /* b6 */ \
215 (pUStk) extr.u r17=r18,3,6; \
216 (pUStk) sub r16=r18,r22; \
[all …]
Dhead.S238 mov r18=KERNEL_TR_PAGE_SHIFT<<2
241 mov cr.itir=r18
245 movl r18=PAGE_KERNEL
249 or r18=r2,r18
253 itr.i itr[r16]=r18
255 itr.d dtr[r16]=r18
323 dep r18=0,r3,0,12
325 or r18=r17,r18
338 itr.d dtr[r19]=r18
363 mov r18=PERCPU_PAGE_SIZE
[all …]
Dfsys.S106 add r18=IA64_TASK_CLEAR_CHILD_TID_OFFSET,r16
120 (p6) st8 [r18]=r32
121 (p7) st8 [r18]=r17
125 mov r18=0 // i must not leak kernel bits...
355 shladd r18=r3,1,r17
357 ld2 r20=[r18] // r20 = cpu_to_node_map[cpu]
396 shladd r18=r17,3,r14
398 ld8 r18=[r18] // load normal (heavy-weight) syscall entry-point
504 mov b6=r18 // I0 copy syscall entry-point to b6 (7 cyc)
507 mov r18=ar.bsp // M2 save (kernel) ar.bsp (12 cyc)
[all …]
Dentry.S283 mov.m r18=ar.fpsr // preserve fpsr
353 st8 [r14]=r18 // save fpsr
394 ld8 r18=[r14],16 // restore caller's unat
451 mov ar.unat=r18 // restore caller's unat
701 RSM_PSR_I(p0, r2, r18) // disable interrupts
711 RSM_PSR_I(pUStk, r2, r18)
720 adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
722 (p6) ld4 r31=[r18] // load current_thread_info()->flags
729 adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
731 (p6) ld4 r31=[r18] // load current_thread_info()->flags
[all …]
/arch/sh/lib64/
Dudivsi3.S19 ptabs r18,tr0
31 mulu.l r4,r21,r18
34 shlrd r18,r0,r18
35 mulu.l r18,r22,r20
45 add r18,r19,r18
55 add r18,r19,r18
58 add.l r18,r25,r0
Dsdivsi3.S25 ptabs r18, tr0
31 muls.l r25, r21, r18 /* s2.58 */
34 sub r19, r18, r18
35 shari r18, 28, r18 /* some 22 bit inverse in s1.30 */
36 muls.l r18, r25, r0 /* s2.60 */
37 muls.l r18, r4, r25 /* s32.30 */
40 muls.l r19, r18, r19 /* s-16.74 */
42 shari r4, 14, r18 /* s19.-14 */
44 muls.l r19, r18, r19 /* s15.30 */
Dstrlen.S13 ptabs r18, tr4
/arch/microblaze/lib/
Dumodsi3.S30 rsub r18, r5, r6
31 beqi r18, return_here
34 xor r18, r5, r6
35 bgeid r18, 16
39 rsub r18, r5, r6 /* microblazecmp */
40 bgti r18, return_here
46 addik r18, r0, 0x7fffffff
47 and r5, r5, r18
48 and r6, r6, r18
Dudivsi3.S30 rsub r18, r5, r6
31 beqid r18, return_here
35 xor r18, r5, r6
36 bgeid r18, 16
40 rsub r18, r6, r5 /* microblazecmp */
41 blti r18, return_here
/arch/ia64/hp/sim/boot/
Dboot_head.S119 add r18=8,r29 /* second index */
122 st8 [r18]=r0,16 /* clear remaining bits */
125 st8 [r18]=r0,16 /* clear remaining bits */
128 st8 [r18]=r0,16 /* clear remaining bits */
132 st8 [r18]=r0,16 /* clear remaining bits */
136 st8 [r18]=r0,16 /* clear remaining bits */
139 st8 [r18]=r0,16 /* clear remaining bits */
142 st8 [r18]=r0,16 /* clear remaining bits */
145 st8 [r18]=r0,16 /* clear remaining bits */
/arch/unicore32/lib/
Dcopy_page.S29 mov r18, r1
33 ldm.w (r0 - r15), [r18]+
/arch/ia64/lib/
Dxor.S76 mov r18 = in3
87 (p[0]) ld8.nta s3[0] = [r18], 8
117 mov r18 = in3
128 (p[0]) ld8.nta s3[0] = [r18], 8
161 mov r18 = in3
173 (p[0]) ld8.nta s3[0] = [r18], 8
/arch/microblaze/kernel/
Dentry-nommu.S86 swi r18, r1, PT_R18
178 lwi r18, r1, PT_R18
240 swi r18, r1, PT_R18
331 swi r18, r1, PT_R18
404 swi r18, r11, CC_R18
458 lwi r18, r11, CC_R18
527 lwi r18, r1, PT_MODE
528 swi r18, r0, PER_CPU(KM)
531 lwi r18, r1, PT_FSR
532 mts rfsr, r18
[all …]
/arch/powerpc/lib/
Dcopypage_power7.S120 std r18,STK_REG(R18)(r1)
137 ld r18,104(r4)
154 std r18,104(r3)
164 ld r18,STK_REG(R18)(r1)
/arch/sh/kernel/cpu/sh5/
Dentry.S266 st.q SP, SAVED_R18, r18
309 st.q SP, SAVED_R18, r18
318 gettr tr4, r18
323 st.q SP, TLB_SAVED_TR4 , r18
346 ld.q SP, TLB_SAVED_TR4, r18
352 ptabs r18, tr4
361 ld.q SP, SAVED_R18, r18
380 ld.q SP, TLB_SAVED_TR4, r18
389 ptabs/u r18, tr4
428 st.q SP, SAVED_R18, r18
[all …]
Dswitchto.S49 st.l r15, 0, r18 ! save link reg
126 ld.l r5, 4, r18 ! next->thread.pc
129 ptabs r18, tr0
189 ld.l r15, 0, r18
191 ptabs r18, tr0
/arch/alpha/include/uapi/asm/
Dptrace.h50 unsigned long r18; member
/arch/arc/include/asm/
Dunwind.h35 unsigned long r18; member
94 PTREGS_INFO(r18), \
/arch/arc/include/uapi/asm/
Dptrace.h45 unsigned long r19, r18, r17, r16, r15, r14, r13; member
/arch/powerpc/boot/
Dppc_asm.h47 #define r18 18 macro
/arch/hexagon/include/uapi/asm/
Duser.h31 unsigned long r18; member

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