| /arch/powerpc/kernel/ |
| D | fsl_booke_entry_mapping.S | 5 mfmsr r7
6 rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
7 mfspr r7, SPRN_PID0
8 slwi r7,r7,16
9 or r7,r7,r4
10 mtspr SPRN_MAS6,r7
12 mfspr r7,SPRN_MAS1
13 andis. r7,r7,MAS1_VALID@h
16 mfspr r7,SPRN_MMUCFG
17 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
[all …]
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| D | tm.S | 131 li r7, (MSR_TS_S)@higher
133 and r6, r6, r7
180 std r7, GPR7(r1) /* Temporary stash */
186 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
191 subi r7, r7, STACK_FRAME_OVERHEAD
194 SAVE_GPR(0, r7) /* user r0 */
195 SAVE_GPR(2, r7) /* user r2 */
196 SAVE_4GPRS(3, r7) /* user r3-r6 */
197 SAVE_GPR(8, r7) /* user r8 */
198 SAVE_GPR(9, r7) /* user r9 */
[all …]
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| D | idle_power4.S | 34 mfmsr r7
35 rldicl r0,r7,48,1
53 mfmsr r7
66 ori r7,r7,MSR_EE
67 oris r7,r7,MSR_POW@h
70 mtmsrd r7
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| D | misc_32.S | 91 mullw r7,r10,r5
92 addc r7,r0,r7
100 addc r7,r0,r7
113 lis r7,__got2_start@ha
114 addi r7,r7,__got2_start@l
117 subf r8,r7,r8
126 add r7,r0,r7
127 2: lwz r0,0(r7)
129 stw r0,0(r7)
130 addi r7,r7,4
[all …]
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| D | misc_64.S | 83 lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
84 addi r5,r7,-1
93 add r6,r6,r7
99 lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
100 addi r5,r7,-1
109 add r6,r6,r7
131 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
132 addi r5,r7,-1
141 add r6,r6,r7
159 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
[all …]
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| /arch/arm/boot/compressed/ |
| D | ll_char_wr.S | 36 stmfd sp!, {r4 - r7, lr}
38 @ Smashable regs: {r0 - r3}, [r4 - r7], (r8 - fp), [ip], (sp), [lr], (pc)
61 ldrb r7, [r6, r1]
65 @ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
68 ldr r7, [lr, r7, lsl #2]
69 mul r7, r2, r7
70 sub r1, r1, #1 @ avoid using r7 directly after
71 str r7, [r0, -r5]!
72 ldrb r7, [r6, r1]
73 ldr r7, [lr, r7, lsl #2]
[all …]
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| /arch/arm/mach-imx/ |
| D | suspend-imx6.S | 103 ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
104 add r7, r7, r0
106 ldr r8, [r7], #0x4
107 ldr r9, [r7], #0x4
120 ldr r7, =MX6Q_MMDC_MPDGCTRL0
121 ldr r6, [r11, r7]
123 str r6, [r11, r7]
125 ldr r6, [r11, r7]
130 ldr r6, [r11, r7]
132 str r6, [r11, r7]
[all …]
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| /arch/m32r/lib/ |
| D | memcpy.S | 23 mv r4, r0 || mv r7, r0
24 or r7, r1 || cmpz r2
28 and3 r7, r7, #3
29 bnez r7, byte_copy
35 ld r7, @r1+ || addi r3, #-1
36 st r7, @+r4 || cmpz r2
41 ldb r7, @r1 || addi r1, #1
42 addi r2, #-1 || stb r7, @r4+
46 ldb r7, @r1 || addi r1, #1
47 addi r2, #-1 || stb r7, @r4
[all …]
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| /arch/arm/mm/ |
| D | pv-fixup-asm.S | 33 add r7, r2, #0x1000
34 add r6, r7, r6, lsr #SECTION_SHIFT - L2_ORDER
35 add r7, r7, #PAGE_OFFSET >> (SECTION_SHIFT - L2_ORDER)
36 1: ldrd r4, [r7]
39 strd r4, [r7], #1 << L2_ORDER
40 cmp r7, r6
44 add r7, r2, #0x1000
45 add r7, r7, r3, lsr #SECTION_SHIFT - L2_ORDER
46 bic r7, r7, #(1 << L2_ORDER) - 1
47 ldrd r4, [r7]
[all …]
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| D | abort-lv4t.S | 32 and r7, r8, #15 << 24
33 add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
64 mov r7, #0x11
65 orr r7, r7, #0x1100
66 and r6, r8, r7
67 and r9, r8, r7, lsl #1
69 and r9, r8, r7, lsl #2
71 and r9, r8, r7, lsl #3
77 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
79 subne r7, r7, r6, lsl #2 @ Undo increment
[all …]
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| /arch/powerpc/crypto/ |
| D | aes-spe-keys.S | 36 xor r7,r7,r7; \
83 LOAD_KEY(r7,r4,8)
87 stw r7,8(r3)
99 xor r7,r7,r6
100 xor r8,r8,r7
103 stw r7,8(r3)
125 LOAD_KEY(r7,r4,8)
131 stw r7,8(r3)
145 xor r7,r7,r6
146 xor r8,r8,r7
[all …]
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| /arch/powerpc/platforms/52xx/ |
| D | mpc52xx_sleep.S | 12 mfmsr r7
13 ori r7, r7, 0x8000 /* EE */
14 mtmsr r7
125 mtspr SPRN_SPRG0, r7
129 mfspr r7, 311 /* MBAR */
130 addi r7, r7, 0x540 /* intr->main_emul */
132 stw r8, 0(r7)
134 dcbf 0, r7
137 mfspr r7, 311 /* MBAR */
138 addi r7, r7, 0x524 /* intr->enc_status */
[all …]
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| /arch/powerpc/platforms/83xx/ |
| D | suspend-asm.S | 74 mfspr r7, SPRN_HID2
78 stw r7, SS_HID+8(r3)
83 mfspr r7, SPRN_DABR
90 stw r7, SS_DABR+0(r3)
97 mfspr r7, SPRN_SPRG3
103 stw r7, SS_SPRG+12(r3)
109 mfspr r7, SPRN_DBAT1L
114 stw r7, SS_DBAT+0x0c(r3)
119 mfspr r7, SPRN_DBAT3L
124 stw r7, SS_DBAT+0x1c(r3)
[all …]
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| /arch/arc/lib/ |
| D | strchr-700.S | 25 asl r7,r2,3
28 asl r7,r3,r7
30 lsr r7,r3,r7
34 sub r12,r2,r7
40 sub r12,r6,r7
43 and r7,r12,r4
44 breq r7,0,.Loop ; For speed, we want this branch to be unaligned.
50 bic r2,r7,r6
69 and r7,r12,r4
70 breq r7,0,.Loop /* ... so that this branch is unaligned. */
[all …]
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| /arch/blackfin/mach-common/ |
| D | entry.S | 52 GET_PDA(p5, r7);
53 r7 = [p5 + PDA_LFRETX]; define
56 cc = r6 == r7;
97 DEBUG_HWTRACE_SAVE(p5, r7)
107 r7 = SEQSTAT; /* reason code is in bit 5:0 */ define
110 r7 = r7 & r6; define
116 DEBUG_HWTRACE_RESTORE(p5, r7)
131 r7 = retx; define
133 cc = r7 == r6;
149 r7 = 10; define
[all …]
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| /arch/powerpc/kvm/ |
| D | book3s_interrupts.S | 184 PPC_LL r7, GPR4(r1)
186 PPC_STL r14, VCPU_GPR(R14)(r7)
187 PPC_STL r15, VCPU_GPR(R15)(r7)
188 PPC_STL r16, VCPU_GPR(R16)(r7)
189 PPC_STL r17, VCPU_GPR(R17)(r7)
190 PPC_STL r18, VCPU_GPR(R18)(r7)
191 PPC_STL r19, VCPU_GPR(R19)(r7)
192 PPC_STL r20, VCPU_GPR(R20)(r7)
193 PPC_STL r21, VCPU_GPR(R21)(r7)
194 PPC_STL r22, VCPU_GPR(R22)(r7)
[all …]
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| /arch/powerpc/lib/ |
| D | memcpy_64.S | 60 srdi r7,r5,4
63 mtctr r7
99 srdi r7,r5,4
103 mtctr r7
113 srd r7,r0,r11
115 or r7,r7,r6
118 # s1<< in r8, d0=(s0<<|s1>>) in r7, s3 in r0, s2 in r9, nix in r6 & r12
131 srd r7,r0,r11
136 # d0=(s0<<|s1>>) in r12, s1<< in r6, s2>> in r7, s2<< in r8, s3 in r9
137 1: or r7,r7,r6
[all …]
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| D | copy_32.S | 18 lwz r7,4(r4); \
22 stw r7,4(r6); \
29 lwz r7,4(r4); \
37 stw r7,4(r6); \
100 clrlwi r7,r6,32-LG_CACHELINE_BYTES
101 add r8,r7,r5
105 xori r0,r7,CACHELINE_MASK & ~3
112 li r7,4
113 10: dcbz r7,r6
151 add r7,r3,r5 /* test if the src & dst overlap */
[all …]
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| /arch/powerpc/platforms/44x/ |
| D | misc_44x.S | 21 mfmsr r7
22 ori r0,r7,MSR_DS
29 mtmsr r7
35 mfmsr r7
36 ori r0,r7,MSR_DS
43 mtmsr r7
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| /arch/powerpc/boot/ |
| D | div64.S | 23 li r7,0
26 divwu r7,r5,r4 # if dividend.hi >= divisor,
27 mullw r0,r7,r4 # quotient.hi = dividend.hi / divisor
56 4: stw r7,0(r3) # return the quotient in *r3
79 addi r7,r5,32 # could be xori, or addi with -32
81 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
82 sraw r7,r3,r7 # t2 = MSW >> (count-32)
84 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
86 or r4,r4,r7 # LSW |= t2
93 addi r7,r5,32 # could be xori, or addi with -32
[all …]
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| D | string.S | 131 rlwinm. r7,r5,32-3,3,31 /* r7 = r5 >> 3 */
136 mtctr r7
140 1: lwz r7,4(r4)
142 stw r7,4(r6)
162 add r7,r0,r4
163 andi. r7,r7,3 /* will source be word-aligned too? */
167 6: lbz r7,4(r4)
169 stb r7,4(r6)
173 rlwinm. r7,r5,32-3,3,31
175 mtctr r7
[all …]
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| /arch/microblaze/lib/ |
| D | uaccess_old.S | 37 beqid r7,3f
38 addik r3,r7,0 /* temp_count = len */
50 rsubk r3,r3,r7 /* temp_count = len - temp_count */
165 beqid r7, 0f /* zero size is not likely */
167 or r3, r3, r7 /* find if count is unaligned */
172 rsubi r3, r7, PAGE_SIZE /* detect PAGE_SIZE */
178 addik r7, r7, -4
179 bneid r7, w1
181 addik r3, r7, 0
195 swi r7, r1, 8
[all …]
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| /arch/nios2/kernel/ |
| D | insnemu.S | 39 ldw r7, PT_R7(sp)
134 stw r7, 28(sp)
199 movi r7, 0x24 /* muli opcode (I-type instruction format) */
200 beq r2, r7, mul_immed /* muli doesn't use the B register as a source */
222 andi r7, r4, 0x02 /* For R-type multiply instructions,
224 bne r7, zero, multiply
273 xori r7, r4, 0x25 /* OPX of div */
274 bne r7, zero, unsigned_division
316 cmplt r7, r3, zero /* r7 = MSB of r3 */
317 or r13, r13, r7
[all …]
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| /arch/score/lib/ |
| D | string.S | 35 0: lbu r7, [r5]
37 1: sb r7, [r4]
48 5: lb r7, [r5]
49 cmpi.c r7, 0
78 ldi r7, 0
79 cmp.c r6, r7
82 addi r7, 1
83 cmp.c r7, r5
89 addri r4, r7, 1
109 mv r7, r4
[all …]
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| /arch/arm/common/ |
| D | fiq_glue.S | 40 stmfd sp!, {r0-r7}
47 mov r7, sp
54 mov r7, sp
57 str sp, [r7, #(4 * 13)]
58 str lr, [r7, #(4 * 14)]
60 str r5, [r7, #(4 * 17)]
64 subne sp, r7, #(4 * 3)
69 sub sp, r7, #12
81 ldr sp, [r7, #(4 * 13)]
82 ldr lr, [r7, #(4 * 14)]
[all …]
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