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/arch/arm/include/debug/
Dsamsung.S16 .macro fifo_level_s5pv210 rd, rx
17 ldr \rd, [\rx, # S3C2410_UFSTAT]
18 ARM_BE8(rev \rd, \rd)
19 and \rd, \rd, #S5PV210_UFSTAT_TXMASK
22 .macro fifo_full_s5pv210 rd, rx
23 ldr \rd, [\rx, # S3C2410_UFSTAT]
24 ARM_BE8(rev \rd, \rd)
25 tst \rd, #S5PV210_UFSTAT_TXFULL
31 .macro fifo_level_s3c2440 rd, rx
32 ldr \rd, [\rx, # S3C2410_UFSTAT]
[all …]
D8250.S18 .macro store, rd, rx:vararg
19 ARM_BE8(rev \rd, \rd)
20 str \rd, \rx
21 ARM_BE8(rev \rd, \rd)
24 .macro load, rd, rx:vararg
25 ldr \rd, \rx
26 ARM_BE8(rev \rd, \rd)
29 .macro store, rd, rx:vararg
30 strb \rd, \rx
33 .macro load, rd, rx:vararg
[all …]
Dmsm.S23 .macro senduart, rd, rx
24 ARM_BE8(rev \rd, \rd )
26 str \rd, [\rx, #0x70]
29 .macro waituart, rd, rx
31 ldr \rd, [\rx, #0x08]
32 ARM_BE8(rev \rd, \rd )
33 tst \rd, #0x08
36 1001: ldr \rd, [\rx, #0x14]
37 ARM_BE8(rev \rd, \rd )
38 tst \rd, #0x80
[all …]
Dicedcc.S19 .macro senduart, rd, rx
20 mcr p14, 0, \rd, c0, c5, 0
23 .macro busyuart, rd, rx
30 .macro waituart, rd, rx
31 mov \rd, #0x2000000
33 subs \rd, \rd, #1
43 .macro senduart, rd, rx
44 mcr p14, 0, \rd, c8, c0, 0
47 .macro busyuart, rd, rx
54 .macro waituart, rd, rx
[all …]
Dpl01x.S29 .macro senduart,rd,rx
30 strb \rd, [\rx, #UART01x_DR]
33 .macro waituart,rd,rx
34 1001: ldr \rd, [\rx, #UART01x_FR]
35 ARM_BE8( rev \rd, \rd )
36 tst \rd, #UART01x_FR_TXFF
40 .macro busyuart,rd,rx
41 1001: ldr \rd, [\rx, #UART01x_FR]
42 ARM_BE8( rev \rd, \rd )
43 tst \rd, #UART01x_FR_BUSY
Drenesas-scif.S35 .macro waituart, rd, rx
36 1001: ldrh \rd, [\rx, #FSR]
37 tst \rd, #TDFE
41 .macro senduart, rd, rx
42 strb \rd, [\rx, #FTDR]
43 ldrh \rd, [\rx, #FSR]
44 bic \rd, \rd, #TEND
45 strh \rd, [\rx, #FSR]
48 .macro busyuart, rd, rx
49 1001: ldrh \rd, [\rx, #FSR]
[all …]
Dzynq.S40 .macro senduart,rd,rx
41 strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
44 .macro waituart,rd,rx
45 1001: ldr \rd, [\rx, #UART_SR_OFFSET]
46 ARM_BE8( rev \rd, \rd )
47 tst \rd, #UART_SR_TXEMPTY
51 .macro busyuart,rd,rx
52 1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
53 ARM_BE8( rev \rd, \rd )
54 tst \rd, #UART_SR_TXFULL @
Dimx.S37 .macro senduart,rd,rx
38 ARM_BE8(rev \rd, \rd)
39 str \rd, [\rx, #0x40] @ TXDATA
42 .macro waituart,rd,rx
45 .macro busyuart,rd,rx
46 1002: ldr \rd, [\rx, #0x98] @ SR2
47 ARM_BE8(rev \rd, \rd)
48 tst \rd, #1 << 3 @ TXDC
Dbcm63xx.S18 .macro senduart, rd, rx
20 strb \rd, [\rx, #UART_FIFO_REG]
23 .macro waituart, rd, rx
24 1001: ldr \rd, [\rx, #UART_IR_REG]
25 tst \rd, #(1 << UART_IR_TXEMPTY)
29 .macro busyuart, rd, rx
30 1002: ldr \rd, [\rx, #UART_IR_REG]
31 tst \rd, #(1 << UART_IR_TXTRESH)
Dnetx.S22 .macro senduart,rd,rx
23 str \rd, [\rx, #UART_DATA]
26 .macro busyuart,rd,rx
27 1002: ldr \rd, [\rx, #UART_FLAG]
28 tst \rd, #UART_FLAG_BUSY
32 .macro waituart,rd,rx
33 1001: ldr \rd, [\rx, #UART_FLAG]
34 tst \rd, #UART_FLAG_BUSY
Dmeson.S21 .macro senduart,rd,rx
22 str \rd, [\rx, #MESON_AO_UART_WFIFO]
25 .macro busyuart,rd,rx
26 1002: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
27 tst \rd, #MESON_AO_UART_TX_FIFO_EMPTY
31 .macro waituart,rd,rx
32 1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
33 tst \rd, #MESON_AO_UART_TX_FIFO_FULL
Defm32.S31 .macro senduart,rd,rx
32 strb \rd, [\rx, #UARTn_TXDATA]
35 .macro waituart,rd,rx
36 1001: ldr \rd, [\rx, #UARTn_STATUS]
37 tst \rd, #UARTn_STATUS_TXBL
41 .macro busyuart,rd,rx
42 1001: ldr \rd, [\rx, UARTn_STATUS]
43 tst \rd, #UARTn_STATUS_TXC
Ds3c24xx.S24 .macro fifo_full_s3c2410 rd, rx
25 ldr \rd, [\rx, # S3C2410_UFSTAT]
26 tst \rd, #S3C2410_UFSTAT_TXFULL
29 .macro fifo_level_s3c2410 rd, rx
30 ldr \rd, [\rx, # S3C2410_UFSTAT]
31 and \rd, \rd, #S3C2410_UFSTAT_TXMASK
Dvt8500.S24 .macro senduart,rd,rx
25 strb \rd, [\rx, #0]
28 .macro busyuart,rd,rx
29 1001: ldr \rd, [\rx, #0x1c]
30 ands \rd, \rd, #0x2
34 .macro waituart,rd,rx
Dks8695.S26 .macro senduart, rd, rx
27 str \rd, [\rx, #KS8695_URTH] @ Write to Transmit Holding Register
30 .macro busyuart, rd, rx
31 1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register
32 tst \rd, #URLS_URTE @ Holding & Shift registers empty?
36 .macro waituart, rd, rx
37 1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register
38 tst \rd, #URLS_URTHRE @ Holding Register empty?
Dsti.S47 .macro senduart,rd,rx
48 strb \rd, [\rx, #ASC_TX_BUF_OFF]
51 .macro waituart,rd,rx
52 1001: ldr \rd, [\rx, #ASC_STA_OFF]
53 tst \rd, #ASC_STA_TX_FULL
57 .macro busyuart,rd,rx
58 1001: ldr \rd, [\rx, #ASC_STA_OFF]
59 tst \rd, #ASC_STA_TX_EMPTY
Dat91.S22 .macro senduart,rd,rx
23 strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
26 .macro waituart,rd,rx
27 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
28 tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
32 .macro busyuart,rd,rx
33 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
34 tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
Ddigicolor.S24 .macro senduart,rd,rx
25 strb \rd, [\rx, #UA0_EMI_REC]
28 .macro waituart,rd,rx
31 .macro busyuart,rd,rx
32 1001: ldrb \rd, [\rx, #UA0_STATUS]
33 tst \rd, #UA0_STATUS_TX_READY
Dasm9260.S18 .macro waituart,rd,rx
21 .macro senduart,rd,rx
22 str \rd, [\rx, #0x50] @ TXDATA
25 .macro busyuart,rd,rx
26 1002: ldr \rd, [\rx, #0x60] @ STAT
27 tst \rd, #1 << 27 @ TXEMPTY
/arch/arm/net/
Dbpf_jit_32.h135 #define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm)) argument
137 #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm)) argument
139 #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) argument
140 #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) argument
142 #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm) argument
143 #define ARM_AND_I(rd, rn, imm) _AL3_I(ARM_INST_AND, rd, rn, imm) argument
145 #define ARM_BIC_R(rd, rn, rm) _AL3_R(ARM_INST_BIC, rd, rn, rm) argument
146 #define ARM_BIC_I(rd, rn, imm) _AL3_I(ARM_INST_BIC, rd, rn, imm) argument
155 #define ARM_EOR_R(rd, rn, rm) _AL3_R(ARM_INST_EOR, rd, rn, rm) argument
156 #define ARM_EOR_I(rd, rn, imm) _AL3_I(ARM_INST_EOR, rd, rn, imm) argument
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/arch/sparc/include/asm/
Dhead_32.h12 rd %psr, %l0; b label; rd %wim, %l3; nop;
15 #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
16 #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
20 rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
37 rd %psr, %l0;
41 rd %psr,%l0; \
49 rd %psr,%l0; \
58 b getcc_trap_handler; rd %psr, %l0; nop; nop;
62 b setcc_trap_handler; rd %psr, %l0; nop; nop;
66 rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;
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/arch/arm/mach-tegra/
Dsleep.h62 .macro cpu_to_halt_reg rd, rcpu
64 subne \rd, \rcpu, #1
65 movne \rd, \rd, lsl #3
66 addne \rd, \rd, #0x14
67 moveq \rd, #0
71 .macro cpu_to_csr_reg rd, rcpu
73 subne \rd, \rcpu, #1
74 movne \rd, \rd, lsl #3
75 addne \rd, \rd, #0x18
76 moveq \rd, #8
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/arch/unicore32/mm/
Dproc-macros.S41 .macro vma_vm_mm, rd, rn
42 ldw \rd, [\rn+], #VMA_VM_MM
48 .macro vma_vm_flags, rd, rn
49 ldw \rd, [\rn+], #VMA_VM_FLAGS
52 .macro tsk_mm, rd, rn
53 ldw \rd, [\rn+], #TI_TASK
54 ldw \rd, [\rd+], #TSK_ACTIVE_MM
60 .macro act_mm, rd argument
61 andn \rd, sp, #8128
62 andn \rd, \rd, #63
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/arch/unicore32/kernel/
Ddebug-macro.S17 .macro put_word_ocd, rd, rx=r16
21 movc p1.c1, \rd, #1
29 .macro senduart, rd, rx
30 put_word_ocd \rd, \rx
33 .macro busyuart, rd, rx
36 .macro waituart, rd, rx
73 .macro senduart,rd,rx
74 str \rd, [\rx, #UART_THR_OFFSET]
77 .macro waituart,rd,rx
78 1001: ldr \rd, [\rx, #UART_LSR_OFFSET]
[all …]
/arch/arm/lib/
Dio-writesb.S13 .macro outword, rd argument
15 strb \rd, [r0]
16 mov \rd, \rd, lsr #8
17 strb \rd, [r0]
18 mov \rd, \rd, lsr #8
19 strb \rd, [r0]
20 mov \rd, \rd, lsr #8
21 strb \rd, [r0]
23 mov lr, \rd, lsr #24
25 mov lr, \rd, lsr #16
[all …]

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