Home
last modified time | relevance | path

Searched refs:rt_sysc_r32 (Results 1 – 10 of 10) sorted by relevance

/arch/mips/include/asm/mach-ralink/
Dralink_regs.h41 static inline u32 rt_sysc_r32(unsigned reg) in rt_sysc_r32() function
48 u32 val = rt_sysc_r32(reg) & ~clr; in rt_sysc_m32()
Dmt7620.h132 return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK; in mt7620_get_eco()
/arch/mips/ralink/
Dmt7621.c129 if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0) in ralink_clk_init()
134 clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); in ralink_clk_init()
141 fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1; in ralink_clk_init()
142 syscfg = rt_sysc_r32(SYSC_REG_SYSCFG); in ralink_clk_init()
Dreset.c35 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); in ralink_assert_device()
50 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); in ralink_deassert_device()
Dmt7620.c384 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); in mt7620_get_xtal_rate()
396 reg = rt_sysc_r32(SYSC_REG_CLKCFG0); in mt7620_get_periph_rate()
412 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); in mt7620_get_cpu_pll_rate()
438 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); in mt7620_get_pll_rate()
455 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); in mt7620_get_cpu_rate()
488 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); in mt7620_get_sys_rate()
571 u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); in ralink_clk_init()
Drt305x.c131 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); in ralink_clk_init()
184 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0); in ralink_clk_init()
Drt288x.c46 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); in ralink_clk_init()
Drt3883.c73 syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0); in ralink_clk_init()
/arch/mips/pci/
Dpci-rt3883.c316 rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); in rt3883_pci_preinit()
317 syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); in rt3883_pci_preinit()
318 clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); in rt3883_pci_preinit()
329 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()
333 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); in rt3883_pci_preinit()
337 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); in rt3883_pci_preinit()
341 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()
391 t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); in rt3883_pci_preinit()
398 t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); in rt3883_pci_preinit()
402 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()
Dpci-mt7620.c246 if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) { in mt7620_pci_hw_init()