Home
last modified time | relevance | path

Searched refs:u16 (Results 1 – 25 of 670) sorted by relevance

12345678910>>...27

/arch/x86/kvm/
Dtss.h30 u16 t;
31 u16 io_map;
35 u16 prev_task_link;
36 u16 sp0;
37 u16 ss0;
38 u16 sp1;
39 u16 ss1;
40 u16 sp2;
41 u16 ss2;
42 u16 ip;
[all …]
/arch/mn10300/unit-asb2364/include/unit/
Dfpga-regs.h11 #define ASB2364_FPGA_REG_RESET_LAN __SYSREG(0xa9001300, u16)
12 #define ASB2364_FPGA_REG_RESET_UART __SYSREG(0xa9001304, u16)
13 #define ASB2364_FPGA_REG_RESET_I2C __SYSREG(0xa9001308, u16)
14 #define ASB2364_FPGA_REG_RESET_USB __SYSREG(0xa900130c, u16)
15 #define ASB2364_FPGA_REG_RESET_AV __SYSREG(0xa9001310, u16)
17 #define ASB2364_FPGA_REG_IRQ(X) __SYSREG(0xa9001510+((X)*4), u16)
24 #define ASB2364_FPGA_REG_MASK(X) __SYSREG(0xa9001590+((X)*4), u16)
31 #define ASB2364_FPGA_REG_CPLD5_SET1 __SYSREG(0xa9002500, u16)
32 #define ASB2364_FPGA_REG_CPLD5_SET2 __SYSREG(0xa9002504, u16)
33 #define ASB2364_FPGA_REG_CPLD6_SET1 __SYSREG(0xa9002600, u16)
[all …]
/arch/s390/kernel/
Dcompat_linux.h90 long compat_sys_s390_chown16(const char __user *filename, u16 user, u16 group);
91 long compat_sys_s390_lchown16(const char __user *filename, u16 user, u16 group);
92 long compat_sys_s390_fchown16(unsigned int fd, u16 user, u16 group);
93 long compat_sys_s390_setregid16(u16 rgid, u16 egid);
94 long compat_sys_s390_setgid16(u16 gid);
95 long compat_sys_s390_setreuid16(u16 ruid, u16 euid);
96 long compat_sys_s390_setuid16(u16 uid);
97 long compat_sys_s390_setresuid16(u16 ruid, u16 euid, u16 suid);
98 long compat_sys_s390_getresuid16(u16 __user *ruid, u16 __user *euid, u16 __user *suid);
99 long compat_sys_s390_setresgid16(u16 rgid, u16 egid, u16 sgid);
[all …]
/arch/powerpc/include/asm/
Dmpc52xx_psc.h159 u16 status;
160 u16 clock_select;
164 u16 reserved1;
169 u16 buffer_16;
183 u16 isr;
184 u16 imr;
188 u16 reserved4;
221 u16 rfnum; /* PSC + 0x58 */
222 u16 reserved18;
223 u16 tfnum; /* PSC + 0x5c */
[all …]
Dimmap_cpm2.h21 u16 sc_swsr;
46 u16 sc_ceer;
47 u16 sc_cemr;
101 u16 memc_mptpr;
128 u16 sit_tmcntsc;
134 u16 sit_piscr;
142 #define PISCR_PIRQ_MASK ((u16)0xff00)
143 #define PISCR_PS ((u16)0x0080)
144 #define PISCR_PIE ((u16)0x0004)
145 #define PISCR_PTF ((u16)0x0002)
[all …]
Dps3av.h357 u16 version;
358 u16 size; /* size of command packet */
363 u16 version;
364 u16 size;
387 u16 num_of_hdmi; /* out: number of hdmi */
388 u16 num_of_avmulti; /* out: number of avmulti */
389 u16 num_of_spdif; /* out: number of hdmi */
390 u16 reserved;
407 u16 red_x;
408 u16 red_y;
[all …]
/arch/x86/boot/
Dboot.h43 static inline void outb(u8 v, u16 port) in outb()
47 static inline u8 inb(u16 port) in inb()
54 static inline void outw(u16 v, u16 port) in outw()
58 static inline u16 inw(u16 port) in inw()
60 u16 v; in inw()
65 static inline void outl(u32 v, u16 port) in outl()
69 static inline u32 inl(u16 port) in inl()
78 const u16 DELAY_PORT = 0x80; in io_delay()
84 static inline u16 ds(void) in ds()
86 u16 seg; in ds()
[all …]
Dvesa.h17 u16 off, seg;
23 u16 version; /* 4 */
27 u16 total_memory; /* 18 */
35 u16 mode_attr; /* 0 */
37 u16 win_grain; /* 4 */
38 u16 win_size; /* 6 */
39 u16 win_seg[2]; /* 8 */
41 u16 logical_scan; /* 16 */
43 u16 h_res; /* 18 */
44 u16 v_res; /* 20 */
[all …]
Dvideo.h67 u16 mode; /* Mode number (vga= style) */
68 u16 x, y; /* Width, height */
69 u16 depth; /* Bits per pixel, 0 for text mode */
79 u16 xmode_first; /* Unprobed modes to try to call anyway */
80 u16 xmode_n; /* Size of unprobed mode range */
86 int mode_defined(u16 mode); /* video.c */
99 static inline u8 in_idx(u16 port, u8 index) in in_idx()
105 static inline void out_idx(u8 v, u16 port, u8 index) in out_idx()
111 static inline u8 tst_idx(u8 v, u16 port, u8 index) in tst_idx()
118 u16 vga_crtc(void); /* video-vga.c */
/arch/arm/mach-omap2/
Dcm33xx.c51 static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx) in am33xx_cm_read_reg()
57 static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx) in am33xx_cm_write_reg()
83 static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs) in _clkctrl_idlest()
99 static bool _is_module_ready(u16 inst, u16 clkctrl_offs) in _is_module_ready()
118 static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs) in _clktrctrl_write()
138 static bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs) in am33xx_cm_is_clkdm_in_hwsup()
157 static void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs) in am33xx_cm_clkdm_enable_hwsup()
171 static void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs) in am33xx_cm_clkdm_disable_hwsup()
184 static void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs) in am33xx_cm_clkdm_force_sleep()
197 static void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs) in am33xx_cm_clkdm_force_wakeup()
[all …]
Dcm.h55 int (*wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
57 int (*wait_module_idle)(u8 part, s16 prcm_mod, u16 idlest_reg,
59 void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
60 void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);
65 int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg,
67 int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg,
69 int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
70 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
Dprm.h20 extern u16 prm_features;
143 bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
144 void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
146 int (*assert_hardreset)(u8 shift, u8 part, s16 prm_mod, u16 offset);
148 u16 offset, u16 st_offset);
150 u16 offset);
160 int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset);
162 u16 offset, u16 st_offset);
163 int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
165 extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
[all …]
Dcminst44xx.c76 static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
87 static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs) in _clkctrl_idlest()
104 static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs) in _is_module_ready()
115 static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) in omap4_cminst_read_inst_reg()
124 static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) in omap4_cminst_write_inst_reg()
133 static u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst, in omap4_cminst_rmw_inst_reg_bits()
146 static u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) in omap4_cminst_set_inst_reg_bits()
151 static u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, in omap4_cminst_clear_inst_reg_bits()
157 static u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) in omap4_cminst_read_inst_reg_bits()
182 static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs) in _clktrctrl_write()
[all …]
/arch/m68k/include/asm/
Draw_io.h35 ({ u16 __v = (*(__force volatile u16 *) (addr)); __v; })
39 ({ u16 __v = le16_to_cpu(*(__force volatile __le16 *) (addr)); __v; })
44 #define out_be16(addr,w) (void)((*(__force volatile u16 *) (addr)) = (w))
89 ({ u16 __v = (*(__force volatile u16 *) (addr)); __v >>= 8; __v; })
91 ({ u16 __v = (*(__force volatile u16 *) (addr)); __v; })
93 ({ u16 __v = le16_to_cpu(*(__force volatile u16 *) (addr)); __v; })
99 ({u16 __w, __v = (w); u32 _addr = ((u32) (addr)); \
100 __w = ((*(__force volatile u16 *) ((_addr & 0xFFFF0000UL) + ((__v & 0xFF)<<1)))); \
101 __w = ((*(__force volatile u16 *) ((_addr | 0x10000) + ((__v >> 8)<<1)))); })
103 ({u16 __w, __v = (w); u32 _addr = ((u32) (addr)); \
[all …]
/arch/x86/include/asm/
Dintel_scu_ipc.h19 int intel_scu_ipc_ioread8(u16 addr, u8 *data);
22 int intel_scu_ipc_ioread16(u16 addr, u16 *data);
25 int intel_scu_ipc_ioread32(u16 addr, u32 *data);
28 int intel_scu_ipc_readv(u16 *addr, u8 *data, int len);
31 int intel_scu_ipc_iowrite8(u16 addr, u8 data);
34 int intel_scu_ipc_iowrite16(u16 addr, u16 data);
37 int intel_scu_ipc_iowrite32(u16 addr, u32 data);
40 int intel_scu_ipc_writev(u16 *addr, u8 *data, int len);
43 int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask);
Dolpc.h66 extern void olpc_ec_wakeup_set(u16 value);
67 extern void olpc_ec_wakeup_clear(u16 value);
70 extern int olpc_ec_mask_write(u16 bits);
71 extern int olpc_ec_sci_query(u16 *sci_value);
85 static inline void olpc_ec_wakeup_set(u16 value) { } in olpc_ec_wakeup_set()
86 static inline void olpc_ec_wakeup_clear(u16 value) { } in olpc_ec_wakeup_clear()
97 extern void olpc_xo1_pm_wakeup_set(u16 value);
98 extern void olpc_xo1_pm_wakeup_clear(u16 value);
/arch/arm/plat-omap/
Ddebug-leds.c30 u16 smc91x[8];
32 u16 fpga_rev;
33 u16 board_rev;
34 u16 gpio_outputs;
35 u16 leds;
37 u16 misc_inputs;
38 u16 lan_status;
39 u16 lan_reset;
40 u16 reserved0;
42 u16 ps2_data;
[all …]
/arch/mips/include/asm/mach-ath25/
Dath25_platform.h15 u16 cksum; /* checksum (starting with BD_REV 2) */
16 u16 rev; /* revision of this struct */
19 u16 major; /* Board major number */
20 u16 minor; /* Board minor number */
40 u16 reset_config_gpio; /* Reset factory GPIO pin */
41 u16 sys_led_gpio; /* System LED GPIO pin */
51 u16 pci_id; /* Pseudo PCIID for common code */
52 u16 mem_cap; /* cap bank1 in MB */
64 u16 devid;
/arch/alpha/include/asm/
Dvga.h16 static inline void scr_writew(u16 val, volatile u16 *addr) in scr_writew()
19 __raw_writew(val, (volatile u16 __iomem *) addr); in scr_writew()
24 static inline u16 scr_readw(volatile const u16 *addr) in scr_readw()
27 return __raw_readw((volatile const u16 __iomem *) addr); in scr_readw()
32 static inline void scr_memsetw(u16 *s, u16 c, unsigned int count) in scr_memsetw()
35 memsetw_io((u16 __iomem *) s, c, count); in scr_memsetw()
41 extern void scr_memcpyw(u16 *d, const u16 *s, unsigned int count);
/arch/sparc/include/asm/
Dvio.h27 u16 stype_env;
48 u16 major;
49 u16 minor;
65 u16 options;
69 u16 resv;
98 u16 __pad2;
113 u16 __pad1;
156 u16 resv1;
171 u16 sector_size;
172 u16 num_partitions;
[all …]
/arch/powerpc/boot/
Dcpm-serial.c19 u16 psmr;
21 u16 todr;
22 u16 dsr;
23 u16 scce;
25 u16 sccm;
33 u16 smcmr;
42 u16 rbase;
43 u16 tbase;
46 u16 mrblr;
49 u16 rbptr;
[all …]
/arch/mn10300/include/asm/
Dtimer-regs.h87 #define TM01MD __SYSREG(0xd4003000, u16) /* timer 0:1 mode register */
93 #define TM01BR __SYSREG(0xd4003010, u16) /* timer 0:1 base register */
99 #define TM01BC __SYSREGC(0xd4003020, u16) /* timer 0:1 binary counter */
279 #define TM4BR __SYSREG(0xd4003090, u16) /* timer 4 base register */
280 #define TM5BR __SYSREG(0xd4003092, u16) /* timer 5 base register */
282 #define TM7BR __SYSREG(0xd4003096, u16) /* timer 7 base register */
283 #define TM8BR __SYSREG(0xd4003098, u16) /* timer 8 base register */
284 #define TM9BR __SYSREG(0xd400309a, u16) /* timer 9 base register */
286 #define TM10BR __SYSREG(0xd400309c, u16) /* timer 10 base register */
287 #define TM11BR __SYSREG(0xd400309e, u16) /* timer 11 base register */
[all …]
/arch/s390/include/asm/
Dpci_clp.h16 u16 device_id;
17 u16 vendor_id;
61 u16 max_fn;
78 u16 vfn; /* virtual fn number */
79 u16 : 7;
80 u16 util_str_avail : 1; /* utility string available? */
81 u16 pfgid : 8; /* pci function group id */
84 u16 pchid;
108 u16 : 4;
109 u16 noi : 12; /* number of interrupts */
[all …]
/arch/blackfin/include/asm/
Dbfin_twi.h15 static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
17 static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
36 static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface) in DEFINE_TWI_REG()
38 u16 ret; in DEFINE_TWI_REG()
48 static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
50 u16 ret;
61 static inline u16 read_FIFO_CTL(struct bfin_twi_iface *iface)
66 static inline void write_FIFO_CTL(struct bfin_twi_iface *iface, u16 v) in write_FIFO_CTL()
72 static inline u16 read_CONTROL(struct bfin_twi_iface *iface) in read_CONTROL()
77 static inline void write_CONTROL(struct bfin_twi_iface *iface, u16 v) in write_CONTROL()
/arch/tile/include/asm/
Dvga.h24 static inline void scr_writew(u16 val, volatile u16 *addr) in scr_writew()
26 __raw_writew(val, (volatile u16 __iomem *) addr); in scr_writew()
29 static inline u16 scr_readw(volatile const u16 *addr) in scr_readw()
31 return __raw_readw((volatile const u16 __iomem *) addr); in scr_readw()

12345678910>>...27