Home
last modified time | relevance | path

Searched refs:x20 (Results 1 – 25 of 293) sorted by relevance

12345678910>>...12

/arch/arm64/crypto/
Dsha512-core.S68 stp x19,x20,[sp,#16]
75 ldp x20,x21,[x0] // load context
98 eor x19,x20,x21 // a^b, b^c in next round
100 ror x6,x20,#28
102 eor x17,x20,x20,ror#5
123 eor x28,x27,x20 // a^b, b^c in next round
131 eor x19,x19,x20 // Maj(a,b,c)
179 add x20,x20,x24 // d+=h
189 ror x16,x20,#14
191 eor x10,x20,x20,ror#23
[all …]
/arch/arm/boot/dts/
Daxm55xx.dtsi55 reg = <0x20 0x10020000 0 0x20000>;
64 reg = <0x20 0x01001000 0 0x1000>,
65 <0x20 0x01002000 0 0x1000>,
66 <0x20 0x01004000 0 0x2000>,
67 <0x20 0x01006000 0 0x2000>;
101 reg = <0x20 0x10030000 0 0x2000>;
117 reg = <0x20 0x10080000 0 0x1000>;
126 reg = <0x20 0x10081000 0 0x1000>;
135 reg = <0x20 0x10082000 0 0x1000>;
144 reg = <0x20 0x10083000 0 0x1000>;
[all …]
Demev2.dtsi206 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
218 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
230 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
242 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
254 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
Dmeson.dtsi120 reg = <0xc8100500 0x20>;
130 reg = <0xc1108500 0x20>;
140 reg = <0xc11087c0 0x20>;
150 reg = <0xc8100480 0x20>;
Dbcm63138.dtsi107 reg = <0x1e200 0x20>;
114 reg = <0x1e600 0x20>;
121 reg = <0x1e620 0x20>;
Darm-realview-pb11mp.dts124 reg = <0x1f000600 0x20>;
131 reg = <0x1f000620 0x20>;
299 mask = <0x20>;
322 lock-offset = <0x20>;
329 lock-offset = <0x20>;
336 lock-offset = <0x20>;
343 lock-offset = <0x20>;
350 lock-offset = <0x20>;
357 lock-offset = <0x20>;
364 lock-offset = <0x20>;
/arch/arm64/kernel/
Drelocate_kernel.S64 add x20, x0, #PAGE_SIZE
69 cmp x0, x20
73 mov x20, x13
75 copy_page x20, x21, x0, x1, x2, x3, x4, x5, x6, x7
Defi-entry.S63 mov x20, x0 // DTB address
113 mov x0, x20
Dentry.S114 stp x20, x21, [sp, #16 * 10]
122 ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear,
124 disable_step_tsk x19, x20 // exceptions when scheduling.
131 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
132 str x20, [sp, #S_ORIG_ADDR_LIMIT]
133 mov x20, #USER_DS
134 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
195 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
196 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
268 ldp x20, x21, [sp, #16 * 10]
[all …]
/arch/powerpc/boot/dts/fsl/
Dqoriq-sec4.0-0.dtsi77 reg = <0x00 0x20 0x100 0x80>;
82 reg = <0x20 0x20 0x200 0x80>;
87 reg = <0x40 0x20 0x300 0x80>;
92 reg = <0x60 0x20 0x500 0x80>;
Dqoriq-sec4.2-0.dtsi83 reg = <0x00 0x20 0x100 0x80>;
89 reg = <0x20 0x20 0x200 0x80>;
95 reg = <0x40 0x20 0x300 0x80>;
101 reg = <0x60 0x20 0x500 0x80>;
Dqoriq-sec5.0-0.dtsi83 reg = <0x00 0x20 0x100 0x80>;
89 reg = <0x20 0x20 0x200 0x80>;
95 reg = <0x40 0x20 0x300 0x80>;
101 reg = <0x60 0x20 0x500 0x80>;
Dqoriq-sec5.2-0.dtsi89 reg = <0x00 0x20 0x100 0x80>;
96 reg = <0x20 0x20 0x200 0x80>;
103 reg = <0x40 0x20 0x300 0x80>;
110 reg = <0x60 0x20 0x500 0x80>;
Dqoriq-sec5.3-0.dtsi89 reg = <0x00 0x20 0x100 0x80>;
96 reg = <0x20 0x20 0x200 0x80>;
103 reg = <0x40 0x20 0x300 0x80>;
110 reg = <0x60 0x20 0x500 0x80>;
/arch/powerpc/boot/dts/
Dsbc8548-pre.dtsi36 d-cache-line-size = <0x20>; // 32 bytes
37 i-cache-line-size = <0x20>; // 32 bytes
Dksi8560.dts82 cache-line-size = <0x20>; /* 32 bytes */
159 reg = <0x520 0x20>;
197 reg = <0x520 0x20>;
254 reg = <0x91a00 0x20 0x88000 0x100>;
266 reg = <0x91a20 0x20 0x88100 0x100>;
292 reg = <0x91300 0x20 0x88400 0x100 0x91390 0x1>;
296 interrupts = <0x20 0x8>;
Dmpc8272ads.dts68 reg = <0x1 0x0 0x20>;
158 reg = <0x11a00 0x20 0x8000 0x100>;
169 reg = <0x11a60 0x20 0x8300 0x100>;
211 reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
224 reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
236 reg = <0x11860 0x20 0x8afc 0x2>;
Dep8248e.dts137 reg = <0x11a80 0x20 0x87fc 2>;
150 reg = <0x11a00 0x20 0x8000 0x100>;
162 reg = <0x11300 0x20 0x8400 0x100 0x11390 1>;
175 reg = <0x11320 0x20 0x8500 0x100 0x113b0 1>;
Dmgcoge.dts142 reg = <0x11a90 0x20 0x88fc 0x02>;
154 reg = <0x11a60 0x20 0x8300 0x100 0x11390 1>;
166 reg = <0x11860 0x20 0x8afc 0x2>;
195 reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
208 reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
Dpq2fads.dts68 reg = <0x1 0x0 0x20>;
157 reg = <0x11a00 0x20 0x8000 0x100>;
168 reg = <0x11a20 0x20 0x8100 0x100>;
179 reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
191 reg = <0x11340 0x20 0x8600 0x100 0x113d0 0x1>;
Dmpc5125twr.dts39 d-cache-line-size = <0x20>; // 32 bytes
40 i-cache-line-size = <0x20>; // 32 bytes
166 reg = <0x1700 0x20>;
176 reg = <0x1720 0x20>;
186 reg = <0x1740 0x20>;
Dvirtex440-ml507.dts44 d-cache-line-size = <0x20>;
49 i-cache-line-size = <0x20>;
111 xlnx,mplb-awidth = <0x20>;
188 xlnx,mch-native-dwidth = <0x20>;
190 xlnx,mch-splb-awidth = <0x20>;
204 xlnx,mem1-width = <0x20>;
205 xlnx,mem2-width = <0x20>;
206 xlnx,mem3-width = <0x20>;
397 xlnx,count-width = <0x20>;
Dvirtex440-ml510.dts39 d-cache-line-size = <0x20>;
44 i-cache-line-size = <0x20>;
106 xlnx,mplb-awidth = <0x20>;
159 xlnx,mch-native-dwidth = <0x20>;
161 xlnx,mch-splb-awidth = <0x20>;
175 xlnx,mem1-width = <0x20>;
176 xlnx,mem2-width = <0x20>;
177 xlnx,mem3-width = <0x20>;
424 reg = <1 0x20 2
458 xlnx,mplb-awidth = <0x20>;
[all …]
/arch/mips/boot/dts/mti/
Dsead3.dts150 mask = <0x20>;
199 mask = <0x20>;
224 reg = <0x1f000900 0x20>;
238 reg = <0x1f000800 0x20>;
/arch/mips/boot/dts/brcm/
Dbcm63268.dtsi68 reg = <0x10000020 0x20>,
69 <0x10000040 0x20>;

12345678910>>...12