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Searched refs:ADDR_SURF_BANK_HEIGHT_4 (Results 1 – 25 of 30) sorted by relevance

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/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c414 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()
424 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()
434 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()
444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()
484 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()
514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()
554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()
594 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()
604 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()
654 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()
[all …]
Dgfx_v8_0.c2253 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()
2257 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()
2261 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()
2265 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()
2285 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()
2289 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()
2444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()
2448 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()
2452 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()
2456 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()
[all …]
Dgfx_v7_0.c1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()
1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()
1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()
1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()
1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()
1546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()
/drivers/gpu/drm/radeon/
Dsi.c2518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()
2527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()
2536 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()
2545 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()
2581 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()
2608 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()
2644 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()
2680 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()
2689 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()
2733 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()
[all …]
Dcik.c2465 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()
2493 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()
2608 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()
2640 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()
2833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()
2865 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()
2869 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()
2976 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()
3008 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()
3012 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()
Dsid.h1214 # define ADDR_SURF_BANK_HEIGHT_4 2 macro
Dcikd.h1270 # define ADDR_SURF_BANK_HEIGHT_4 2 macro
Devergreend.h2225 # define ADDR_SURF_BANK_HEIGHT_4 2 macro
/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_8_2_enum.h966 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
Dgmc_8_1_enum.h1096 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_5_1_enum.h966 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
Dbif_5_0_enum.h1096 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_8_0_enum.h966 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
Dsmu_7_1_0_enum.h1125 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
Dsmu_7_1_1_enum.h1126 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
Dsmu_7_1_2_enum.h1144 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
Dsmu_7_1_3_enum.h1180 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_enum.h1051 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
Ddce_10_0_enum.h1671 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_enum.h979 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
Duvd_5_0_enum.h1109 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_enum.h1261 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
Doss_3_0_1_enum.h1362 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
Doss_3_0_enum.h1395 ADDR_SURF_BANK_HEIGHT_4 = 0x2, enumerator
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h1212 # define ADDR_SURF_BANK_HEIGHT_4 2 macro

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